TWI583003B - Semiconductor devices - Google Patents

Description

Semiconductor component

The invention relates to a way of placing a circuit layout, in particular to a way of placing a circuit layout of a diode.

As the functions of electronic devices continue to change, so does the power consumption. For example, in the case of a diode, as the power consumption increases, the driving of the diode also increases. However, the driving current of the diode is proportional to the circumference of the junction, so that the area of the diode is bound to increase. Therefore, how to effectively use the area to increase the effective junction perimeter of the diode has become an urgent problem to be solved.

In view of this, the present invention provides a semiconductor device including: a plurality of first wires and a plurality of second wires. Each of the first wires described above forms a closed polygon and surrounds a center. Each of the second wires described above forms the closed polygon and surrounds the center. The first wire and the second wire are interlaced with each other, and neither of the first wire and the second wire are connected.

According to an embodiment of the invention, the method further includes: a plurality of third wires and a plurality of fourth wires. The third wire is located above the first wire and the second wire, and radiates outward from the center. The fourth wire is located above the first wire and the second wire, and radiates outward from the center.

According to an embodiment of the invention, the third wire and the fourth wire are staggered and not connected to each other, wherein the third wire and the fourth wire are equally divided into the closed polygon.

According to an embodiment of the present invention, the third wire intersects the center and a first connection point, and the fourth wire intersects with a second connection point, wherein the first connection point and the second connection point are located above The first wire and the second wire are formed by the closed polygon formed by the second wire.

According to an embodiment of the present invention, the method further includes: a plurality of fifth wires and a plurality of sixth wires. The fifth wire overlaps with the first wire and is located above the first wire, wherein the fifth wire is coupled to the third wire, and the fifth wire and the fourth wire have a predetermined gap. The sixth wire overlaps with the second wire and is located above the second wire, wherein the sixth wire is coupled to the fourth wire, and the predetermined gap is formed between the fifth wire and the third wire.

According to an embodiment of the invention, the fifth lead wire is electrically connected to the first wire, and the sixth wire is electrically connected to the second wire.

According to an embodiment of the invention, the closed polygon is a regular polygon, a circle or an ellipse.

According to an embodiment of the invention, the first wire is coupled to a diode-P-doped layer, and the second wire is coupled to one of the diodes.

According to an embodiment of the invention, the first wire is a diode positive terminal, and the second wire is a diode negative terminal.

10, 20, 30, 40‧‧‧ diodes

11‧‧‧P type doped layer

12‧‧‧N-doped layer

21, 31‧‧‧ first wire

22, 32‧‧‧ second wire

23, 33, 43 ‧ ‧ Center

41‧‧‧ Third wire

42‧‧‧fourth wire

44‧‧‧ fifth wire

45‧‧‧6th wire

1 is a cross-sectional view showing a diode according to an embodiment of the present invention; FIG. 2 is a top view showing a diode according to an embodiment of the present invention; and FIG. 3 is a view showing A top view of a diode according to another embodiment of the present invention; and a fourth view showing a top view of a diode wire connection according to an embodiment of the present invention.

The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims appended claims A good example. It is to be understood that the invention is not limited to the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a diode according to an embodiment of the present invention. As shown in FIG. 1 , the diode 10 includes a P-type doped layer 11 and an N-type doped layer 12 . The P-type doped layer 11 is coupled to the first conductive line 21 , and the N-type doped layer 12 is coupled to the first Two wires 22. According to an embodiment of the invention, the diode 10 is a Schottky diode; according to another embodiment of the invention, the diode 10 is a fast recovery diode (fast recovery) Diode).

Fig. 2 is a top view showing a diode according to an embodiment of the present invention. As shown in FIG. 2, the diode 20 includes a plurality of first wires 21 and a plurality of second wires 22, each of the first wires 21 and the second wires 22 forming a closed polygon, and the first wires 21 and Each of the two wires 22 surrounds the center 23.

According to an embodiment of the invention, the first wire 21 is stacked on the P-type doped layer and coupled to the P-type doped layer, and the second wire 22 is stacked on the N-type doped layer and coupled to N-type doped layer. According to another embodiment of the present invention, the first wire 21 is stacked on the N-type doped layer and coupled to the N-type doped layer, and the second wire 22 is stacked on the P-type doped layer and coupled To the P-type doped layer.

According to an embodiment of the invention, the closed polygon is a regular quadrilateral, a regular hexagon, a regular octagon, a regular hexagon, a circle, an ellipse or any other regular polygon. According to another embodiment of the invention, the closed polygon may be any other enclosed graphic. According to the embodiment of Fig. 1, the first wire 21 and the second wire 22 are formed to be concentric circles around the center 23.

As shown in FIG. 2, the first wire 21 and the second wire 22 are interlaced with each other, and the first wire 21 and the second wire 22 of either of them are not connected to each other. According to an embodiment of the invention, a second wire 22 is inserted in the middle of each of the two first wires 21, and the outermost ring is the first wire 21. According to another embodiment of the present invention, the outermost ring is the second wire 22, and a first wire 21 is inserted between each of the two second wires 22.

According to an embodiment of the invention, the first wire 21 and the second wire 22 comprise a wire pitch, and the minimum wire pitch is determined according to a design rule of the semiconductor process. According to one of the inventions In the embodiment, since the first wire 21 and the second wire 22 respectively represent the positive terminal and the negative terminal of the diode 20, the first wire 21 and the second wire 22 are not connected to prevent a short circuit from occurring.

Figure 3 is a top view showing a diode according to another embodiment of the present invention. As shown in FIG. 3, the diode 30 includes a plurality of first wires 31 and a plurality of second wires 32, wherein each of the first wires 31 and the second wires 32 form an ellipse, and the first wires 31 and Each of the second wires 32 surrounds the center 33.

According to an embodiment of the invention, the first wire 31 is stacked on the P-type doped layer and coupled to the P-type doped layer, and the second wire 32 is stacked on the N-type doped layer and coupled to N-type doped layer. According to another embodiment of the present invention, the first wire 31 is stacked on the N-type doped layer and coupled to the N-type doped layer, and the second wire 32 is stacked on the P-type doped layer and coupled To the P-type doped layer.

As shown in FIG. 3, the first wire 31 and the second wire 32 are mutually staggered, and the first wire 31 and the second wire 32 of either of them are not connected to each other. According to an embodiment of the present invention, a second wire 22 is inserted in the middle of each of the two first wires 31, and the outermost ring is the first wire 31. According to another embodiment of the present invention, the outermost ring is the second wire 32, and a first wire 31 is inserted between each of the two second wires 32.

According to an embodiment of the invention, the first wire 31 and the second wire 32 comprise a wire pitch, and the minimum wire pitch is determined according to a design rule of the semiconductor process. According to an embodiment of the present invention, since the first wire 31 and the second wire 32 respectively represent the positive terminal and the negative terminal of the diode 30, the first wire 31 and the second wire 32 are not connected. Connect to prevent a short circuit.

Figure 4 is a top plan view showing a diode wire connection in accordance with an embodiment of the present invention. In order to explain the technical features of the present invention in detail, the fourth drawing will be described with reference to FIG. As shown in FIG. 4, the diode 40 further includes a plurality of third wires 41, a plurality of fourth wires 42, a plurality of fifth wires 44, and a plurality of sixth wires 45, wherein the third wire 41, the fourth wire 42, and the fifth wire 44 and the sixth conductor 45 are located above the first wire 21 and the second wire 22 of FIG.

According to an embodiment of the invention, the third wire 41 and the fourth wire 42 both radiate outwardly from the center 43 and the third wire 41 and the fourth wire 42 are not connected to each other. According to an embodiment of the present invention, the third wire 41 and the fourth wire 42 are equally divided into concentric circles surrounded by the first wire 21 and the second wire 22 of FIG.

As shown in FIG. 4, the diode 40 has three third wires 41 and three fourth wires 42, wherein the third wire 41 and the fourth wire 42 divide the diode 40 into six equal parts. According to other embodiments of the present invention, the third wire 41 and the fourth wire 42 can arbitrarily divide the closed polygon surrounded by the first wire 21 and the second wire 22 of FIG.

The fifth wire 44 is overlapped with the first wire 21 of FIG. 2, and the fifth wire 44 is located above the first wire 21 of FIG. 2, and the fifth wire 44 is electrically connected to the first wire 21 of FIG. The first connection 44 is coupled to the third conductor 41 and has a predetermined gap between the fifth conductor 44 and the fourth conductor 42. According to an embodiment of the invention, the minimum value of the predetermined gap is determined according to a design rule of the semiconductor process.

The sixth wire 45 is overlapped with the second wire 22 of FIG. 2, and the sixth wire 45 is located above the second wire 22 of FIG. 2, and the sixth wire 45 is electrically connected to the second wire 22 of FIG. The sixth connection 45 is coupled to the fourth conductor 42 and has a predetermined gap between the sixth conductor 45 and the third conductor 41. According to an embodiment of the invention, the minimum value of the predetermined gap is determined according to a design rule of the semiconductor process.

As shown in FIG. 4, the third wire 41 is coupled to the center 43. According to another embodiment of the invention, the fourth wire 42 is coupled to the center 43. According to an embodiment of the present invention, the third wire 41 and the fourth wire 42 are respectively connected to the first connection point and the second outside the closed polygon surrounded by the first wire 21 and the second wire 22 of FIG. Junction.

According to an embodiment of the present invention, the first wire 21 of FIG. 2 is coupled to the P-type doping layer 11 of FIG. 1 , and the second wire 22 is coupled to the N-type doping layer 12, thus When the wire 41 is coupled to the first connection point and the fourth wire is coupled to the second connection point, the first connection point is coupled to the P-type doped layer 11 and the second connection point is coupled to the N-type doped layer 12 Therefore, the first connection point can serve as the positive terminal of the diode, and the second connection point can serve as the negative terminal of the diode. According to another embodiment of the present invention, the first connection point and the second connection point can be used as one of the positive terminal of the diode and the negative terminal of the diode by changing the connection mode.

According to an embodiment of the present invention, the first wire 21 and the second wire 22 shown in FIG. 2 and the first wire 31 and the second wire 32 shown in FIG. 3 are located in the first metal layer in the semiconductor process ( Metal-1 layer), wherein the first wire 21 and the second wire 22 or the first wire 31 and the second wire 32 are respectively coupled to the P-type doped layer 11 and the N-type doped layer via contacts 12.

According to another embodiment of the present invention, the first wire 21 and the second wire 22 shown in FIG. 2 are located in the first metal layer in the semiconductor process, wherein the first wire 21 and the second wire 22 may also pass through the contact point. (contact), respectively coupled to the N-type doped layer 12 and the P-type doped layer 11.

According to an embodiment of the present invention, the third wire 41, the fourth wire 42, the fifth wire 44, and the sixth wire 45 of FIG. 4 are located in a top metal layer in a semiconductor process, wherein the third wire 41. The fourth wire 42, the fifth wire 44, and the sixth wire 45 are formed by a via layer, respectively, with the first wire 21 or the second wire 22 of FIG. 2 or the first wire 31 or the third wire of FIG. The two wires 32 are connected.

According to another embodiment of the present invention, the metal layer used for the third wire 41, the fourth wire 42, the fifth wire 44, and the sixth wire 45 of FIG. 4 is any metal layer of the first metal layer or more. According to another embodiment of the present invention, the first wire 21 and the second wire 22 shown in FIG. 2 and the first wire 31 and the second wire 32 shown in FIG. 3 are not limited to use any metal layer, and That is, the third wire 41, the fourth wire 42, the fifth wire 44, and the sixth wire 45 are located in the first wire 21 and the second wire 22 shown in FIG. 2, and the first wire 31 and the second wire shown in FIG. Just above the wire 32.

According to an embodiment of the present invention, the layout of the second, third, and fourth embodiments can also be applied to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

The features of many embodiments are described above to enable those of ordinary skill in the art to clearly understand the form of the specification. Those of ordinary skill in the art will understand that it can be based on the disclosure of the present invention. The same objectives and/or advantages of the above-described embodiments are achieved by designing or modifying other processes and structures. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

20‧‧‧ diode

21‧‧‧First wire

22‧‧‧second wire

23‧‧‧ Center

Claims (9)

A semiconductor device comprising: a plurality of first wires, wherein each of the first wires forms a closed polygon and surrounds a center; and a plurality of second wires, wherein each of the second wires forms the above-mentioned closed a polygon, and surrounding the center, wherein the first wire and the second wire are interdigitated, and any one of the first wire and the second wire are not connected. The semiconductor device of claim 1, further comprising: a plurality of third wires located on the first wire and the second wire, and extending outward from the center; and a plurality of fourth wires located at And above the first wire and the second wire, and radiating outward from the center. The semiconductor device according to claim 2, wherein the third wire and the fourth wire are staggered and not connected to each other, wherein the third wire and the fourth wire are equally divided into the closed polygon. The semiconductor device of claim 3, wherein the third wire intersects the center and a first connection point, and the fourth wire intersects with a second connection point, wherein the first connection point and the first The two connection points are located outside the closed polygon formed by the first wire and the second wire. The semiconductor component as described in claim 3, further comprising: a plurality of fifth wires overlapping the first wire and located above the first wire, wherein the fifth wire is coupled to the third wire, and the fifth wire and the fourth wire have a predetermined gap; And a plurality of sixth wires overlapping the second wire and located above the second wire, wherein the sixth wire is coupled to the fourth wire, and the predetermined gap is formed between the fifth wire and the third wire . The semiconductor device according to claim 5, wherein the fifth wire is electrically connected to the first wire, and the sixth wire is electrically connected to the second wire. The semiconductor device according to claim 1, wherein the closed polygon is a regular polygon, a circle or an ellipse. The semiconductor device of claim 1, wherein the first wire is coupled to a diode-P-doped layer, and the second wire is coupled to one of the diodes. Miscellaneous layer. The semiconductor device of claim 8, wherein the first wire is a diode positive terminal and the second wire is a diode negative terminal.