JP2013041994A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve, in a small area, a structure that relaxes the electric-field strength around a power semiconductor element.SOLUTION: In a peripheral region Q, a plurality of polycrystalline silicon layers 70 are provided between a source region 30 and an end drain electrode 41 via a peripheral interlayer insulating layer (an insulating layer) between the polycrystalline silicon layers 70 and a semiconductor layer. In the polycrystalline silicon layers 70, inclination portions in which their longitudinal direction are inclined from the horizontal direction (the inclination angle is θ, where 0<θ<90°) are provided. In the inclination portions of the polycrystalline silicon layers 70, a plurality of p-type regions 71 and n-type regions 72 are alternately formed in the longitudinal direction.

Description

  The present invention relates to a structure of a semiconductor device that operates by applying a high voltage.

  In a power semiconductor element that operates by applying a high voltage and flowing a large current, a high voltage is applied between the electrodes. For this reason, a structure in which the withstand voltage between the electrodes is sufficiently high is employed.

  In general, breakdown occurs where the potential gradient locally increases when a high voltage is applied. For this reason, in order to increase the withstand voltage, it is effective to adopt a structure in which a portion where the potential gradient (electric field strength) becomes large does not occur locally. For this reason, generally, a reverse conductivity type layer (guard ring) or the like surrounding the active region in a ring shape is used.

  For example, Patent Document 1 describes an IGBT (Insulated Gate Bipolar Transistor) having such a structure. This IGBT describes a configuration in which an annular guard ring that surrounds multiple active regions (regions where emitters and gates are formed) is provided. With this guard ring, local electric field strength can be relaxed in the in-plane direction near the surface. Further, by optimizing the cross-sectional shape of the diffusion layer in the lower part of the emitter region, a portion where the potential gradient locally increases inside the semiconductor layer is removed. Thereby, the breakdown voltage in the IGBT can be improved. Such a structure is not limited to the IGBT, but has the same structure, and the same applies to a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that requires a withstand voltage.

JP 2008-277352 A

  In the configuration using the guard ring, a depletion layer is formed at the interface between the semiconductor layer and the guard ring (reverse conductivity type layer) formed therein, and this depletion layer may exist in the lateral direction. Contributes to the relaxation of the electric field strength. However, a region that is not depleted in the semiconductor layer or the reverse conductivity type layer does not contribute to the relaxation of the electric field strength. For this reason, when the electric field strength is relaxed using such a reverse conductivity type layer, a region which does not originally contribute to the relaxation of the electric field strength is simultaneously formed. For this reason, the area occupied by the guard ring is increased because it is necessary for relaxation of the electric field strength. That is, in order to ensure a sufficient breakdown voltage, it is necessary to form the guard ring over a wide area.

  That is, in a power semiconductor element, it has been difficult to realize a structure for relaxing the electric field strength in the periphery with a small area.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention has a substantially rectangular ring-shaped peripheral region that surrounds the active region in plan view outside the active region that is formed in a semiconductor layer and has a substantially rectangular shape in plan view. In the peripheral region, one end of one side of the substantially rectangular shape is connected to one of the two electrodes in the peripheral region, and the outer one of the substantially rectangular ring shape parallel to the one side. A plurality of polycrystalline silicon layers extending toward the side and having the other end connected to the other of the two electrodes on the outer side are formed with an insulating layer interposed between the semiconductor layers. The polycrystalline silicon layer includes an inclined portion extending in a linear shape in which an angle between a longitudinal direction and one side of the substantially rectangular shape is θ (0 <θ <90 °), A plurality of pn junctions in the inclined portion are It is formed so as countercurrent and the pn junction interface are vertical the inclined portion at a plurality of said polycrystalline silicon layer is characterized by comprising a structure which is formed in parallel.
The semiconductor device of the present invention is characterized in that, in the inclined portion, the pn junction interface is periodically formed in the longitudinal direction.
The semiconductor device according to the present invention is characterized in that the pn junction interface forms the same straight line at a location where the inclined portions of the plurality of polycrystalline silicon layers are parallel to each other.
In the semiconductor device of the present invention, the plurality of polycrystalline silicon layers include the two inclined portions corresponding to two intersecting sides in the substantially rectangular shape, and a curved shape between the two inclined portions. And has two parallel portions extending linearly in parallel with each of the two intersecting sides between each of the two inclined portions and the curved portion. It is characterized by that.
In the semiconductor device of the present invention, the curved portions of the plurality of adjacent polycrystalline silicon layers have arc shapes each having a different curvature radius and having substantially the same curvature center.
In the semiconductor device of the present invention, the curved portions of the plurality of adjacent polycrystalline silicon layers have arc shapes having substantially the same radius of curvature and different curvature centers.
The semiconductor device of the present invention is characterized in that, in the parallel portion, a pn junction is formed such that a direction in which the parallel portion extends and a pn junction interface are perpendicular to each other.
In the semiconductor device of the present invention, the semiconductor element is a power MOSFET (Metal Oxide Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor).
In the semiconductor device of the present invention, one of the two electrodes is a source electrode in the power MOSFET or an emitter electrode in the IGBT,
The other of the two electrodes is a drain electrode in the power MOSFET or a collector electrode in the IGBT.
In the semiconductor device of the present invention, the breakdown voltage between the two electrodes in the semiconductor element is Vds, the number of pn junctions formed in one polycrystalline silicon layer is Nz, and the breakdown voltage of the pn junction is Vz. In this case, Vds <Vz × Nz.
In the semiconductor device of the present invention, one of the two electrodes is a gate electrode in the power MOSFET or a gate electrode in the IGBT,
The other of the two electrodes is a drain electrode in the power MOSFET or a collector electrode in the IGBT.
In the semiconductor device of the present invention, the breakdown voltage between the two electrodes in the semiconductor element is Vds, the number of pn junctions formed in one polycrystalline silicon layer is Nz, and the breakdown voltage of the pn junction is Vz. In this case, Vds> Vz × Nz.

  Since the present invention is configured as described above, in the power semiconductor element, a structure for relaxing the peripheral electric field strength can be realized with a small area.

It is the block diagram seen from the upper surface of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the semiconductor element formed in the active region of the semiconductor device which concerns on embodiment of this invention. It is a top view of the structure of the peripheral region of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the peripheral region of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows typically the condition of the depletion layer formed in a polycrystalline-silicon layer. It is a top view of the structure in the corner | angular part of the peripheral region of the semiconductor device which concerns on embodiment of this invention. It is a top view of the modification of the structure of the peripheral region of the semiconductor device which concerns on embodiment of this invention. It is a top view of the modification of the structure in the corner | angular part of the peripheral region of the semiconductor device which concerns on embodiment of this invention. It is a top view of the modification of the structure in the parallel part of the peripheral region of the semiconductor device which concerns on embodiment of this invention. It is two types of equivalent circuits of the semiconductor device which concerns on embodiment of this invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is a power MOSFET, and in particular, there are places where the potential gradient (electric field strength) locally increases around the active region of the power MOSFET (the region where the gate and the channel under the gate are formed). A difficult structure is formed.

  FIG. 1 is a configuration diagram of the power MOSFET (semiconductor device) 10 as viewed from above. The power MOSFET 10 has a substantially rectangular shape, and an active region P having a substantially rectangular shape is formed in the center in a plan view. In the active region P, a plurality of gate electrodes 20 are formed on the semiconductor layer 50, and a source electrode 30 insulated from the gate electrode 20 is formed around the gate electrode 20. The plurality of gate electrodes 20 are connected in parallel by gate connection electrodes 21. On the other hand, a drain electrode is formed on the entire lower surface. Thereby, in the active region P, a plurality of power MOSFET elements (semiconductor elements) connected in parallel are formed. Here, the outer shape of the source electrode 30 is equal to the shape of the active region P.

  FIG. 2 is a cross-sectional view in the AA direction (direction perpendicular to the longitudinal direction of the gate electrode 20) in FIG. This power MOSFET element is a planar gate type, and a gate is formed on the surface of a semiconductor layer via a gate oxide film.

The semiconductor layer 50 in this structure is formed of silicon, and an n ⁻ (n-type with low impurity concentration) layer 52 is formed on an n ⁺ (high-impurity concentration n-type) substrate 51 that functions as a drain. A gate electrode 20 is formed on the n ⁻ layer 52 via a gate oxide film 60. The gate electrode 20 can be made of, for example, conductive polycrystalline silicon. A p layer 53 is formed in the semiconductor layer 50 (n ⁻ layer 52) on both sides of the gate electrode 20, and an n ⁺ layer 54 that functions as a source is further formed in the p layer 53. A source electrode 30 is formed on the upper surface of this structure via an interlayer insulating layer 61 so as to be insulated from the gate electrode 20. Source electrode 30 is connected to the surfaces of n ⁺ layer 54 and p layer 53.

On the other hand, a drain electrode 40 is formed on the lower surface of the n ⁺ substrate 51. Further, as described above, the gate connection electrode 21 is formed on the upper surface side in a state where the insulating property between the source electrode 30 and the interlayer insulating layer 61 is ensured. In this structure, the source electrode 30, the drain electrode 40, and the gate connection electrode 21 can be operated with the three electrode terminals of the MOSFET. In particular, a high voltage is applied between the source electrode 30 and the drain electrode 40, and a large current flows. In addition, the manufacturing method of each said layer, the material of each electrode, etc. are the same as that of what is generally known. The above structure is the same as that of a normal planar gate type MOSFET.

  As shown in FIG. 1, a substantially rectangular ring-shaped peripheral region Q surrounding the active region P in plan view is formed. A characteristic of the structure of the power MOSFET 10 is the structure in the peripheral region Q. A detailed top view of the region X in the peripheral region Q in FIG. 1 is shown in FIG. 3, and a sectional view in the CC direction is shown in FIG. The region X is a part of the peripheral region Q on the lower side of the active region P in FIG.

As described above, the source electrode 30 connected to the n ⁺ layer 54 and the p layer 53 is formed above the region X in FIG. On the other hand, an end n ⁺ layer 55 is formed on the lower side (end side) in FIG. 3, and an end drain electrode 41 is formed on the end n ⁺ layer 55. The potential of the end drain electrode 41 is the same as that of the n ⁻ layer 52, and this potential is the same as that of the drain electrode 40. That is, the source electrode 30 and the end drain electrode 41 are provided at the upper and lower ends of the region X, respectively. The potential difference between them is the potential difference between the source and drain during the operation of the power MOSFET 10.

  On the other hand, as shown in FIGS. 3 and 4, in the peripheral region Q, a plurality of polycrystalline silicon layers 70 are connected to the semiconductor layer 50 via the peripheral interlayer insulating layer (insulating layer) 62 from the source electrode 30. It is provided between the end drain electrodes 41. The longitudinal direction of the polycrystalline silicon layer 70 is inclined from the horizontal direction in FIG. 3 (the direction of a straight line constituting one side of the substantially rectangular active region P) (inclination angle θ, 0 <θ <90 °). An inclined portion is provided. The longitudinal directions of the inclined portions in the plurality of polycrystalline silicon layers 70 are parallel to each other. This polycrystalline silicon layer 70 is one of two electrodes (source electrode 30 and drain electrode 40) constituting a power MOSFET element on one side (upper side in FIG. 3) of a substantially rectangular shape corresponding to the active region P. It is connected to a certain source electrode 30. The polycrystalline silicon layer 70 extends to the outer side of the substantially rectangular ring shape corresponding to the peripheral region Q (parallel to one side of the substantially rectangular shape) via the inclined portion. One end side of the outer side is connected to the end drain electrode 41 which is the other of the two electrodes. In FIG. 3, constituent elements (peripheral interlayer insulating layer 62 and the like) other than the source electrode 30, the end drain electrode 41, and the polycrystalline silicon layer 70 are omitted. Further, as will be described later, one end of the polycrystalline silicon layer 70 may be connected to the gate electrode 20 (gate connection electrode 21) instead of the source electrode 30 in some cases.

  In the inclined portion of the polycrystalline silicon layer 70, a large number of conductive p-type regions 71 and conductive n-type regions 72 are alternately formed in the longitudinal direction. The p-type region 71 and the n-type region 72 are p-type and n-type conductivity types in the thickness direction of the polycrystalline silicon layer 70, respectively. As shown in FIG. 3, the pn junction interface formed by the boundary between the p-type region 71 and the n-type region 72 is periodically configured in plan view. Further, the pn junction interface is perpendicular to the longitudinal direction of the inclined portion of the polycrystalline silicon layer 70, and between the adjacent polycrystalline silicon layers 70, the p-type regions 71 and the n-type regions 72 are adjacent to each other. Is set. For this reason, the pn junction interfaces in the adjacent polycrystalline silicon layers 70 are set so as to form the same straight line.

  The operation of the polycrystalline silicon layer 70 during the operation of the power MOSFET 10 will be described. First, both ends of the polycrystalline silicon layer 70 are set to the same potential as the source electrode 30 (source) and the end drain electrode 41 (drain), respectively. For this reason, the potential difference between both ends of the polycrystalline silicon layer 70 during operation increases. However, since a large number of pn junctions are formed at equal intervals between the both ends, and a portion that is necessarily reverse-biased is generated in one period in each pn junction, each pn junction does not break down. In the state, the current flowing in the polycrystalline silicon layer 70 can be ignored regardless of the direction of the potential difference. That is, this polycrystalline silicon layer 70 can be regarded as an insulator. However, since the polycrystalline silicon layer 70 can be regarded as having substantially the same potential between the pn junctions that are reverse-biased, the potential between the source electrode 30 and the end drain electrode 41 is the reverse-biased pn junction ( Alternatively, it is equally divided into a large number by a depletion layer.

  On the other hand, as shown in FIG. 4, a MOS structure is formed by the polycrystalline silicon layer 70, the peripheral interlayer insulating layer (insulating layer) 62 under the polycrystalline silicon layer 70, and the semiconductor layer 50 (p layer 53). Therefore, the surface potential of the semiconductor layer 50 (p layer 53) is controlled by the local potential of the polycrystalline silicon layer 70. In the inclined portion of the polycrystalline silicon layer 70, since the potential is equally divided in the longitudinal direction, the surface potential of the p layer 53 is also equally divided. For this reason, local electric field concentration in the semiconductor layer 50 is suppressed in the longitudinal direction of the polycrystalline silicon layer 70.

  A large number of inclined portions of this configuration are provided in parallel, and in the region X in FIG. For this reason, electric field concentration can be suppressed over the entire surface of the semiconductor layer 50.

  It is clear that this effect increases as the number of pn junctions provided in each inclined portion increases. If the longitudinal direction of the polycrystalline silicon layer 70 is the vertical direction in FIG. 3 (the direction perpendicular to the direction of the straight line constituting the end portion of the active region), one polycrystalline silicon layer 70 is short. Therefore, in order to secure the number of pn junctions, it is necessary to make the p-type region 71 and the n-type region 72 sufficiently small. However, since the size of the p-type region 71 and the n-type region 72 is limited by the accuracy of lithography and the degree of impurity diffusion, it is difficult to make the p-type region 71 and the n-type region 72 small.

  On the other hand, in the configuration of FIG. 3, the individual polycrystalline silicon layers 70 are elongated by setting the longitudinal direction of the inclined portion provided in the polycrystalline silicon layer 70 to a direction slightly inclined from the horizontal direction. Even when the p-type region 71 and the n-type region 72 are set large (long), the number of pn junctions can be ensured. Since a large number of polycrystalline silicon layers 70 are provided in parallel at short intervals, the peripheral region Q is substantially covered with the polycrystalline silicon layer 70 substantially. Therefore, the potential of the semiconductor layer 50 (p layer 53) in the peripheral region Q is set in the polycrystalline silicon layer 70, and electric field concentration is suppressed.

  In addition, it is preferable that the pn junction interface at the boundary between the p-type region 71 and the n-type region 72 is perpendicular to the longitudinal direction of the polycrystalline silicon layer 70. FIG. 5 schematically shows the situation when a bias is applied to the polycrystalline silicon layer 70 in the case where the relationship between the direction of the pn junction interface and the longitudinal direction of the polycrystalline silicon layer 70 is different. Here, it is assumed that the impurity concentration is particularly high in the n-type region 72. For this reason, when a bias is applied, the depletion layer 73 is mainly formed on the p-type region 71 side having a low impurity concentration. The reverse characteristics (breakdown characteristics) of the pn junction are greatly affected by the form of the depletion layer 73.

As shown in the upper side of FIG. 5A, the pn junction interface is formed perpendicular to the longitudinal direction of the polycrystalline silicon layer 70, and a negative bias is applied to the upper right side and the lower left side in the figure. In FIG. 5A, the depletion layer 73 is formed symmetrically on both sides (both sides of the polycrystalline silicon layer 70) in the direction in which the pn junction interface extends. The length of the depletion layer 73 along the longitudinal direction of the polycrystalline silicon layer 70 (inclined portion) and D _0.

On the other hand, the same situation in the case where the pn junction is not formed perpendicular to the longitudinal direction of the polycrystalline silicon layer 70 is shown in FIG. In this case, since the relationship between the n-type region 72 having a high impurity concentration and the side surface of the polycrystalline silicon layer 70 is not symmetric on both sides in the direction in which the pn junction extends, the situation is different from FIG. . As shown in the lower side of FIG. 5B, the n-type region 72 does not exist on the upper right side of the pn junction on the upper left side of the pn junction. Since the depletion layer 73 is formed so that the total amount of donors and acceptors on both sides of the pn junction is equal, in order for the depletion layer 73 to be formed in an equilibrium state in this state, Becomes shorter. The length of the upper left law end of the depletion layer 73 along the longitudinal direction of the polycrystalline silicon layer 70 and D _1. On the other hand, since the lower right law end is in the opposite state, the depletion layer 73 becomes longer at the lower right law end. When the length of the lower right end of the depletion layer 73 along the longitudinal direction of the polycrystalline silicon layer 70 is D ₂ , D ₂ > D ₁ is satisfied. On the other hand, the situation in the middle between the upper left end and the lower right end is not different from the case of FIG. 5A, and therefore the length of the depletion layer 73 along the longitudinal direction of the polycrystalline silicon layer 70 is D ₀ . Become. That is, the depletion layer 73 is formed in a form in which D ₁ <D ₀ <D ₂ .

Since the voltage applied across the depletion layer 73 is the same as in FIGS. 5 (a) to right rule ends left law ends, at a point the length of the shortest length D ₁ of the depletion layer 73 Has the highest electric field strength and is easy to break down. For this reason, in the case of the configuration of FIG. 5B, breakdown is easily caused at the upper left end, and the breakdown voltage of the polycrystalline silicon layer 70 is lowered. On the other hand, when the pn junction is formed perpendicular to the longitudinal direction of the polycrystalline silicon layer 70 as shown in FIG. 5A, such asymmetry does not occur, and the breakdown voltage can be increased.

  When the length in the vertical direction (distance between the source and the drain) of the polycrystalline silicon layer 70 in FIG. 3 is L and the inclination angle of the polycrystalline silicon layer 70 from the horizontal direction is θ, the polycrystalline silicon layer 70. The length in the longitudinal direction is L / sin θ. In the case where the number of pn junctions in one polycrystalline silicon layer 70 is Nz, the period of the pn junction is Zp, the breakdown voltage of a single pn junction is Vz, and the required breakdown voltage between the source and drain is Vds. / Vz≈Nz. That is, Nz may be set so that this condition is satisfied. As described above, in order to increase Nz, it is effective to reduce θ (however, θ ≠ 0). That is, sin θ <L / (Zp · Nz) may be satisfied.

  In the polycrystalline silicon layer 70, it is preferable that the polycrystalline silicon layer 70 is used as an insulator, that is, the current flowing between both ends during the normal operation of the power MOSFET can be ignored. For this purpose, it is preferable to set the length of the p-type region 71 so that the p-type region 71 and the n-type region 72 do not constitute a thyristor.

  The configuration of the peripheral region Q on the upper side of the active region P in FIG. 1 is a configuration obtained by rotating FIG. 3 clockwise by 180 °, and the configuration of the peripheral region Q on the left side of the active region P is shown in FIG. The configuration of the peripheral region Q on the right side of the active region P is 90 ° around, and is a configuration obtained by rotating FIG. 3 270 ° clockwise.

  A detailed top view of the region Y in the peripheral region Q in FIG. 1 is shown in FIG. The region Y is a connection portion between the peripheral region Q on the lower side of the active region P in FIG. 1 and the peripheral region Q on the left side of the active region P. Although not shown, a peripheral interlayer insulating layer (insulating layer) 62 is formed between the polycrystalline silicon layer 70 and the semiconductor layer 50 in the region Y as well as in the case of FIG. Yes.

  The configuration in the upper region of the region Y is a configuration obtained by rotating the configuration in FIG. 3 by 90 ° clockwise. For this reason, the extending direction of the plurality of polycrystalline silicon layers 70 in the region Y changes. However, when the polycrystalline silicon layer 70 is bent, an acute angle portion that is likely to cause electric field concentration is not generated. For this reason, the polycrystalline silicon layer 70 extended from the right side in FIG. 6 at the inclination angle θ is once changed in the horizontal direction in FIG. 6 (direction parallel to the straight line constituting the end of the active region). A parallel part is provided, and then a curved part with a predetermined radius of curvature is provided on the upper side in FIG. In FIG. 6, the parallel part in the polycrystalline silicon layer 70 which is the outermost part at the corner part is indicated by S, and the curved part is indicated by B. On the left side of the peripheral region Q, these polycrystalline silicon layers 70 are stretched with a straight line and an inclination angle θ constituting the left side of the active region P across a parallel portion parallel to the left side of the active region P. An inclined portion is provided.

  Each polycrystalline silicon layer 70 includes a curved portion that changes in a 90 ° direction in an arc shape in the lower left in FIG. 6. The curvature of the curved portion is set so as to increase from the inner polycrystalline silicon layer 70 toward the outer polycrystalline silicon layer 70. At this time, each center of curvature is set to be a fixed portion indicated by X in FIG.

  At this time, when a pn junction is formed in the curved portion, the same situation as in FIG. 5B is likely to occur. Therefore, it is preferable not to form the n-type region 72 in the curved portion. For this reason, this curved portion is constituted only by the p-type region 72. Therefore, the curved portion of each polycrystalline silicon layer 70 has a uniform potential. This potential is a potential obtained by dividing the potential from the source electrode 30 to the end drain electrode 41 in each polycrystalline silicon layer 70 by the pn junction. The surface potential of semiconductor layer 50 (p layer 53) has a value corresponding to this potential, and is constant immediately below the curved portion of each polycrystalline silicon layer 70.

  The polycrystalline silicon layer 70 having the above configuration can control the surface potential of the semiconductor layer 50 (p layer 53) and suppress electric field concentration. Here, as described above, a large number of pn junctions can be formed in the polycrystalline silicon layer 70 by forming inclined portions in the polycrystalline silicon layer 70. Thereby, even when the width of the peripheral region Q around the active region P is narrow, it is possible to provide many points in the peripheral region Q where the surface potential of the semiconductor layer 50 is controlled. For this reason, compared with the structure using the conventional guard ring, the area of the peripheral region Q where electric field intensity is reduced can be reduced, and the area of the entire chip can be reduced.

  In manufacturing the above configuration, the polycrystalline silicon layer 70 can be formed of polycrystalline silicon simultaneously with the gate electrode 20 after the gate oxide film 60 is formed. At this time, the oxide film under the polycrystalline silicon layer 70 and the oxide film under the gate electrode 20 can be made different by forming an additional oxide film locally in the peripheral region Q. The subsequent patterning of the polycrystalline silicon layer 70 can be performed simultaneously with the gate electrode 20.

Further, the p layer 53 is formed by ion implantation of boron or the like. If the ion implantation is performed simultaneously on the polycrystalline silicon layer 70 at this time, the entire polycrystalline silicon layer 70 is made p-type. Can do. Similarly, the n ⁺ layer 54 is formed by ion implantation of phosphorus or the like. At this time, if the ion implantation is selectively performed simultaneously in the region corresponding to the n-type region 72 in the polycrystalline silicon layer 70, A p-type region 71 and an n-type region 72 can be formed in the polycrystalline silicon layer 70. At this time, if the pn junction interface in the adjacent polycrystalline silicon layer 70 (inclined portion) forms the same straight line, the mask for forming the n-type region 72 in the peripheral region Q is a simple line and space. Pattern. For this reason, this manufacturing is particularly easy, and it is particularly easy to make each n-type region 72 small. Note that the end n ⁺ layer 55 can also be formed simultaneously with the n ⁺ layer 54.

  Further, the interlayer insulating layer 61 and the peripheral interlayer insulating layer 62 on the polycrystalline silicon layer 70 can be formed simultaneously. After the openings are formed in the interlayer insulating layer 61 and the peripheral interlayer insulating layer 62, the source electrode 30, the gate connection electrode 21, and the end drain electrode 41 can be simultaneously formed of a material such as Al. On the other hand, on the lower surface side, the drain electrode 40 can be similarly formed of a material such as Al.

  Thus, in the power MOSFET 10, a power MOSFET element having a normal structure is formed in the active region P, and the structure of the peripheral region Q is simultaneously formed in the manufacturing process for forming the power MOSFET element. be able to. That is, the power MOSFET 10 can be manufactured at a low cost.

  The configuration of the polycrystalline silicon layer 70 can be set as appropriate in addition to the above. For example, the configuration of the pn junction in the polycrystalline silicon layer 70 can be set as appropriate so that the electric field strength is relaxed. For this purpose, it is effective to partially disrupt the periodicity of the pn junction. There is also. FIG. 7 shows a configuration in which n-type regions 72 are reduced by two in the region near the source electrode 30 in the inclined portion of the polycrystalline silicon layer 70 as compared with the configuration of FIG. As described above, the n-type region 72 can be formed by ion implantation. However, such fine adjustment can be made by changing the pattern (mask pattern) of the n-type region 72 without changing the ion implantation conditions. The electric field distribution in the semiconductor layer 50 can be easily optimized.

  Various settings can also be made for the configuration of the curved portion of the polycrystalline silicon layer 70. For example, the configuration in the region Y can be as shown in FIG. In the case of this example, the radius of curvature at a location where the orientation of each polycrystalline silicon layer 70 changes by 90 ° is constant. Therefore, as shown by X in FIG. 8, the center of curvature of each polycrystalline silicon layer 70 is on the inner side in the inner polycrystalline silicon layer 70 and on the outer side in the outer polycrystalline silicon layer 70. Is set.

  As described above, since no pn junction is formed in the curved portion of each polycrystalline silicon layer 70, this curved portion has the same potential. For this reason, these shapes can be set as appropriate so that electric field concentration in the semiconductor layer 50 does not easily occur. That is, in the power MOSFET 10 described above, the electric field distribution near the corners in the semiconductor layer 50 can be optimized by appropriately setting the shape of the polycrystalline silicon layer 70 at the locations corresponding to the four corners.

  Further, as shown in FIG. 6, in the polycrystalline silicon layer 70, the inclined portion (θ ≠ 0 °) is connected to the curved portion via the parallel portion (θ = 0 °). As described above, it is preferable not to form a pn junction in the curved portion. However, by forming a pn junction in the parallel portion, the potential distribution of the semiconductor layer 50 immediately below the parallel portion and the potential of the curved portion are set. Can do. FIG. 9 is a diagram showing an example of this configuration. Here, an n-type region 72 is additionally formed in the parallel portion on the left end side and the parallel portion on the right end side in the polycrystalline silicon layer 70. Since the parallel portion is also linear like the inclined portion, the pn junction interface can be formed perpendicular to these straight lines, and the potential can be adjusted in the same manner as the inclined portion. As in the case of FIG. 5A, the electric field concentration in the polycrystalline silicon layer 70 is less likely to occur.

  In the above example, the potential distribution of the semiconductor layer 50 is adjusted by the polycrystalline silicon layer 70 (peripheral region Q), and the breakdown voltage between the source (S) and drain (D) of the power MOSFET is improved. On the other hand, the polycrystalline silicon layer 70 can also be considered as a series connection of Zener diodes connected between the source and the drain. In this case, an equivalent circuit of the power MOSFET is as shown in FIG. That is, a Zener diode (ZD) is connected between the source electrode terminal (S) and the drain electrode terminal (D). However, this Zener diode is configured by connecting a large number of Zener diodes in series in alternate directions. In this configuration, as described above, the breakdown voltage of the power MOSFET 10 is improved by providing the peripheral region Q. However, in which component will the breakdown between the source and the drain finally occur when a high voltage is applied? Can be set as appropriate. That is, it is possible to make two settings, that is, this breakdown occurs in the power MOSFET element in the active region P or (2) occurs in the polycrystalline silicon layer 70 in the peripheral region Q. In the case of (2), the peripheral region Q also functions as a protection element in the power MOSFET 10.

  When the breakdown is generated in (1) the power MOSFET element in the active region P, as described above, when the breakdown voltage of the power MOSFET element is Vds, Vds is the voltage at which the polycrystalline silicon layer 70 breaks down. What is necessary is just to set lower than VzxNz. That is, by setting Vds <Vz × Nz, breakdown can be generated in the power MOSFET element in the active region P. As described above, in order to obtain Nz satisfying this condition, the inclination angle θ may be set so that sin θ <L / (Zp · Nz). As described above, the breakdown voltage Vds is improved by the presence of the peripheral region Q.

  On the contrary, from the viewpoint of protecting the power MOSFET element, (2) a configuration in which breakdown occurs in the polycrystalline silicon layer 70 in the peripheral region Q is effective. Such characteristics are particularly preferable when the power MOSFET 10 is used as, for example, a switching element for engine ignition. As a standard in this case, Vds> Vz × Nz, contrary to the above case.

  However, in this case, it may be preferable in use that the overcurrent flowing through the polycrystalline silicon layer 70 does not flow through the source electrode terminal (S) but flows through the gate electrode terminal (G). The equivalent circuit configuration in this case can be as shown in FIG. That is, in the above example, one end of the Zener diode (ZD) is connected to the source electrode terminal (S), whereas this one end is connected to the gate electrode terminal (G). Specifically, one end of the polycrystalline silicon layer 70 connected to the source electrode 30 in the above example is connected to the gate connection electrode 21 instead. During normal use of the power MOSFET, the source electrode terminal (S) has a ground potential, the drain electrode terminal (D) has a high potential, and the gate electrode terminal (G) has a low potential (control potential) close to the ground potential. Also in this case, it is clear that the effect of improving the breakdown voltage can be obtained similarly. That is, the same breakdown voltage improving effect can be obtained, and the peripheral region Q functions as a protective element, and the overcurrent that has flowed through the protective element can flow to the gate electrode terminal (G).

  In the above setting, the withstand voltage Vz of a single pn junction in the polycrystalline silicon layer 70 is not easily adjusted. However, the setting of Nz is the adjustment of the patterning of the n-type region 72, that is, when the n-type region 72 is formed This mask pattern can be easily used. Accordingly, the above settings (1) and (2) can be easily performed without performing, for example, ion implantation conditions other than the mask pattern.

  In the above example, the case where the polycrystalline silicon layer having the above-described configuration is provided corresponding to all four sides of the active region P has been described. A polycrystalline silicon layer having the above structure may be provided.

  In the above configuration, it is clear that the same effect can be obtained even if the p-type and the n-type in the semiconductor layer and the polycrystalline silicon layer are reversed. Also, the method for forming the p-type region and the n-type region in the polycrystalline silicon layer is arbitrary.

  In the above configuration, a planar type power MOSFET element is formed in the active region P. However, even when a trench type power MOSFET element, an IGBT (Insulated Gate Bipolar Transistor) element, or the like is formed, It is clear that the same effect can be achieved. In the case of IGBT, it is the same as the above except that a p layer serving as a collector layer is provided on the lower surface side in the configuration of FIGS. 2 and 4 and a collector electrode is formed on the lower surface side. . In this case, if the gate electrode, source electrode, and drain electrode in the power MOSFET are replaced with the gate electrode, emitter electrode, and collector electrode in the IGBT, respectively, it is apparent that the same effect can be obtained. Similarly, the connection of the polycrystalline silicon layers can be performed so that the equivalent circuit of FIGS. 10A and 10B is realized, and the effect is also the same.

10 Power MOSFET (semiconductor device)
20 gate electrode 21 gate connection electrode 30 source electrode 40 drain electrode 41 ends the drain electrode 50 semiconductor layer 51 ^{n +} substrate 52 n ^- layer 53 p layer 54 ^{n +} layer 55 ends ^{the n +} layer 60 gate oxide film 61 interlayer insulating layer 62 Peripheral interlayer insulation layer (insulation layer)
70 polycrystalline silicon layer 71 p-type region 72 n-type region 73 depletion layer

Claims (12)

A semiconductor device in which a semiconductor element having two electrodes is formed in a semiconductor layer and has a substantially rectangular ring-shaped peripheral region surrounding the active region in plan view outside the active region that is substantially rectangular shape in plan view. And
In the peripheral region,
One end of one side of the substantially rectangular shape is connected to one of the two electrodes, extends toward one side of the outer side of the substantially rectangular ring shape parallel to the one side, and one side of the outer side A plurality of polycrystalline silicon layers whose other ends are connected to the other of the two electrodes, with an insulating layer interposed between the semiconductor layers,
The polycrystalline silicon layer includes an inclined portion extending in a linear shape in which an angle between a longitudinal direction and one side of the substantially rectangular shape is θ (0 <θ <90 °). A plurality of pn junctions are formed so that the longitudinal direction and the pn junction interface are perpendicular to each other, and the inclined portions are formed in parallel in the plurality of polycrystalline silicon layers. Semiconductor device.   The semiconductor device according to claim 1, wherein the inclined portion has a configuration in which the pn junction interface is periodically formed in a longitudinal direction.   3. The semiconductor device according to claim 1, wherein the pn junction interface is formed to form the same straight line at a portion where the inclined portions are parallel to each other in the plurality of polycrystalline silicon layers. . The plurality of polycrystalline silicon layers include two inclined portions corresponding to two intersecting sides in the substantially rectangular shape, and a curve that changes 90 ° in a curved shape between the two inclined portions. Comprising
4. Two parallel portions extending linearly in parallel with each of the two intersecting sides are provided between each of the two inclined portions and the curved portion. The semiconductor device according to any one of the above.   5. The semiconductor device according to claim 4, wherein the curved portions of the plurality of adjacent polycrystalline silicon layers have arc shapes each having a different curvature radius and having substantially the same curvature center.   5. The semiconductor device according to claim 4, wherein the curved portions of the plurality of adjacent polycrystalline silicon layers have arc shapes having substantially the same radius of curvature and different curvature centers.   The pn junction is formed in the parallel portion so that a direction in which the parallel portion extends and a pn junction interface are perpendicular to each other. Semiconductor device.   8. The semiconductor device according to claim 1, wherein the semiconductor element is a power MOSFET (Metal Oxide Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). 9. One of the two electrodes is a source electrode in the power MOSFET or an emitter electrode in the IGBT,
The semiconductor device according to claim 8, wherein the other of the two electrodes is a drain electrode in the power MOSFET or a collector electrode in the IGBT.   When the breakdown voltage between the two electrodes in the semiconductor element is Vds, the number of pn junctions formed in one polycrystalline silicon layer is Nz, and the breakdown voltage of the pn junction is Vz, Vds <Vz × The semiconductor device according to claim 9, wherein the semiconductor device is Nz. One of the two electrodes is a gate electrode in the power MOSFET or a gate electrode in the IGBT,
The semiconductor device according to claim 8, wherein the other of the two electrodes is a drain electrode in the power MOSFET or a collector electrode in the IGBT.   When the breakdown voltage between the two electrodes in the semiconductor element is Vds, the number of pn junctions formed in one polycrystalline silicon layer is Nz, and the breakdown voltage of the pn junction is Vz, Vds> Vz × The semiconductor device according to claim 11, wherein the semiconductor device is Nz.

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