TWI617934B - Data correcting apparatus, drawing apparatus, wiring pattern forming system, inspection apparatus, data correcting method and wiring substrate producing method - Google Patents

Abstract

The width between the mask element pairs (710) formed adjacent to each other on the film (8) of the substrate (9) is used as the mask gap width (G). For each of the plurality of mask gap widths, it is ready to be used. Reference information on the relationship between the mask element pair and the pattern element pair (810) to be formed on the film by etching the upper surface gap width (GT) between the upper surfaces and the lower surface gap width (GB) between the lower surfaces . The measured value of the gap width on the upper surface of each pattern element pair is obtained in a substrate completed by etching using a plurality of mask element pairs having a plurality of mask gap widths set. By using the measured value and referring to the reference information, the value of the surface gap width below the mask gap width is obtained, and the design data of the pattern of the film is corrected based on the value. Thereby, correction of design data based on the lower surface of the pattern of the film can be easily realized.

Description

Data correction device, drawing device, wiring pattern forming system, inspection device, data correction method, and manufacturing method of wiring substrate

The invention relates to a data correction device, a drawing device, a wiring pattern forming system, an inspection device, a data correction method, and a method for manufacturing a wiring substrate.

In the past, various processes have been performed on substrates in the manufacturing steps of printed substrates (hereinafter simply referred to as "substrates"). For example, a photoresist pattern is formed on the surface of a substrate on which a conductive film such as copper is formed, and etching is performed to form a pattern (wiring pattern) of the conductive film on the substrate. During the etching, the shape of the pattern formed on the substrate may be different from the design data due to the density of the arrangement of the pattern elements. Therefore, Japanese Patent Application Laid-Open No. 2001-230323 and Japanese Patent Application Laid-Open No. 2005-202949 disclose methods of calculating the final width of the wiring and correcting design data by numerical simulation.

However, among the pattern elements of the conductor film formed on the substrate, it is known that the cross-sectional shape is trapezoidal. Since an image of the upper surface of the pattern element can be easily obtained, the shape of the upper surface can also be easily measured using the image. On the other hand, the amount of light (reflected light of illumination light) obtained from the foot of the pattern element is insufficient, so measurement of the shape of the surface below the pattern element is not easy. Therefore, it is difficult to make the lower surface of the pattern of the conductor film a base. Correct the standard design data, or check the lower surface of the conductor film pattern as a reference.

The invention relates to a data correction device for correcting design data of a pattern formed by etching a conductive film formed on a surface of a substrate with an etchant.

The data correction device of the present invention includes: a design data storage unit that stores design data of the above-mentioned pattern of the conductive film formed on the substrate on which the conductive film is formed by etching under specific conditions; referring to the information storage unit, it stores information on the substrate The width of the gap between the mask element pairs formed adjacent to each other on the conductor film is used as the mask gap width. Reference information is stored for each of the plurality of mask gap widths, and the reference information indicates the use of the above mask element pairs. The relationship between the gap width between the upper surfaces of the pattern element pairs formed on the conductor film by etching, that is, the upper surface gap width, and the gap width between the lower surfaces of the pattern element pairs, that is, the lower surface gap width; The obtaining unit obtains a plurality of patterns corresponding to the plurality of mask element pairs in the processing-completed substrate using the plurality of mask element pairs each having the plurality of mask gap widths and performing the etching under the specific conditions. The measured value of the mask width on each of the element pairs, using the above measured value and referring to the above reference information For the above-mentioned processed substrate, the values of the plurality of lower surface gap widths of the plurality of mask gap widths are obtained; and the data correction unit is based on the values of the plurality of lower surface gap widths of the plurality of mask gap widths, Correct the above design information; and for each of the plurality of mask gap widths, a pattern element when the conductor film is etched along the surface from a state where the conductor film is etched to the surface of the substrate with a polynomial of time The shape change is formulated, and the coefficients of the polynomial are determined by fitting the measured values of the shape of the pattern elements of the test substrate subjected to the etching at a specific time to obtain the above reference information.

In the above-mentioned data correction device, it is possible to easily correct the design data using the lower surface of the pattern of the conductor film as a reference.

The measured value of the gap width on the upper surface of each of a plurality of pattern element pairs; the data correction unit uses the above-mentioned measured value for the above-mentioned mask gap width for each pattern element of the pattern on the target substrate, referring to the above design The reference information of the specific mask gap width of the data is obtained from the pattern shown in the inspection image data, and the shape of the lower surface of the pattern on the target substrate is obtained; and a defect detection section based on the correction section by the data The shape of the lower surface of the pattern obtained is used to detect the defects of the pattern on the target substrate; and each of the plurality of mask gap widths is etched from the conductor film to the surface of the substrate with a polynomial of time. After this state, the shape change of the pattern element when the conductor film is etched along the surface is formulated, and determined by fitting the measured value of the shape to the pattern element of the test substrate subjected to the etching at a specific time. The coefficient of the above polynomial to obtain the above reference information.

In the inspection device described above, inspection can be easily performed with the lower surface of the pattern of the conductor film as a reference.

The present invention also relates to a data correction method for correcting design data of a pattern formed by etching a conductive film formed on a surface of a substrate with an etchant, and a method for manufacturing a wiring substrate.

The above-mentioned objects and other objects, features, aspects, and advantages will be made clear by the following detailed description of the present invention with reference to the accompanying drawings.

1‧‧‧ depicting device

2‧‧‧ Data Processing Device

3‧‧‧ exposure device

4‧‧‧Inspection device

8‧‧‧Conductor film

9‧‧‧ substrate

10‧‧‧Wiring pattern forming system

11‧‧‧Drawing data production agency

12‧‧‧ Depicting agencies

13‧‧‧Development Agency

14‧‧‧Wiring pattern forming mechanism

15‧‧‧ inspection agency

16‧‧‧ amending agency

19‧‧‧ Design Information Production Agency

21‧‧‧Data Correction Device

22‧‧‧Data Conversion Department

31‧‧‧Drawing controller

32‧‧‧ carrier

33‧‧‧light emitting section

35‧‧‧scanning agency

41‧‧‧Design Data Memory Department

42‧‧‧Reference Information Memory Department

43‧‧‧Actual image memory section

44‧‧‧ Upper surface gap width acquisition section

45‧‧‧Data Correction Department

46‧‧‧Defect Inspection Department

71‧‧‧Mask pattern

201‧‧‧CPU

202‧‧‧ROM

203‧‧‧RAM

204‧‧‧ fixed disk

205‧‧‧Display

207‧‧‧Read / Write Device

208‧‧‧Ministry of Communications

211‧‧‧Design Data Memory Department

212‧‧‧Reference Information Generation Department

213‧‧‧Reference Information Memory

214‧‧‧Low surface etching amount acquisition section

216‧‧‧Data Correction Department

331‧‧‧light source

332‧‧‧Light Modulation Department

710‧‧‧Mask element pair

711‧‧‧Mask elements

810‧‧‧Pattern element pair

811‧‧‧ Pattern Elements

4a‧‧‧Inspection device

206a‧‧‧Keyboard

206b‧‧‧mouse

D1‧‧‧distance

D2‧‧‧distance

E1‧‧‧ symbol

E2‧‧‧ symbol

E3‧‧‧ symbol

EB‧‧‧Bottom surface etching amount

ET‧‧‧Surface Etching Amount

G‧‧‧ Mask gap width

GB‧‧‧Bottom surface gap width

GT‧‧‧ Upper surface gap width

L1‧‧‧line

L2‧‧‧line

P‧‧‧ Object position

R1‧‧‧Recording Media

R2‧‧‧program

S1 ~ S7‧‧‧step

S11 ~ S17‧‧‧step

Steps S21 ~ S26‧‧‧‧

T1‧‧‧Processing time

FIG. 1 is a block diagram showing a configuration of a wiring pattern forming system according to the first embodiment.

FIG. 2 is a diagram showing a processing flow for manufacturing a wiring substrate.

Fig. 3 is a diagram showing the configuration of a drawing device.

Fig. 4 is a diagram showing the structure of a data processing device.

Fig. 5 is a block diagram showing the functions of the data processing device.

FIG. 6A is a diagram for explaining etching of a substrate.

FIG. 6B is a diagram for explaining etching of a substrate.

FIG. 6C is a diagram for explaining etching of a substrate.

FIG. 7 is a diagram showing a flow of drawing by a drawing device.

FIG. 8 is an enlarged plan view showing a part of the processed substrate.

FIG. 9 is a cross-sectional view showing a pattern element pair on a processed substrate.

FIG. 10 is a diagram showing reference information.

FIG. 11 is a diagram showing a plurality of object positions on the processed substrate.

Fig. 12 is a block diagram showing the function of the inspection device of the second embodiment.

FIG. 13 is a diagram showing an inspection flow of the inspection device.

FIG. 1 is a block diagram showing a configuration of a wiring pattern forming system 10 according to the first embodiment. The wiring pattern forming system 10 forms a wiring pattern on a substrate to manufacture a wiring substrate. The wiring pattern forming system 10 includes a drawing data creation mechanism 11, a drawing mechanism 12, a developing mechanism 13, a wiring pattern forming mechanism 14, an inspection mechanism 15, and a correction mechanism 16. In FIG. 1, a design data production mechanism 19 provided outside the wiring pattern forming system 10 is also illustrated.

FIG. 2 is a diagram showing a processing flow for manufacturing a wiring substrate by the wiring pattern forming system 10. In the manufacture of the wiring board, design data (CAD data) showing a desired wiring pattern is produced by the design data creation mechanism 19 (step S1), and is output to the drawing data creation mechanism 11. The rendering data creation mechanism 11 is realized by, for example, a computer, and converts vector data, that is, design data, into raster data, that is, rendering data. That is, drawing data is created (step S2).

The drawing mechanism 12 is a direct exposure device (drawing device) that directly forms an exposure pattern without using a photomask, and holds a predetermined substrate to be a wiring substrate. A conductor film for wiring formation is formed on the surface of the insulating layer of the substrate, and a photoresist film is formed on the conductor film. In the drawing mechanism 12, a photosensitive photoresist film is irradiated with ultraviolet rays or the like based on the drawing data, thereby drawing (exposing) a pattern to the photoresist film (step S3).

When the drawing of the pattern is completed, the substrate is transferred to the developing device 13 which is a developing device. In the developing mechanism 13, a developing step of spraying a developing solution on the exposed photoresist film is performed (step S4). Through the developing step, the unnecessary area of the photoresist film is removed to form a pattern (development pattern) of the photoresist film. In the wiring pattern forming mechanism 14 which is an etching device, the substrate after the developing step is etched. Thereby, the portion of the conductor film that is not covered by the photoresist pattern, that is, exposed from the photoresist pattern (cutting) is removed. Thereafter, the photoresist pattern is removed by performing photoresist peeling. In this way, a wiring pattern, which is a pattern of a conductive film, can be formed on the substrate (step S5).

The wiring substrate, which is a substrate on which a wiring pattern is formed, is transported to the inspection mechanism 15 which is an inspection device, and the wiring pattern is inspected (step S6). In fact, the pattern shown in the design data contains a specific test pattern in addition to the wiring pattern, and the inspection result of the test pattern formed on the substrate is output to the correction mechanism 16. The correction mechanism 16 is implemented by, for example, a computer, and corrects the design data based on the inspection result of the test pattern on the substrate and the difference from the test pattern displayed by the design data (step S7). At this time, the shape of the wiring pattern is corrected in the design data, and the shape of the test pattern is not corrected. The revised design data is output to the drawing data creation mechanism 11 as a pattern to be displayed on the next substrate.

The drawing data creation mechanism 11 creates drawing data from the revised design data (step S2), and performs drawing steps, development steps, and wiring pattern formation steps (steps S3 to S5) under the same conditions as described above. That is, a wiring pattern is formed on the substrate based on the revised design data. Thereby, a wiring substrate having a wiring pattern similar to the wiring pattern indicated by the design data manufacturing mechanism 19, that is, the original design data (uncorrected design data) is manufactured. In the wiring pattern forming system 10, each time a wiring substrate is manufactured, the design data is revised based on the inspection steps and inspection results (correction of the original design data) (steps S6 and S7). The revised design data is used in Formation of a wiring pattern on the next substrate (steps S2 to S5). It is also possible to modify the design data at intervals determined arbitrarily, such as the manufacture of a specific number of wiring boards, and every predetermined period.

FIG. 3 is a diagram showing the configuration of a drawing device 1 including an example of the drawing data creation mechanism 11, the drawing mechanism 12, and the correction mechanism 16. The drawing device 1 is a direct drawing device that directly irradiates light onto a photosensitive material provided on the surface of the substrate 9, that is, a photoresist film, and directly draws an image of a pattern on the photoresist film. Development and etching are performed on various substrates 9 on which a pattern is drawn by the drawing device 1 (see FIG. 1). Thereby, a pattern is formed on the substrate 9. The etching of the substrate 9 is, for example, wet etching performed by applying an etchant to the substrate 9.

The drawing device 1 includes a data processing device 2 and an exposure device 3. The data processing device 2 corrects design data of a pattern drawn on the substrate 9 to generate drawing data. The exposure device 3 draws (that is, exposes) the substrate 9 based on the drawing data transmitted from the data processing device 2. If the data processing device 2 and the exposure device 3 can transfer and receive data between the two devices, they can also be physically separated, and of course, they can also be integrated.

FIG. 4 is a diagram showing the configuration of the data processing device 2. The data processing device 2 is configured as a general computer system including a CPU 201 that performs various calculation processes, a ROM 202 that stores basic programs, and a RAM 203 that stores various information. The data processing device 2 further includes: a fixed magnetic disk 204 for storing information; a display 205 for displaying various information such as images; a keyboard 206a and a mouse 206b for receiving input from an operator; reading / writing The input device 207 reads and writes information from a computer-readable recording medium R1 such as an optical disk, a magnetic disk, a magneto-optical disk; and a communication unit 208, which transmits and receives signals to and from other components of the drawing device 1. .

In the data processing device 2, the program R2 is read from the recording medium R1 via the read / write device 207 and stored in the fixed disk 204 in advance. The CPU 201 uses the RAM 203 or the fixed magnetic disk 204 in accordance with the program R2 to perform arithmetic processing (that is, the computer executes the program), thereby realizing the functions described later.

FIG. 5 is a block diagram showing the functions of the data processing apparatus 2. In FIG. 5, a part of the configuration of the exposure device 3 (the drawing controller 31) connected to the data processing device 2 and an external inspection device 4 are shown together. Data processing device 2 includes data correction device 21 and data conversion 部 22. The data correction device 21 corrects design data of a pattern formed on the substrate 9 by etching. The data correction device 21 includes a design data storage unit 211, a reference information generation unit 212, a reference information storage unit 213, a lower surface etching amount acquisition unit 214, and a data correction unit 216. In the data conversion unit 22, design data (hereinafter referred to as "correction completion data") corrected by the data correction device 21 is input. Corrected data is usually vector data such as polygons. The data conversion unit 22 converts vector data, that is, corrected data, into raster data, that is, drawing data. The function of the data processing device 2 can be realized by a dedicated electric circuit, and a dedicated electric circuit can also be used in part.

As shown in FIG. 3, the exposure device 3 includes a drawing controller 31, a stage 32, a light emitting unit 33, and a scanning mechanism 35. The drawing controller 31 controls the light emitting unit 33 and the scanning mechanism 35. The stage 32 holds the substrate 9 below the light emitting portion 33. The light emitting section 33 includes a light source 331 and a light modulation section 332. The light source 331 emits laser light toward the light modulation section 332. The light modulation section 332 modulates light from the light source 331. The light modulated by the light modulation section 332 is irradiated onto the substrate 9 on the stage 32. As the light modulation section 332, for example, a DMD (Digital Mirror Device) in which a plurality of light modulation elements are two-dimensionally arranged is used. The light modulation section 332 may be a modulator or the like in which a plurality of light modulation elements are arranged one-dimensionally.

The scanning mechanism 35 moves the stage 32 in the horizontal direction. Specifically, the stage 32 is moved in the main scanning direction and the sub-scanning direction perpendicular to the main scanning direction by the scanning mechanism 35. Thereby, the light modulated by the light modulation section 332 is scanned on the substrate 9 in the main scanning direction and the sub-scanning direction. The exposure device 3 may be provided with a rotation mechanism for horizontally rotating the stage 32. Further, a lifting mechanism for moving the light emitting section 33 in the vertical direction may be provided. The scanning mechanism 35 is only required to scan the light from the light emitting portion 33 on the substrate 9, and a mechanism for moving the stage 32 is not necessary. For example, the light emitting unit 33 may be moved above the stage 32 in the main scanning direction and the sub scanning direction by the scanning mechanism 35.

Here, the etching of the substrate 9 will be described. 6A to 6C are diagrams for explaining etching of the substrate 9, and are sectional views of the substrate 9. As shown in FIG. 6A, the During the etching, a conductor film 8 made of a conductive material such as metal (for example, copper) is formed on the main surface of the substrate 9 in advance, and a mask pattern 71 of a photoresist material is formed on the conductor film 8. The main surface of the substrate 9 is, for example, a surface provided on an insulating layer (or the substrate 9 itself) of the substrate 9. The thicknesses of the conductive film 8 and the mask pattern 71 are determined in advance. The mask pattern 71 is a collection of a plurality of mask elements 711.

Next, the substrate 9 is subjected to wet etching using an etchant. At this time, the substrate 9 (the insulating layer) and the mask pattern 71 are not etched by the etching solution. Therefore, as shown in FIG. 6B, the area on the upper surface of the conductor film 8 not covered by the mask element 711 is removed by etching.

The removal of the conductor film 8 by the etching solution is performed approximately isotropically from the area on the upper surface of the conductor film 8 not covered by the mask element 711, as shown in FIG. 6C, and also on the mask element 711 and the substrate 9. Between the areas. As a result, in the pattern element 811 formed on the conductor film 8 using each of the mask elements 711, the width of the upper surface in contact with the mask element 711 becomes narrower than the width of the lower surface in contact with the substrate 9. That is, the cross-sectional shape of the pattern element 811 is trapezoidal. In FIG. 6C, only the vicinity of one side wall of each pattern element 811 having a trapezoidal cross-sectional shape is shown. The plurality of pattern elements 811 corresponding to the plurality of mask elements 711 included in the mask pattern 71 are separated from each other, and the set of the plurality of pattern elements 811 becomes the pattern of the conductor film 8.

Next, the drawing flow of the drawing device 1 will be described with reference to FIG. 7. First, in the data correction device 21, the reference information used in the processing to be described later is stored in the reference information storage unit 213, thereby preparing (step S11). Details about the reference information will be described later. In addition, design data of a predetermined pattern formed by etching is inputted to the data correction device 21 on the substrate 9 and stored in the design data storage unit 211, thereby preparing (step S12).

Next, a substrate 9 (hereinafter referred to as "processed substrate 9") is prepared by drawing the pattern displayed on the design data on the photoresist film by the exposure device 3, and then performing development, etching, and photoresist peeling. The processed substrate 9 is a substrate that is drawn in step S17 described later. 9 is the same shape and size. In addition to the wiring patterns on the substrate 9, the patterns shown in the design information also include test patterns.

FIG. 8 is an enlarged plan view showing a part of the processed substrate 9, showing the area of the test pattern. Each of the plurality of pattern elements 811 displaying the test pattern is a substantially straight line extending in one direction. The two pattern elements 811 adjacent to each other among the plurality of pattern elements 811 shown in FIG. 8 are used as pattern element pairs 810, and a plurality of pattern element pairs 810 are formed in the processed substrate 9.

FIG. 9 is a diagram showing a pattern element pair 810 on the processed substrate 9, and shows a cross section perpendicular to the length direction of the pattern element 811. In addition, in FIG. 9, two mask elements 711 for forming the two pattern elements 811 of the pattern element pair 810 are shown by two-dot chain lines. In the following description, the two mask elements 711 corresponding to each pattern element pair 810 will be referred to as a "mask element pair 710".

The plurality of pattern element pairs 810 of the processed substrate 9 are formed by etching using the plurality of mask element pairs 710, respectively. Specifically, first, a plurality of photomask element pairs 710 are formed by the exposure device 3 drawing the photoresist film and developing the photoresist film. The two mask elements 711 included in each mask element pair 710 are adjacent to each other on the conductor film 8. If the width G of the gap between the two mask elements 711 of the mask element pair 710 is set as the mask gap width G, a plurality of mask gap widths G different from each other are set in the plurality of mask element pairs 710, respectively. . Then, a plurality of mask element pairs 710 are used to form a plurality of pattern element pairs 810 of the conductive film 8 by etching using the type, concentration, temperature, or processing time of the etching solution as specific set conditions. In the processed substrate 9, a plurality of mask elements 711 are removed by photoresist peeling.

As described above, in the pattern element 811 formed on the conductive film 8 using each mask element 711, the width of the upper surface in contact with the mask element 711 becomes narrower than that of the lower surface in contact with the substrate 9. In the following description, among the mask elements 711 included in the mask element pair 710, from the edge of the predetermined mask gap width G to the pair of mask elements 711 The distance up to the edge of the upper surface of the pattern element 811 (the distance perpendicular to the length direction of the pattern element 811 and the direction along the main surface of the substrate 9) is called the "top surface etching amount ET" and will reach the level of the pattern element 811. The distance to the edge of the lower surface is referred to as the "lower surface etching amount EB". The upper surface etching amount ET and the lower surface etching amount EB are changed depending on the mask gap width G.

In the inspection device 4 provided outside the drawing device 1, an image of the upper surface of the plurality of pattern element pairs 810 on the processed substrate 9 is obtained, and based on the image, the gap width between the upper surfaces of each pattern element pair 810 is measured. That is, the upper surface gap width GT. The inspection device 4 may be installed in the drawing device 1. The measured value of the upper surface gap width GT of each pattern element pair 810 is input to the lower surface etching amount acquisition unit 214.

In the lower surface etching amount obtaining section 214, the design gap used for the pattern drawing of the substrate 9 is determined from the mask gap width G of the mask element pair 710 used for forming each pattern element pair 810. Then, one half of the value obtained by subtracting the mask gap width G from the measured value of the upper surface gap width GT is taken as the measured value of the upper surface etching amount ET (step S13). In this embodiment, the position, shape, and size of each mask element 711 of the mask pattern 71 are set to be strictly consistent with the pattern displayed by the design data.

Here, the above-mentioned reference information prepared in step S11 will be described. FIG. 10 is a diagram showing an example of reference information. In FIG. 10, the change over time of the etching amount ET on the upper surface of the etching is shown by the line L1, and the change over time of the etching amount EB of the lower surface is shown by the line L2. The reference information substantially shows the relationship between the etching amount ET on the upper surface of the pattern element pair 810 formed on the conductor film 8 by etching the 710 using the mask element and the etching amount EB on the lower surface. The upper surface etching amount ET gradually increases from the start of etching as the processing time elapses. At a time after a certain time has elapsed from the start of the etching, the etchant reaches the surface of the substrate 9 (refer to the shape E2 of the conductor film 8 shown by a two-dot chain line in FIG. 6B), and the etching amount of the lower surface EB from that time It gradually increases with the passage of processing time. In addition, in the left-right direction of FIG. 9, when the edge of the lower surface of the pattern element 811 is located between the mask element pair 710, the following table The surface etching amount EB becomes a negative value, and when the edge is located below the mask element 711, the lower surface etching amount EB becomes a positive value. The reference information is generated for each of the plurality of mask gap widths G. The process of generating reference information will be described later.

In the lower surface etch amount obtaining unit 214, for example, when the measured value of the surface etch amount ET above a mask gap width G is D1, the line L1 is specifically the line showing the change in the upper surface etch amount ET in FIG. It becomes the processing time T1 of the distance D1. And, the distance D2 of the processing time T1 in the line L2 showing the change in the lower surface etching amount EB is obtained as the value of the lower surface etching amount EB. In this way, by using the measured values of the surface etching amount ET above each mask gap width G and referring to a reference information, for the processed substrate 9, the values of the plurality of mask etching widths EB of the plurality of mask gap width G are obtained (Step S14). The relationship between the mask gap width G and the lower surface etching amount EB is typically that the lower surface etching amount EB gradually decreases as the mask gap width G becomes smaller, and the rate of change gradually increases.

The data correction section 216 corrects the design data stored in the design data storage section 211 based on the values of the plurality of lower surface etching amounts EB of the plurality of mask gap widths G to generate correction completion data (step S15). In the revision of the design data, it is considered that the conductor film 8 on the substrate 9 is etched in excess (that is, exceeds a desired amount) according to the lower surface etching amount EB. That is, referring to the values of the plurality of lower surface etching amounts EB of the plurality of mask gap widths G, the lower surface of each pattern element 811 of the pattern on the substrate 9 is formed with a desired line width or size. Correct the line width or size of the pattern elements included in the wiring pattern of the design data. In fact, the value of the surface etching amount EB under a gap width (gap width of the mask element 711) different from the plurality of mask gap widths G is obtained through various interpolation operations, and the gap width and The etching curve in relation to the surface etching amount EB is used for correction of design data. In addition, the shape of the pattern elements included in the test pattern of the design data is not changed (corrected).

The correction completion data is sent from the data correction unit 216 to the data conversion unit 22. In the data conversion section 22, the vector data, that is, the corrected data is converted into the raster data, that is, the drawing data. (Step S16). This drawing data is sent from the data conversion section 22 to the drawing controller 31 of the exposure device 3. In the exposure device 3, based on the drawing data, the drawing controller 31 controls the light modulation section 332 and the scanning mechanism 35 of the light emitting section 33 to perform drawing on the substrate 9 (step S17). The imaged substrate 9 is subjected to processing such as development, etching, and the like, thereby forming a plurality of pattern elements 811 representing a wiring pattern (and a test pattern) on the substrate 9.

In this embodiment, step S13 in FIG. 7 corresponds to the checking step in step S6 in FIG. 2, and steps S14 and S15 correspond to the design data correction step in step S7. Step S16 corresponds to the drawing data creation step of step S2, and step S17 corresponds to the drawing step of step S3. Therefore, in the repetition of steps S2 to S7 of FIG. 2, steps S13 to S17 of FIG. 7 are repeated. At this time, a pattern is drawn in step S17, and the substrate 9 on which the wiring pattern is formed through steps S4 and S5 is used as the processed completed substrate 9, and the other substrates 9 are subjected to steps S13 to S17. Steps S11 and S12 in FIG. 7 are included in step S1 in FIG. 2.

Next, the generation of reference information will be described. In the etching of the conductor film 8, the surface in contact with the etchant in the conductor film 8 that is the etching interface passes through the shape with the symbol E1 and the shape with the symbol E2 in FIG. 6B, and becomes the symbol E3 in FIG. 6C. Its shape. Here, after the etching starts (refer to FIG. 6A), until the etching interface reaches the shape E2 when the etching interface reaches the surface of the substrate 9, the etching is performed approximately isotropically at a constant speed, and the shape changes from the shape E2 to the shape E3 at the etching interface In the process, it is assumed that the shape of the etching interface can be expressed in terms of polynomial timing. Under this assumption, the time required from the beginning of etching to the etching interface becoming the shape E2 is determined by the etching speed (ie, the etching distance per unit time, which can also be called the etching rate) required in advance according to experiments and the like and the conductor film. 8 thickness is calculated. In addition, the time change ET (t) of the upper surface etching amount ET and the time change EB (t) of the lower surface etching amount EB during the process of changing the etching interface from the shape E2 to the shape E3 are represented by the numbers 1 and 2 respectively. . In the numbers 1 and 2, t is the time from the moment when the etching interface reaches the surface of the substrate 9.

(Number 1) ET (t) = a0 + a1 * t + a2 * t ² + a3 * t ³ + ...

(Number 2) EB (t) = b0 + b1 * t + b2 * t ² + b3 * t ³ + ...

During the process from the shape E2 to the shape E3 at the etching interface, it is considered that there is no specific change in the etching, so the term 3 of the time t in the number 1 and the number 2 can be ignored afterwards, and the time change ET (t) of the upper surface etching amount ET , And the time change EB (t) of the lower surface etching amount EB is modeled (formulated) by a number 3 and a number 4.

(Number 3) ET (t) = a0 + a1 * t + a2 * t ²

(Number 4) EB (t) = b0 + b1 * t + b2 * t ²

The numbers 3 and 4 are essentially polynomials that formulate changes in the shape of the etched pattern element to the shape 810 (changes from the shape E2). In the reference information generating unit 212, the coefficients a0, a1, a2, b0, b1, and b2 of the numbers 3 and 4 are determined for each of the plurality of mask gap widths G. Specifically, the coefficients a0 and b0 of the numbers 3 and 4 are such that t is 0, that is, the upper surface etching amount ET and the lower surface etching amount EB when the etching interface reaches the surface of the substrate 9. The surface etching amount ET (ie, the coefficient a0) above t = 0 can be obtained using the above-mentioned etching rate, and the surface etching amount EB (ie, the coefficient b0) below t = 0 is (-G / 2). The coefficients a1 and b1 of the numbers 3 and 4 are changes in the surface etching amount ET (ET '(0)) above t = 0, and changes in the surface etching amount EB below t = 0 (EB' ( 0)), here, the same as the etching rate.

The coefficients a2 and b2 of the numbers 3 and 4 are determined using a test substrate to be etched. Specifically, on the conductive film 8 of the test substrate, a plurality of mask element pairs 710 each having a plurality of mask gap widths G are formed, and the plurality of mask element pairs 710 are used to form a plurality of pattern elements by etching. To 810. The test substrate preferably has the same shape and size as the substrate 9 described above. The type, concentration, temperature, or processing time of the etching solution used for the etching is the same as that of the above-mentioned processing-completed substrate 9. The processing time for etching the test substrate may also be changed within a range where a plurality of pattern element pairs 810 corresponding to the plurality of mask element pairs 710 are appropriately formed.

Thereafter, the surface gap width GT on the plurality of pattern element pairs 810 on the test substrate is measured in the inspection device 4 (see FIG. 9). The gap width between the lower surfaces of each pattern element pair 810, that is, the lower surface gap width GB was also measured. The measured values of the plurality of pattern elements on the upper surface gap width GT and lower surface gap width GB of 810, that is, the measured values of the upper surface gap width GT and lower surface gap width GB of the mask gap width G and the etching of the test substrate The processing time is input to the reference information generating unit 212 together. The lower surface gap width GB (and the upper surface gap width GT) can also be measured using a microscope or the like.

As described above, if the time from the start of the etching to the time when the etching interface reaches the surface of the substrate 9 (the time until the etching interface becomes the shape E2) is set to Tm, the numbers 3 and 4 indicate the time after the time Tm has elapsed since the start of the etching. The time change ET (t) of the surface etching amount ET and the time change EB (t) of the lower surface etching amount EB. The time Tm is obtained from the etching rate and the thickness of the conductive film 8. Further, in the reference information generating unit 212, the values of the upper surface etching amount ET and the lower surface etching amount EB (measured values) are obtained from the measured values of the upper surface gap width GT and the lower surface gap width GB of each mask gap width G. ). Therefore, in the number 3 of the determination coefficients a0 and a1, the value obtained by subtracting the time Tm from the processing time of the test substrate etching is substituted into t, and the measured value of the upper surface etching amount ET is substituted into ET (t).出 flag a2. Similarly, in the number 4 of the determination coefficients b0 and b1, the value obtained by subtracting Tm from the processing time of the test substrate etching is substituted into t, and the measured value of the lower surface etching amount EB is substituted into EB (t).出 效应 b2.

In the reference information generating unit 212, the etched pattern element pair 810 is etched on the surface of 810 by determining the coefficients a0, a1, a2, b0, b1, and b2 of numbers 3 and 4 for each mask gap width G. Reference information on the change with time of the amount ET and the change with time of the lower surface etching amount EB (see FIG. 10). The reference information shows the relationship between the etched amount ET on the upper surface of the pattern element pair 810 and the etched amount EB on the lower surface. The reference information may be generated by a computer external to the information correction device 21 and input to the reference information storage unit 213.

As described above, in the data correction device 21 and the reference information storage unit 213, For each of the plurality of photomask gap widths G, reference information is displayed that shows the relationship between the pattern surface element etching amount ET on the upper surface 810 and the bottom surface etching amount EB. In addition, for the substrate 9 which has been etched by using a plurality of mask element pairs 710 each having a plurality of mask gap widths G, each of a plurality of pattern element pairs 810 corresponding to the plurality of mask element pairs 710 is obtained. This is the measured value of the surface etching amount ET. Then, using the measured values and referring to the reference information, the values of the plurality of lower surface etching amounts EB for obtaining the plurality of mask gap widths G for the completed substrate 9 are corrected based on the values of the plurality of lower surface etching amounts EB. Design Resources. Thereby, it is possible to easily perform the correction of the design data using the lower surface of the pattern of the conductor film 8 as a reference.

When obtaining the reference information, regarding each of the plurality of mask gap widths G, the state where the conductive film 8 is etched to the surface of the substrate 9 (that is, the state when the etching interface reaches the surface of the substrate 9), the conductive film 8 is along the A change in the shape of the pattern element 810 at the time of etching the surface is formulated by a polynomial of time. Then, the coefficient of the polynomial is determined by substituting the measured value of the shape of the pattern element 810 of the test substrate subjected to the etching at a specific time. This makes it easy to obtain reference information. In addition, the processed completed substrate 9 that is patterned based on design data may be processed as a test substrate.

As described above, in the repetition of steps S2 to S7 in FIG. 2, in principle, the same conditions are processed by each step. However, the etching conditions (such as the temperature of the etchant) of the etching device are slightly changed. At this time, the measured values of the surface etching amount ET on the plurality of mask gap widths G of the substrate 9 after the processing are changed.

In this case, the processing time corresponding to the measurement value of the upper surface etching amount ET is specified in the reference information of FIG. 10 in the lower surface etching amount obtaining section 214, and the lower surface etching amount corresponding to the processing time is obtained. EB value. That is, a change in the measurement value of the upper surface etching amount ET due to a slight change in the etching conditions is substantially converted into a change in the processing time of the etching, and the value of the lower surface etching amount EB is preferably obtained with accuracy. Thereby, it is possible to perform the correction of the design data with the lower surface of the pattern of the conductor film 8 as a reference with better accuracy (for Correction of original design information).

However, in etching the substrate 9, the etching amount (the upper surface etching amount ET and the lower surface etching amount EB) may be different depending on the position on the substrate 9. In this case, as shown in FIG. 11, it is preferable to arrange a test pattern on the processed substrate 9 at a plurality of positions P (hereinafter, referred to as “target positions P”). That is, in each of the plurality of target positions P, a plurality of pattern element pairs 810 corresponding to the plurality of mask gap widths G are formed.

In the processing of FIG. 7 using the processing of FIG. 11 to complete the substrate 9, the measured values of the etching amount ET on the upper surface of the plurality of pattern element pairs 810 are obtained for each object position P (step S13). Next, in the reference information of each mask gap width G (refer to FIG. 10), the processing time corresponding to the measurement value of the surface etching amount ET on the mask gap width G at each target position P is specified, and the corresponding processing time is obtained. The processing time corresponds to the value of the lower surface etching amount EB (step S14). That is, the difference in the amount of etching depending on the position on the substrate 9 (the difference in the measured value of the amount of etching on the upper surface ET) is substantially converted into the difference in the processing time of etching using the same reference information to obtain the amount of etching on the lower surface EB Value.

In the data correction section 216, the design data is corrected based on the values of the plurality of lower surface etching amounts EB of the plurality of object positions P to generate correction completion data (step S15). At this time, in the correction of the pattern element at each position on the substrate 9 displayed in the design data, for example, the value of the surface etching amount EB under the object position P closest to the position is referred to. With this, the design data is corrected by considering the difference in the etching amount depending on the position on the substrate 9. The correction-completed data is converted into drawing data (step S16), and based on the drawing data, the drawing of the substrate 9 is performed (step S17).

As described above, in the data correction device 21, when a test pattern is arranged in each of the plurality of object positions P on the processed substrate 9, the same reference information is referred to each mask gap width G, thereby The values of the plurality of lower surface etching amounts EB of the plurality of object positions P are obtained. Accordingly, based on the values of the plurality of lower surface etching amounts EB, it is possible to easily perform high-accuracy correction of design data.

As is clear from FIG. 9, the gap width between the upper surfaces of the pattern element pair 810, that is, the upper surface gap width GT is twice the etching amount ET on the upper surface plus the mask gap width G. Therefore, in each mask gap width G, the upper surface gap width GT and the upper surface etching amount ET can be treated as equivalent. Similarly, the gap width between the lower surfaces of the pattern element pair 810, that is, the lower surface gap width GB is the value of twice the etching amount EB on the lower surface plus the mask gap width G. Therefore, in each mask gap width G, the lower surface gap width GB and the lower surface etching amount EB can be treated as equivalent.

Therefore, in the reference information storage unit 213 of the data correction device 21, for each of the plurality of mask gap widths G, the reference of the relationship between the pattern element pair 810 upper surface gap width GT and the lower surface gap width GB is memorized. Information. In addition, the lower surface etching amount obtaining unit 214 can obtain the measured value of the gap clearance GT on the upper surface of the substrate 9 by using the process and refer to the reference information, and obtain a plurality of mask gap widths G for the processed substrate 9. A plurality of lower surface gap width acquiring portions are provided below the value of the plurality of lower surface gap widths GB. Then, in the data correcting section 216, the design data based on the plurality of lower surface gap widths GB of the plurality of mask gap widths G is substantially corrected.

Next, an inspection apparatus according to a second embodiment of the present invention will be described. Fig. 12 is a block diagram showing the functions of the inspection device 4a. The inspection device 4a is a device for inspecting a pattern formed on the substrate 9 by etching based on design data. The inspection device 4a is the same as the data processing device 2 shown in FIG. 2 and constitutes a general computer system.

The inspection device 4 a includes a design data storage unit 41, a reference information storage unit 42, an actual image storage unit 43, an upper surface gap width acquisition unit 44, a data correction unit 45, and a defect detection unit 46. The design data storage unit 41 and the reference information storage unit 42 are the same as the design data storage unit 211 and the reference information storage unit 213 of FIG. 5. The actual image storage unit 43 stores the image data of the upper surface of the pattern of the conductor film 8 formed on the substrate 9 (hereinafter referred to as “the target substrate 9”) to be inspected as the inspection image data. The upper surface gap width obtaining unit 44 obtains the space between the upper surfaces of the pattern element pair 810 included in the test pattern based on the inspection image data. The measured value of the gap width GT (see FIG. 9). The data correction unit 45 uses the measured value of the upper surface gap width GT to obtain the shape of the lower surface of the pattern on the target substrate 9 from the pattern of the conductor film 8 displayed on the image data. The defect detection unit 46 detects a defect of the pattern based on the shape of the lower surface of the pattern of the conductor film 8.

Next, the inspection flow of the inspection device 4a will be described with reference to FIG. 13. In the inspection of the inspection device 4a, first, for each of the plurality of mask gap widths G, reference information of the relationship between the display pattern element pair 810 upper surface gap width GT and lower surface gap width GB is stored in the reference information memory. The unit 42 thus prepares (step S21). The reference information is generated by a reference information generating section of an external computer or inspection device 4a. Further, it is prepared by storing the design data used when the pattern of the conductor film 8 is formed on the target substrate 9 in the design data storage unit 41 (step S22).

Next, the image data displayed on the upper surface of the pattern of the conductor film 8 formed on the target substrate 9 is acquired, and the image data is stored as the inspection image data in the actual image storage unit 43 (step S23). Here, the pattern of the conductor film 8 on the target substrate 9 is based on design information, and a pattern drawn on the photoresist film on the substrate 9 is developed to form a mask pattern 71 of the photoresist film, and the mask pattern 71 is used Then, etching is performed to thereby form a pattern on the target substrate 9. Similar to the processing described with reference to FIG. 7, the pattern displayed in the design data includes a test pattern in addition to the wiring pattern. Therefore, a plurality of mask element pairs 710 each having a mask gap width G set are used to form a plurality of pattern element pairs 810 on the target substrate 9. The inspection image data is obtained by an imaging unit provided outside the inspection device 4a or an imaging unit provided in the inspection device 4a.

The upper surface gap width acquisition unit 44 acquires the measured values of the upper surface gap width GT of each of the plurality of pattern element pairs 810 included in the test pattern based on the inspection image data (step S24). That is, the measured values of the plurality of upper surface gap widths GT corresponding to each of the plurality of mask gap widths G are obtained.

In the data correction unit 45, one pattern element 811 on the target substrate 9 is noticed The pattern element 811 uses the gap width between the mask element 711 used to form the attention pattern element 811 and the mask element 711 adjacent to the mask element 711 as the gap width of the mask element 711 and is based on the design data. specific. Next, the value of the lower surface gap width GB is obtained by using the measured value of the upper surface gap width GT corresponding to the mask gap width G and referring to the reference information of the mask gap width G that is similar or consistent with the gap width. . Then, in the image displayed by the inspection image data, based on, for example, the difference between the measured value of the upper surface gap width GT and the value of the lower surface gap width GB (to be precise, it is the upper surface etch amount ET and the lower surface in FIG. 9). The difference in the etching amount EB) changes the line width or size of the area of the attention pattern element 811, thereby obtaining the shape of the lower surface of the attention pattern element 811 on the target substrate 9.

Similar to the data correction unit 216 in FIG. 5, the difference between the gap widths different from the mask gap width G is obtained through various interpolation operations, and a curve showing the relationship between the difference and the gap width can also be generated. In this case, the above-mentioned difference corresponding to the gap width of the mask element 711 for the attention pattern element 811 is obtained from the curve, and is used to change the line width or size of the area of the attention pattern element 811. In essence, the processing using this curve can also refer to the reference value of the mask gap width G specified from the design data for the attention pattern element 811 as the measured value of the mask gap width G.

In the data correction unit 45, each of the pattern elements 811 included in the wiring pattern is performed on the target substrate 9 as the attention pattern element 811, and the pattern shown in the image data is obtained by inspecting the pattern from the object. The shape of the lower surface of the pattern of the conductor film 8 formed on the substrate 9 (step S25). The defect detection unit 46 detects a defect in the pattern of the conductor film 8 on the target substrate 9 based on the shape of the lower surface of the pattern obtained by the data correction unit 45 (step S26). For example, when the distance between the edge of the lower surface of each pattern element 811 and the edge of the lower surface of a pattern element 811 adjacent to the pattern element 811 is obtained, and the distance is below a specific threshold, the two patterns Element 811 is detected as a defect. Defects can also be detected by various methods.

As described above, in the inspection device 4a, reference information on the relationship between the upper surface gap width GT and the lower surface gap width GB of the pattern element pair 810 is prepared for each of the plurality of mask gap widths G. In addition, inspection image data, which is image data of the upper surface of the pattern formed on the target substrate 9, is prepared. Based on the inspection image data, measured values of the gap width GT on the upper surface of each of a plurality of pattern element pairs 810 are obtained. . Then, for each pattern element 811 of the pattern on the target substrate 9, the measured value of the mask gap width G is used and the reference information of the mask gap width G specified from the design data is referred to thereby self-checking the image data display The pattern obtains the shape of the lower surface of the pattern on the target substrate 9. This makes it possible to easily perform an inspection using the lower surface of the pattern of the conductive film 8 as a reference.

The data correction device 21, the drawing device 1, the wiring pattern forming system 10, and the inspection device 4a can be variously changed.

The processing sequence of FIGS. 7 and 13 may be changed as appropriate. For example, the order of step S11 and step S12 can also be interchanged in the processing of FIG. 7 (the same applies to steps S21 and S22 in FIG. 13).

The substrate 9 may be a semiconductor substrate, a glass substrate, or the like, in addition to a printed substrate. The data correction device 21 can also be used independently from the drawing device 1.

The structures of the above-mentioned embodiment and each modification can be appropriately combined as long as they do not contradict each other.

Although the present invention has been described and illustrated in detail, the above description is illustrative and not restrictive. Therefore, as long as it does not depart from the scope of the present invention, it can be said that there can be various changes or aspects.

8‧‧‧Conductor film

9‧‧‧ substrate

71‧‧‧Mask pattern

710‧‧‧Mask element pair

711‧‧‧Mask elements

810‧‧‧Pattern element pair

811‧‧‧ Pattern Elements

EB‧‧‧Bottom surface etching amount

ET‧‧‧Surface Etching Amount

G‧‧‧ Mask clearance

GB‧‧‧Bottom surface gap width

GT‧‧‧ Upper surface gap width

Claims (8)

A data correction device that corrects design data of a pattern formed by etching a conductive film formed on the surface of a substrate with an etchant, and includes: a design data storage section for storing data on a substrate on which a conductive film is formed Design information of the pattern of the above-mentioned conductor film formed by etching under specific conditions; referring to the information memory section, the gap between the pair of mask element pairs formed next to each other on the conductor film of the substrate The width is used as a mask gap width, and reference information is memorized for each of the plurality of mask gap widths. The reference information indicates that: the pattern element to be formed on the conductor film by the above-mentioned mask element pair is etched. The relationship between the width of the gap between the upper surfaces is the width of the upper surface, and the width of the gap between the lower surfaces of the pattern element is the width of the lower surface; A plurality of mask element pairs of a plurality of mask gap widths are subjected to the above-mentioned specific conditions for the etching to complete the substrate. The measured value of the mask width on the upper surface of each of the plurality of pattern element pairs corresponding to the mask element pair, using the measured value and referring to the above reference information, thereby obtaining the mask gap width of the plurality of mask gaps for the above-mentioned processed completed substrate. The value of the plurality of lower surface gap widths; and a data correction unit that corrects the design data based on the value of the plurality of lower surface gap widths of the plurality of mask gap widths; and each of the plurality of mask gap widths Or, a polynomial of time is used to formulate a change in the shape of the pattern element when the conductor film is etched along the surface from the state where the conductor film is etched to the surface of the substrate, and to use the The fitting of the measured values of the pattern elements of the etched test substrate to the shape determines the coefficient of the above polynomial, thereby obtaining the above Reference information. For example, the data correction device of claim 1, wherein a plurality of pattern element pairs corresponding to the plurality of mask gap widths are formed at each of the plurality of object positions on the above-mentioned processed completed substrate, and the lower surface gap width is obtained The department obtains the values of the plurality of lower surface gap widths of the plurality of object positions by referring to the same reference information for each mask gap width; and the data correction unit is based on the plurality of lower positions of the plurality of object positions. The value of the surface gap width is to correct the above design information. A drawing device is a person who draws a pattern on a substrate, and includes: a data correction device such as the item 1 or 2; a light source; and a light modulation unit, which is modulated based on the design data corrected by the data correction device. Light from a light source; and a scanning mechanism that scans the light modulated by the light modulation section on a substrate. A wiring pattern forming system includes: a data correction device as claimed in claim 1 or 2; and a wiring pattern forming mechanism that forms a wiring pattern on a substrate based on design data corrected by the data correction device. An inspection device for inspecting a pattern formed by etching a conductive film formed on a surface of a substrate with an etching solution, and including: a design data memory section, which is to be formed by etching on a substrate on which a conductive film is formed The design data of the above-mentioned pattern of the conductive film; referring to the information memory section, the width of the gap between the pair of mask elements formed adjacent to each other on the conductive film of the substrate is set as the mask gap width, and for a plurality of mask gaps Each of the widths has reference information, which indicates that: The width of the gap between the mask element pair and the pattern element pair to be formed on the conductor film by etching is the upper surface gap width, and the gap between the pattern element pair and the lower surface is the lower surface. The relationship between the gap widths; the actual image memory contains: by using the etching of the mask pattern formed based on the design data described above, the image data of the upper surface of the pattern formed on the target substrate is the inspection image Data; an upper surface gap width acquisition unit that uses the plurality of mask element pairs each having the plurality of mask gap widths to form a plurality of pattern element pairs in the target substrate, and obtains the pattern element pairs based on the inspection image data. The measurement value of the gap width on the upper surface of each of the plurality of pattern element pairs; the data correction unit uses the measurement value of the mask gap width for each pattern element of the pattern on the target substrate, referring to the above The above reference information of the mask gap width specified in the design data is obtained from the pattern shown in the above inspection image data The shape of the lower surface of the pattern on the target substrate; and a defect detection unit that detects a defect of the pattern on the target substrate based on the shape of the lower surface of the pattern obtained by the data correction unit; and For each of the plurality of mask gap widths, the change in the shape of the pattern element when the conductor film is etched along the surface will be formulated in a polynomial of time from the state where the conductor film is etched to the surface of the substrate. And the coefficient of the above polynomial is determined by fitting the measured values of the pattern elements of the test substrate subjected to the etching at a specific time to obtain the above reference information. A data correction method that corrects the design data of a pattern formed by etching a conductive film formed on the surface of a substrate with an etchant, and has the following steps: (a) preparing to borrow on a substrate formed with a conductive film Formed by etching under specific conditions The design information of the pattern of the above-mentioned conductor film; (b) The width of the gap between the mask element pairs formed adjacent to each other on the conductor film of the substrate is set as the mask gap width, and for each of the plurality of mask gap widths, The user prepares a step of referring to information, which indicates that the width of the gap between the upper surfaces of the pattern element pair using the photomask element pair and to be formed on the conductor film by etching, that is, the upper surface gap width, and the above The relationship between the width of the gap between the lower surface of the pattern element, that is, the width of the lower surface gap; (c) using a plurality of mask element pairs having the plurality of mask gap widths respectively set above and subjected to the above-mentioned specific conditions for etching In the processed substrate, the measured values of the surface gap widths on each of the plurality of pattern element pairs corresponding to the plurality of mask element pairs are obtained; (d) by using the above measurement values and referring to the above reference information, The substrate is processed as described above to obtain the values of the plurality of lower surface gap widths of the plurality of mask gap widths; and (e) based on the plurality of mask gap widths The values of the plurality of lower surface gap widths are used to correct the design data; and for each of the plurality of mask gap widths, the conductors are etched from the state where the conductor film is etched to the surface of the substrate with a polynomial of time. The shape change of the pattern element when the film is etched along the surface is formulated, and the coefficient of the above polynomial is determined by fitting the measured value of the shape of the pattern element of the test substrate subjected to the etching at a specific time, by Get the above reference information. For example, the data correction method of claim 6, wherein a plurality of pattern element pairs corresponding to the plurality of mask gap widths are formed on each of the plurality of object positions on the above-mentioned processed completed substrate, and in step (d) above For the width of each mask gap, refer to the same reference To obtain the values of the plurality of lower surface gap widths of the plurality of object positions, and in the step (e), based on the values of the plurality of lower surface gap widths of the plurality of object positions, correct the design data. . A method of manufacturing a wiring substrate includes the following steps: correcting design data by a data correction device such as the item 1 or 2; and forming a wiring pattern on the substrate based on the revised design data.