JP2004212572A - Method for manufacturing exposure mask and semiconductor device and system for judging necessity of defect correction - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing exposure mask capable of exactly performing the judgement of the necessity of defect correction of the exposure mask. <P>SOLUTION: A correspondence relation between dimensions of a three-dimensional image when changing the dimensions of the three-dimensional image on a wafer surface of a mask pattern in a prescribed range and the dimensions of a pattern formed by etching the wafer by using a resist pattern formed by the three-dimensional image as an etching mask is determined preliminarily. Subsequently, the mask pattern is formed on a mask blank. The three-dimensional image on the wafer surface of the mask pattern is obtained. Then, the dimensions of the pattern formed from the obtained three-dimensional image on the wafer is predicted based on the correspondence relation preliminarily determined. When the predicted value of the predicted pattern dimensions is outside the allowable range, the correction of the mask pattern is performed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing an exposure mask, a method of manufacturing a semiconductor device using the exposure mask, and an apparatus for determining whether or not the exposure mask needs defect correction.
[0002]
[Prior art]
A conventional method of inspecting an exposure mask will be described. The mask pattern formed on the exposure mask is optically scanned by an optical pattern inspection device using transmitted light or reflected light to acquire mask pattern data. The drawing data for forming the mask pattern is compared with the acquired mask pattern data. A method of comparing the same mask pattern formed on one exposure mask or comparing mask pattern data of two exposure masks on which the same mask pattern is formed may be used. is there.
[0003]
If there is a different portion between the two data to be compared, the portion is recognized as a defect, and the coordinates of the defective portion, the size and type of the pattern, and the like are stored in the storage device. The quality of the exposure mask for which a defect has been detected is determined by displaying the defective portion on a display device and observing the mask pattern.
[0004]
If the mask pattern is fine or it is difficult to judge the pass / fail, use a simulation microscope or the like to generate an aerial image on the wafer under the same conditions as the actual exposure conditions and measure the light intensity distribution. I do. The quality of the exposure mask is determined based on the measurement result.
[0005]
With reference to FIG. 6, a description will be given of a conventional mask pattern pass / fail determination method and its problem.
FIG. 6A shows a plan view of two mask patterns 100 and 101 for forming a gate electrode of a MOSFET. At the end of one mask pattern 101, a defect 102 in which a part of the pattern is missing has occurred.
[0006]
FIG. 6B is a plan view of aerial images 100A and 101A of the two mask patterns 100 and 101 on the wafer surface. Both ends of the aerial image 100 </ b> A of the mask pattern 100 having no defect extend over the outer periphery of the active region 110. In the aerial image 101A of the mask pattern 101 including the defect 102, the edge where the defect 102 occurs is slightly receded. However, the receding end also covers the outer periphery of the active region 110. Therefore, it is determined that the defect 102 of the mask pattern 101 does not need to be corrected.
[0007]
FIG. 6C shows a plan view of resist patterns 100B and 101B formed based on the aerial images 100A and 101A of FIG. 6B. Corresponding to the retreat of the leading end of the aerial image 101A, the leading end of the resist pattern 101B is also receding. Depending on the resist material, development conditions, baking conditions, and the like, the receding amount increases.
[0008]
FIG. 6D is a plan view of the gate patterns 100C and 101C formed using the resist patterns 100B and 101B shown in FIG. 6C as an etching mask. In order to shorten the gate length of the MOSFET, a trimming technique of forming a gate pattern smaller than the width of the resist pattern by performing a certain over-etching in some cases may be employed.
[0009]
When the trimming technique is employed, the width of the gate pattern becomes narrower than the width of the resist pattern, and at the same time, the end of the gate pattern recedes from the end of the resist pattern. For this reason, even when the end of the resist pattern 101B shown in FIG. 6C extends over the outer periphery of the active region 110, the end of the corresponding gate pattern 101C recedes to the inside of the active region 110. Resulting in. Therefore, this semiconductor device becomes defective.
[0010]
As described above, when the trimming technique is adopted, the actual semiconductor device becomes defective even when it is determined that the correction is unnecessary based on the aerial image shown in FIG. 6B.
[0011]
Japanese Patent Application Laid-Open No. H11-163,087 considers various conditions in a wafer process, for example, a resist baking condition, a resist composition, a plasma etching condition, and the like, and predicts a pattern formed on a wafer by simulation to determine the quality of an exposure mask. The technology is disclosed.
[0012]
[Patent Document 1]
JP 2001-516898 A
[0013]
[Problems to be solved by the invention]
In the method of predicting a pattern on a wafer in consideration of various conditions of a wafer process, it is difficult to appropriately determine whether or not defect correction is necessary when prediction accuracy is low.
[0014]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an exposure mask that can more accurately determine whether or not the exposure mask needs defect correction.
Another object of the present invention is to provide a method for manufacturing a semiconductor device using the above-described exposure mask.
[0015]
It is still another object of the present invention to provide a defect correction necessity determination apparatus that can be used in the above-described method of manufacturing an exposure mask.
[0016]
[Means for Solving the Problems]
According to one aspect of the present invention, a resist film formed on a wafer is exposed through a mask for exposure on which a mask pattern is formed, under a condition that a spatial image of the mask pattern is formed on the wafer. A method of manufacturing an exposure mask for forming a mask, wherein (a) the size of the aerial image when the size of the aerial image on the wafer surface of the mask pattern is changed within a certain range; Determining in advance the correspondence between the dimensions of the pattern formed by etching the wafer using the resist pattern formed by the above as an etching mask; and (b) forming a mask pattern on a mask blank; (C) a step of obtaining an aerial image on the wafer surface of the mask pattern formed in the step (b), and (d) a step of obtaining the spatial image in the step (c). Predicting the size of the pattern formed on the wafer from the intermediate image based on the correspondence obtained in the step (a); and (e) predicting the pattern dimension predicted in the step (d). Determining whether or not the value falls within an allowable range.
[0017]
According to another aspect of the present invention, when exposing a photosensitive resist film on a wafer through an exposure mask having a mask pattern formed thereon, spatial image data for generating spatial image data of the mask pattern on the wafer Generating means for etching the wafer using the resist pattern formed by the spatial image as a mask when the dimension of the spatial image on the wafer surface of the mask pattern is changed within a certain range; Correspondence storage means for storing a correspondence relationship with the dimensions of the pattern formed by the above, an allowable range storage means for storing an allowable range of the dimensions of the pattern to be formed on the wafer, and a space image data generation means. The size of the pattern formed on the wafer is obtained from the dimensions of the aerial image thus obtained and the correspondence stored in the correspondence storage. Law predicts the predicted size, the allowable range defect correction necessity determining unit and a determining control means whether within the allowable range stored in the storage means.
[0018]
By determining in advance the correspondence between the dimensions of the aerial image and the dimensions of the pattern formed on the wafer, the dimensions of the pattern formed on the wafer can be increased from the dimensions of the aerial image of the mask pattern having a defect. The accuracy can be predicted. By determining the necessity of defect repair based on the predicted value of the pattern dimension, the determination accuracy can be improved.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
With reference to FIGS. 1 and 2, a method for manufacturing an exposure mask according to a first embodiment of the present invention will be described. In the first embodiment, as an example, a method of forming a mask pattern of a KrF excimer laser mask for forming a via hole having a diameter of 120 nm in an interlayer insulating film formed on a semiconductor wafer by using a resist shrink technique will be described. I do.
[0020]
FIG. 1A shows a mask pattern 1 having no defect. A mask pattern 1 composed of a square transmission area is formed in a light shielding area 2 (an area hatched in FIG. 1A). In the light-shielding region 2, a light-shielding film such as chromium (Cr) is disposed.
[0021]
FIG. 1B shows a spatial image 1B of the resist pattern 1 on the wafer surface. A circular aerial image with a diameter of 200 nm is obtained. When the aerial image shown in FIG. 1B is formed on the surface of the positive resist film and development is performed, a circular opening having a diameter of 200 nm is formed in the resist film.
[0022]
FIG. 1C shows a resist pattern after application of the hole shrink technique. The opening immediately after development is reduced, and an opening 1C having a diameter of 120 nm is obtained. The hole shrink can be performed, for example, by applying a solvent to the surface of the resist film and baking. By etching the interlayer insulating film using the resist film to which the hole shrink technique has been applied as an etching mask, a via hole having a diameter of 120 nm can be formed.
[0023]
The radius of the via hole is reduced from 100 nm to 60 nm. This reduction amount of 40 nm is generally called a process shift value.
FIG. 2 shows the correspondence between the diameter of the opening in the resist film before the application of the hole shrink technology and the diameter of the opening after the application of the hole shrink technology. Before applying the hole shrink technology, this correspondence is created by forming openings of various sizes, reducing the diameter of these openings by applying the hole shrink technology, and measuring the diameter of the openings after reducing the diameter. It is required by doing. The diameter of the opening before the application of the hole shrink technology is substantially equal to the diameter of the aerial image shown in FIG. 1B, and the diameter of the opening after the application of the hole shrink technology is the via hole actually formed in the interlayer insulating film. Is approximately equal to the diameter of For this reason, it is also possible to obtain the correspondence between the diameter of the aerial image and the diameter of the via hole.
[0024]
The horizontal axis and the vertical axis in FIG. 2 represent the diameter of the opening before and after application of the Hall shrink technology in the unit of “nm”, respectively. When the diameter of the opening before the application of the Hall shrink technology is 200 nm, the diameter of the opening after the application of the Hall shrink technology becomes 120 nm. As the diameter of the opening before the shrink increases, the diameter of the opening after the shrink also increases, but the relationship is not proportional. For this reason, it is difficult to predict the diameter of the opening after shrinking with high accuracy only by simulation, without experiment. In this embodiment, openings having various diameters are actually shrunk, and the diameters of the openings after the shrink are measured. Therefore, a highly accurate correspondence between the two can be obtained.
[0025]
Based on the correspondence shown in FIG. 2, a highly accurate correspondence between the dimensions of the aerial image and the dimensions of the pattern on the wafer can be obtained. In the embodiment described below, the correspondence between the dimensions of the aerial image obtained based on the correspondence shown in FIG. 2 and the dimensions of the pattern on the wafer is used.
[0026]
FIG. 1D shows an example in which a defect 6 in which a light-blocking region protrudes toward the inside of a transmission region is formed in a mask pattern 5 including a transmission region. FIG. 1E shows a spatial image 5B of the mask pattern 5 having the defect 6. Due to the presence of the defect 6, the diameter of the aerial image 5B becomes smaller than the diameter of the aerial image 200 nm when there is no defect. For example, the diameter of the aerial image 5B is 180 nm. FIG. 1F shows an opening 5C after applying the hole shrink technique to the opening 5B having a diameter of 180 nm. The diameter of the opening 5C is about 100 nm.
[0027]
FIG. 1G shows an example in which a defect 9 whose transmission region protrudes toward the light shielding region is formed in a mask pattern 8 including the transmission region. FIG. 1H shows a spatial image 8B of the mask pattern 8 having the defect 9. Due to the presence of the defect 9, the diameter of the aerial image 8B is larger than the diameter of the aerial image 200 nm in the case where there is no defect. For example, the diameter of the aerial image 8B is 220 nm. FIG. 1I shows an opening 8C after applying the hole shrink technique to the opening 8B having a diameter of 220 nm. The diameter of the opening 8C is about 150 nm.
[0028]
Assuming that the target value of the diameter of the opening after shrinking is 120 nm and the dimensional tolerance is ± 10%, the allowable range of the diameter of the opening is 108 to 132 nm. Since the diameters of the openings 5C and 8C shown in FIGS. 1F and 1I are out of the allowable range, the mask patterns 5 and 8 shown in FIGS. 1D and 1G are used. Need to be fixed.
[0029]
Hereinafter, the manufacturing process of the exposure mask according to the embodiment will be described in order. First, a number of mask patterns are formed on a mask blank. A mask pattern having a defect is extracted by observing a large number of mask patterns. For a mask pattern determined to have a defect (for example, the mask pattern shown in FIGS. 1D and 1G), an aerial image (for example, the aerial image shown in FIGS. 1E and 1H) is formed. Ask. The aerial image can be obtained by using a simulation microscope to generate an aerial image under the same conditions as the actual exposure conditions and measure the light intensity distribution. Note that it is also possible to obtain an aerial image by numerical simulation.
[0030]
Next, the dimension of the aerial image of the mask pattern having a defect is applied to the correspondence between the dimension of the aerial image previously determined based on FIG. The dimensions of the pattern to be performed. Since the correspondence shown in FIG. 2 is obtained from an actual experiment, the dimension can be predicted with high accuracy.
[0031]
When the size prediction result falls within the allowable range of the size of the pattern, the defect of the mask pattern need not be corrected. If the size prediction result is out of the allowable range, it is determined that the defect of the mask pattern needs to be corrected.
[0032]
Next, a defect that is determined to need to be repaired is repaired. As shown in FIG. 1D, a defect in which a light-shielding film remains in a portion that should be a transmission region is repaired by irradiating the defective portion with a laser beam to remove an excess light-shielding film. As shown in FIG. 1 (G), for a defect in which a light-shielding film in a portion to be a light-shielding region has been removed to become a transmissive region, a focused ion beam of carbon is incident on the defect portion to deposit a carbon film. Will be repaired.
[0033]
In the first embodiment, the size of the pattern actually formed on the wafer is predicted, and the necessity of defect correction is determined. When the necessity of defect correction is determined based on the dimensions of the aerial image shown in FIGS. 1E and 1H, the two cases fall within ± 10% of the dimension of the target aerial image. Therefore, it is determined that no correction is required. Determining the necessity of defect correction based on the predicted dimensions of the pattern formed on the wafer shown in FIGS. 1F and 1I erroneously determines that the defect to be corrected is unnecessary. Can be prevented.
[0034]
Next, a method for manufacturing an exposure mask according to a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, as an example, a method of manufacturing a mask pattern of a KrF excimer laser mask for forming a gate electrode having a gate length of 60 nm on a semiconductor wafer by using a trimming technique will be described.
[0035]
FIG. 3A shows a mask pattern 11 having no defect. In the transmissive area 12, two mask patterns 11 each composed of a rectangular light shielding area are formed. In the light-shielding region, a light-shielding film such as chromium (Cr) is disposed.
[0036]
FIG. 3B shows a spatial image 11B of the resist pattern 11 on the wafer surface. A strip-shaped aerial image having a width of 100 nm is obtained. The ends of the aerial image 11B are rounded with corners removed. When the spatial image shown in FIG. 3B is formed on the surface of the positive resist film and development is performed, a belt-like resist pattern having a width of 100 nm is formed.
[0037]
FIG. 3C shows the gate electrode 11C after the trimming technique is applied. Although the width of the resist pattern used as the etching mask is 100 nm, the gate electrode 11C having a width of 60 nm is formed by trimming 20 nm on one side. For example, trimming can be performed by performing over-etching under the condition that the etching is isotropic. This trimming amount is generally called a process shift value.
[0038]
For aerial images of various widths, gate electrodes are actually formed, and the widths of the gate electrodes after trimming are measured. From this measurement result, the correspondence between the width of the aerial image and the width of the gate electrode after trimming is obtained. This correspondence corresponds to the correspondence shown in FIG. 2 in the first embodiment.
[0039]
FIG. 3D shows an example in which a defect 16 in which the light-shielding region protrudes from the longer side of one of the two rectangular mask patterns 15 formed of the light-shielding region toward the transmissive region is formed. Is shown. FIG. 3E shows a spatial image 15 </ b> B of the mask pattern 15 having the defect 16. A protrusion 16B appears at a position corresponding to the defect 16. When the protrusion amount of the protrusion 16B is 10 nm, the width of the aerial image at this portion becomes 110 nm. FIG. 3F shows a gate electrode 15C formed using the resist pattern formed by the aerial image shown in FIG. 3E as an etching mask. A protrusion 16C is formed at a position corresponding to the protrusion 16B of the aerial image 15B. When trimming of 20 nm on one side is performed, the width of the gate electrode at the position of the protrusion 16C becomes 70 nm.
[0040]
FIG. 3G shows an example in which a defect 19 that is recessed inward from the long side of one of the two rectangular mask patterns 18 formed of the light-shielding region is shown. FIG. 3H shows a spatial image 18 </ b> B of the mask pattern 18 having the defect 19. A depression 19 </ b> B appears at a position corresponding to the defect 19. When the depression amount of the depression 19B is 10 nm, the width of the aerial image at this portion is 90 nm. FIG. 3I shows a gate electrode 18C formed using the resist pattern formed by the aerial image shown in FIG. 3H as an etching mask. A depression 19C is formed at a position corresponding to the depression 19B of the aerial image 18B. When trimming is performed on one side at 20 nm, the width of the gate electrode 18C at the position of the recess 19C becomes 50 nm.
[0041]
Assuming that the target value of the gate electrode width after trimming is 60 nm and the dimensional tolerance is ± 10%, the allowable range of the gate electrode width is 54 to 66 nm. Since the width of the gate electrode shown in FIGS. 3F and 3I is out of the allowable range, the mask patterns 15 and 18 shown in FIGS. 3D and 3G need to be modified. There is.
[0042]
The widths of the portions corresponding to the defects in the aerial images 15B and 18B shown in FIGS. 3E and 3H fall within a range of ± 10% of the width of the normal aerial image shown in FIG. ing. For this reason, if it is determined whether the defect needs to be corrected based on the width of the aerial image, it is determined that the defects 16 and 19 shown in FIGS. 3D and 3G do not need to be corrected.
[0043]
In the case of the second embodiment, the correspondence between the width of the aerial image of the gate pattern and the width of the gate electrode formed by the aerial image after trimming is determined in advance. According to this correspondence, the width of the gate electrode after trimming is determined from the width of the aerial image of the gate pattern. It is possible to predict with high accuracy. Since the necessity of correcting a mask pattern defect is determined based on the predicted width of the gate electrode, the accuracy of the determination can be increased.
[0044]
In the first embodiment, the method of determining the necessity of defect repair has been described with reference to the mask pattern for forming a via hole, and in the second embodiment, a mask pattern for forming a gate electrode. The determination method can be applied to the determination of other mask pattern defects.
[0045]
In general, the mask pattern is formed by etching the wafer using the resist pattern formed by the aerial image when the aerial image size on the wafer surface is changed within a certain range and the resist pattern formed by the aerial image as an etching mask. What is necessary is just to obtain the correspondence relationship with the size of the pattern to be performed in advance. With this correspondence, the size of the pattern on the wafer can be predicted with high accuracy from the size of the aerial image.
[0046]
Next, a method of manufacturing an exposure mask according to a third embodiment will be described. In the first and second embodiments, a pattern in which the size of the aerial image is shifted is formed on the wafer by using the hole shrink technique or the trimming technique. The third embodiment is not limited to the case where such a process shift technique is employed.
[0047]
The exposure mask manufactured in the third embodiment includes a region where the arrangement of the mask pattern is dense and a region where the arrangement of the mask pattern is sparser than that. A first correspondence relationship indicating the correspondence between the dimension of the spatial image of the mask pattern in the dense area and the dimension of the pattern formed on the wafer, and the dimension of the spatial image of the mask pattern in the sparse area and the dimension formed on the wafer. A second correspondence relationship indicating the correspondence with the dimensions of the pattern is determined in advance. These correspondences are obtained by actually forming a corresponding pattern on a wafer using a plurality of mask patterns whose dimensions are changed within a certain range, and determining the dimensions of the aerial image and the pattern actually formed on the wafer. By measuring the dimensions of
[0048]
A mask pattern is formed on the mask blank, and the presence or absence of a defect is inspected. An aerial image of the mask pattern determined to have a defect is obtained. When the mask pattern is arranged in a dense area, the size of the pattern formed on the wafer is predicted from the size of the aerial image based on the first correspondence. If the mask pattern is arranged in a sparse region, the size of the pattern formed on the wafer is predicted from the size of the aerial image based on the second correspondence.
[0049]
Generally, the etching rate in a dense area of a pattern is different from the etching rate in a sparse area. For this reason, the degree of the influence of the defect generated in the mask pattern also differs. In the third embodiment, the correspondence between the size of the aerial image and the size of the pattern on the wafer is separately obtained for the dense region and the sparse region, and the pattern size is predicted. For this reason, a prediction error due to a difference in etching rate can be eliminated, and more accurate pattern dimension prediction can be performed.
[0050]
Next, a method for manufacturing an exposure mask according to a fourth embodiment will be described with reference to FIG.
FIG. 4A shows an example of a mask pattern. A linear mask pattern 30 extending in the horizontal direction in the figure and a mask pattern 31 extending in the vertical direction in the figure are arranged. A small distance D between the tip of the mask pattern 31 and the mask pattern 31 ₁ Is defined.
[0051]
FIG. 4B shows another example of the mask pattern. A plurality of linear patterns 32A, 32B, and 32C are arranged in a line along one virtual straight line, and a minute interval D is set between adjacent patterns. ₂ Is defined.
[0052]
FIG. 4C shows an example of a correspondence relationship between a minute interval in an aerial image and an interval between patterns formed on a wafer. This correspondence is represented by the interval D ₁ And D ₂ Is changed within a certain range to form a plurality of mask patterns, and the mask patterns are used to actually form patterns on a wafer.
[0053]
Due to the occurrence of a defect in the mask pattern, the distance D in the aerial image ₁ And D ₂ Is deviated from a desired value, the pattern interval on the wafer can be predicted using the correspondence shown in FIG. Based on the predicted value, the necessity of defect correction is determined.
[0054]
Generally, the distance D in the aerial image ₁ And D ₂ Is shifted, the corresponding interval of the pattern on the wafer does not always fluctuate in proportion to the shift amount in the aerial image. For this reason, it is difficult to predict how much the pattern interval on the wafer will be. As in the fourth embodiment, by previously measuring the space in the aerial image and the space between the corresponding patterns on the wafer in advance, the space between the patterns on the wafer can be predicted with high accuracy. .
[0055]
By determining whether or not the defect needs to be corrected based on the predicted interval between the patterns on the wafer, the determination accuracy can be improved.
Next, a method of manufacturing a semiconductor device using the exposure mask manufactured by the method according to the first to fourth embodiments will be described.
[0056]
First, a photosensitive resist film is formed on the surface of a semiconductor wafer. The photosensitive resist film is exposed and developed through an exposure mask prepared by any one of the first to fourth embodiments. Thus, a resist pattern is formed on the semiconductor wafer.
[0057]
The surface layer of the semiconductor wafer is etched using the resist pattern as an etching mask. As described in the second embodiment, a trimming technique may be applied to this etching. Further, as described in the first embodiment, the hole shrink technique may be applied after forming the resist pattern.
[0058]
FIG. 5 shows a block diagram of a defect repair necessity determination device for executing the above embodiment. The defect correction necessity determination device includes a simulation microscope 40, a defect detection device 43, a spatial image data storage device 41, a correspondence data storage device 42, a defect data storage device 44, a predicted value data storage device 45, and an allowable range data storage device 46. , And a control device 47.
[0059]
The simulation microscope 40 generates a spatial image of a mask pattern of an exposure mask to be inspected. Aerial image data obtained by digitizing the generated aerial image is stored in the aerial image data storage device 41.
[0060]
The defect detection device 43 optically observes the mask pattern of the exposure mask to be inspected, converts the mask pattern into numerical data, and compares the numerical data with the original drawing data. If there is a difference between the two, the part is determined to be a defect, and defect data including the position information of the defect, the type of the pattern having the defect, and the like are stored in the defect data storage unit 44.
[0061]
The correspondence between the size of the aerial image of the mask pattern of the exposure mask to be inspected and the size of the pattern actually formed on the wafer, for example, the correspondence shown in FIG. 2 is stored in the correspondence data storage device 42. Have been.
[0062]
The control device 47 reads defect position information from the defect data storage device 44. The aerial image data of the mask pattern including the defect is obtained from the aerial image data storage device 41. The dimensions of the aerial image are obtained from the obtained aerial image data. The obtained dimensions are applied to the correspondence stored in the correspondence data storage device 42 to predict the dimensions of the pattern actually formed on the wafer. The predicted size is stored in the predicted value data storage device 45.
[0063]
The allowable range data storage unit 46 stores the pattern data of the pattern to be formed on the wafer and the allowable range of the dimension of the pattern formed on the wafer. The control device 47 determines whether or not the predicted value falls within an allowable range. If the predicted value falls within the allowable range, it is determined that the defect need not be corrected. If the predicted value is out of the allowable range, it is determined that the defect needs to be corrected.
[0064]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0065]
【The invention's effect】
As described above, according to the present invention, it is possible to increase the accuracy of determining whether or not a defect in a mask pattern of an exposure mask needs to be corrected.
[Brief description of the drawings]
FIG. 1 is a plan view showing a mask pattern, an aerial image, and a resist pattern (pattern on a wafer) for describing a method of manufacturing an exposure mask according to a first embodiment.
FIG. 2 is a graph showing a relationship between an opening diameter before hole shrink and an opening diameter after hole shrink used in the first embodiment.
FIG. 3 is a plan view showing a mask pattern, an aerial image, and a pattern on a wafer for describing a method of manufacturing an exposure mask according to a second embodiment.
FIG. 4 is a plan view showing a mask pattern of an exposure mask formed by a method according to a fourth embodiment, and a graph showing a relationship between an interval in an aerial image and an interval between patterns on a wafer.
FIG. 5 is a block diagram of a defect correction necessity determination device.
6A is a plan view of a mask pattern having a defect, FIG. 6B is a plan view of an aerial image thereof, FIG. 6C is a plan view of a resist pattern corresponding to the aerial image, and FIG. FIG. 4 is a plan view of a pattern on a wafer formed using the resist pattern.
[Explanation of symbols]
1, 5, 8, 11, 15, 18, 30, 31, 32A to 32C Mask Pattern
1B, 5B, 8B, 11B, 15B, 18B Aerial image
1C, 5C, 8C Opening after hole shrink
2 Shading area
6, 9, 16, 19 defects
11C, 15C, 18C Gate electrode on wafer
40 Simulation microscope
41 Aerial image data storage device
42 Correspondence data storage device
43 Defect detection device
44 Defect data storage device
45 Prediction value data storage device
46 Tolerance data storage device
47 Controller

Claims (5)

Exposure mask for exposing a resist film formed on the wafer under conditions where a spatial image of the mask pattern is formed on the wafer through an exposure mask on which the mask pattern is formed, and forming a resist pattern The method of manufacturing
(A) etching the wafer using the resist pattern formed by the aerial image when the size of the aerial image of the mask pattern on the wafer surface is changed within a certain range and the resist pattern formed by the aerial image as an etching mask; Preliminarily determining the correspondence relationship with the dimensions of the pattern to be formed;
(B) forming a mask pattern on the mask blank;
(C) a step of obtaining an aerial image on the wafer surface of the mask pattern formed in the step (b);
(D) predicting the size of a pattern formed on a wafer from the aerial image obtained in the step (c) based on the correspondence obtained in the step (a);
(E) determining whether or not the predicted value of the pattern dimension predicted in the step (d) is within an allowable range. The mask pattern, from the resist pattern transferred to the resist film on the wafer, for forming a pattern on the wafer the pattern dimensions of which are shifted based on the process shift value,
The correspondence determined in the step (a) is that the pattern formed on the wafer under the condition that the pattern size is shifted based on the dimension of the aerial image of the mask pattern on the wafer and the process shift value The method for manufacturing an exposure mask according to claim 1, wherein the correspondence with the dimension is expressed. The exposure mask includes a dense area and a sparse area where the mask pattern is arranged,
The correspondence obtained in the step (a) is a first correspondence showing the correspondence between the dimension of the spatial image of the mask pattern in the dense area and the dimension of the pattern formed on the wafer, and the sparse area And a second correspondence relationship indicating the correspondence between the dimension of the aerial image of the mask pattern and the dimension of the pattern formed on the wafer,
In the step (d), the size of the pattern formed on the wafer in the dense area is predicted based on the first correspondence, and the size of the pattern formed on the wafer in the sparse area is estimated. The method of manufacturing an exposure mask according to claim 1, wherein the dimension is predicted based on the second correspondence. A step of preparing an exposure mask manufactured by the method for manufacturing an exposure mask according to any one of claims 1 to 3,
Forming a photosensitive resist film on the surface of the semiconductor wafer,
Through the exposure mask, exposing the photosensitive resist film, a step of forming a resist pattern by developing,
Etching the surface layer portion of the semiconductor wafer using the resist pattern as an etching mask. When exposing a photosensitive resist film on a wafer through an exposure mask having a mask pattern formed thereon, a spatial image data generating means for generating spatial image data of the mask pattern on the wafer,
The mask pattern is formed by etching the wafer using the resist pattern formed by the aerial image dimension and the aerial image when the aerial image dimension on the wafer surface is changed within a certain range as an etching mask. Correspondence storage means for storing the correspondence with the size of the pattern,
Tolerance storage means for storing a tolerance of a dimension of a pattern to be formed on the wafer;
From the dimensions of the aerial image generated by the aerial image data generation means and the correspondence stored in the correspondence storage means, the dimensions of the pattern formed on the wafer are predicted, and the predicted dimensions are: A defect correction necessity determining device having a control unit for determining whether or not the defect is within an allowable range stored in the allowable range storage unit.

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