TWI608522B - System for wafer-level phosphor deposition - Google Patents

Description

Wafer level phosphor powder deposition system 【priority】

The present application claims priority to US Patent Application Serial No. 12/963, 011, entitled "System for Wafer-Level Phosphor Deposition", filed on Dec. 8, 2010, and entitled The priority of the U.

This application is generally directed to light emitting diodes, and more particularly to systems for wafer level phosphor powder deposition.

Light-emitting diodes are semiconductor materials that are implanted or doped with impurities that add "electrons" and "holes" into the semiconductor and are relatively free to move within the material. Depending on the type of impurity, the doped region of the semiconductor may have electrons or holes significantly, which may be referred to as n-type or p-type semiconductor regions, respectively.

In LED applications, an LED semiconductor wafer includes an n-type semiconductor region and a p-type semiconductor region. A reverse electric field is created at the junction between the two regions, causing the electrons and holes to be separated from the junction to form the active region. When a forward voltage supply sufficient to overcome the reverse electric field is supplied through the p-n junction, electrons and holes are forced into the active region and combined, and when the electrons are combined with the hole, they fall to a lower energy level and release energy in the form of light. The ability of LED semiconductors to illuminate allows these semiconductors to be used in a variety of lighting devices, such as LED semiconductors, which can be used in indoor lighting applications or in general lighting applications for a variety of outdoor applications.

During fabrication, a large number of LED semiconductor dies are produced on a semiconductor wafer, for example, the wafer may contain more than one hundred dies. The die is cut from the wafer using a process called singulation. The grains are then coated with phosphor powder to control the color of the light emitted by the grains upon energization. The wafers are tested and tested for color, brightness output, power consumption, and any other operational characteristics after coating.

Unfortunately, the cost of coating and testing the grains after die cutting is expensive or complicated, making it difficult to obtain crystals of uniform color, brightness output, or other characteristics.

Therefore, there is a need for a simple and efficient way to apply phosphor powder to a semiconductor wafer and perform tests prior to die cutting to achieve consistent grain characteristics and avoid expensive and complicated processes for individual die.

In one or more aspects, a wafer level phosphor deposition system is provided to perform phosphor coating and testing on a semiconductor wafer prior to die cutting. As such, the system simplifies the phosphor powder deposition process, allowing individual LED semiconductor dies to have consistent operating parameters.

In one aspect, a method is provided for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies. The method includes: covering a semiconductor wafer with a photoresist of a selected thickness; removing a portion of the photoresist material to expose a portion of the semiconductor wafer such that electrical contacts associated with the LED dies remain unattached Exposed; and deposited phosphor powder on the exposed portion of the semiconductor wafer.

In one aspect, an apparatus is provided for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies. The device comprises: a device, For covering a semiconductor wafer with a selected thickness of photoresist material; means for removing a portion of the photoresist material to expose a portion of the semiconductor wafer such that electrical connections are combined with the plurality of LED dies The dots remain unexposed; and means for depositing phosphor powder to deposit phosphor on the exposed bare portion of the semiconductor wafer.

In one aspect, an LED die fabricated by a process is provided, the process comprising: covering a semiconductor wafer comprising the LED die with a selected thickness of photoresist material; removing a portion of the photoresist material, Exposing a portion of the semiconductor wafer such that the electrical contacts of the LED die remain unexposed; depositing phosphor powder on the exposed portion of the semiconductor wafer, removing remaining photoresist material to expose The electrical contacts of the LED die; and performing a die cutting process to cut the LED die from the semiconductor wafer.

In an alternative aspect, a semiconductor wafer includes an LED die, at least one photoresist pillar, and a phosphor deposit layer, wherein at least one of the LED die includes at least one electrical contact. The photoresist column covers at least one electrical contact. In one example, the height of the photoresist column is approximately 200 microns. The photoresist post has a shape that is disposed to cover the at least one electrical contact. The phosphor powder deposition layer is disposed to cover the semiconductor wafer and surround the at least one photoresist column. In one aspect, the semiconductor wafer further includes a carrier wafer attached to the semiconductor wafer. In one aspect, the thickness of the semiconductor wafer is approximately 150 microns. In other examples, the phosphor deposit layer includes at least one recess for exposing at least one electrical contact.

After reading the following brief description, description and patent application scope, you can understand other aspects.

In many aspects, a wafer level phosphor powder deposition system is provided. Fluorescent powder coating and testing is performed on the semiconductor wafer prior to die cutting.

The wafer level phosphor powder deposition system will be described more fully hereinafter with reference to the accompanying drawings in which many specific embodiments are shown. However, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments disclosed herein. Rather, these aspects are provided so that this disclosure will be thorough enough to fully convey the invention to those skilled in the art. The above-described aspects of the invention are not drawn to scale, and rather, the size of many components may be enlarged or reduced for clarity. In addition, some of the drawings are simplified for clarity. Accordingly, such components or methods of all known devices (eg, devices) may not be depicted in the drawings.

Many aspects of the invention are described herein with reference to a schematic illustration of the idealized construction of the invention. As such, it is contemplated that such exemplified shape changes are, for example, the result of manufacturing techniques and/or tolerances. Therefore, the various aspects of the invention disclosed herein are not to be construed as limited to the particular element shapes (e.g., regions, layers, sections, substrates, etc.) illustrated and described herein, but include, for example Make the difference in shape produced. By way of example, elements illustrated or described as rectangular may have rounded or curved features and/or gradually concentrated edges, rather than discrete variations between elements and elements. Accordingly, the elements illustrated in the figures are illustrative in nature and their shapes are not intended to illustrate the precise shape of the elements and are not intended to limit the scope of the invention.

It can be understood that when an element such as a region, layer, segment, substrate, or the like is referred to as being "above" another element, it may be directly on the other element or the intermediate element. Conversely, when an element is referred to as being "directly" on another element We will further understand that when a component is "formed" on another component, It can be grown, deposited, etched, attached, joined, coupled, or fabricated or fabricated on another element or intermediate element.

Further, the relative terms such as "lower" or "bottom" and "top" or "top" may be used to describe the relationship of one element to another, as exemplified in the figures. It is understood that the relative vocabulary is used to cover different orientations of the device in addition to the orientation depicted in the drawings. By way of example, if the devices in the drawings are turned over, the components on the "lower" side of the other components will become on the "upper" side of the other components. Therefore, the word "below" includes "below" and "above" depending on the particular orientation of the device. Similarly, if the device in the figure is turned over, the components that are "below" or "under" the other components will become "above" the other components. Therefore, the words "below" or "bottom" include the above and below.

All words (including technical and scientific terms) used herein have the same meaning as understood by one of ordinary skill in the art. It is further understood that words such as those defined in commonly used dictionaries should be interpreted as meanings in accordance with the meaning of the related art and the context of the present invention.

As used herein, the singular forms "a", "the", "the" It will be further understood that the "comprises" and/or "comprising" used in the specification indicates the existence of the stated features, integers, steps, operations, components and/or components, but does not exclude one or more other features, The existence or addition of the whole, steps, operations, components, components and/or groups. The term "and/or" includes any and all combinations of one or more of the associated listed items.

I will understand that although the words "first" and "second" are used herein to describe a number of regions, layers and/or segments, such regions, layers and/or Sections should not be limited to these words. These words are only used to distinguish one region, layer or segment from other regions, layers or segments. Thus, the first region, layer or segment discussed below may be termed a second region, layer or segment, and the second region, layer or segment may be termed. A region, layer, or section.

The first figure shows a side view of an exemplary LED semiconductor wafer 100 obtained from a wafer process. For example, in one implementation, the thickness (t) of the LED wafer 100 is approximately 150 microns. The wafer 100 includes any number of LED dies exposed on the surface 102. For example, the LED wafer 100 can include more than one hundred LED dies with associated electrical contacts, as well as illuminating regions formed on the surface 102. During operation, the electrical contacts of each die are energized, causing the associated illumination zone to illuminate.

The second figure shows a side view of an exemplary wafer assembly 200 including the LED wafer 100 in a first view attached to a carrier wafer 202. For example, in one implementation, the carrier wafer 202 includes a sapphire carrier wafer attached to the LED wafer 100 and having a thermal release tape 204. The sapphire carrier wafer 202 is used to support the LED wafer 100 during a phosphor deposition process described below. The thermal release strap allows the sapphire carrier wafer 202 to be easily removed from the LED wafer 100 later. Please note that other types of carrier wafers and additional mechanisms may be used to support the LED wafer 100 during the phosphor deposition process. In one implementation, the wafer 100 is assembled onto the carrier wafer 202 containing the thermal release strip 204 using any suitable automated assembly.

The third figure shows a side view of the wafer assembly 200 and a wafer assembly 300 of a layer of photoresist material 302. The photoresist material 302 is a photosensitive material which is soluble in the photoresist developer after exposure. Any portion of the photoresist material 302 that is not exposed remains insoluble in the photoresist developer. In one implementation, the photoresist material 302 is spin coated to form on the LED wafer 100 Into a thick layer. For example, the photoresist material 302 has a thickness of about two hundred microns. Also note that any suitable photoresist deposition device can be used to apply the photoresist material 302 to the wafer assembly 200.

The fourth diagram shows a side view of a wafer assembly 400 including the wafer assembly 300 after removal of the selected portion of the photoresist layer 302 using a yellow lithography process. For example, the yellow lithography device uses light to transfer a geometric pattern on the reticle onto the photosensitive photoresist layer 302. The exposed portion of the photoresist layer 302 is then removed by the yellow lithography apparatus using a photoresist developer, leaving unexposed portions. In this example, the unexposed portion is illustrated as a photoresist column 402.

In one implementation, the photoresist pillars 402 have a height of approximately two hundred microns and are used to cover the p and n electrical contact pads of all of the LED dies of the LED wafer 100. For example, region 404 includes three photoresist columns 406, 408, and 410. The fifth diagram depicts a top view of these photoresist columns, shown as 412, in more detail.

The fifth figure shows a top view of the wafer assembly 400 shown in the fourth figure, and a detailed view of the area 404 is provided from the perspective of the top view indicator 412. The region 404 includes the photoresist columns 406, 408, and 410 for covering the p and n electrical contacts of the LED dies on the LED wafer 100. Please note that the photoresist columns 406, 408, and 410 can comprise any shape or shape and are not limited to the shape shown in the fifth figure. By covering the p and n contacts, the photoresist columns protect the contacts from the phosphor deposit layer to be deposited on the surface 502 of the LED wafer 100. The phosphor powder deposition is used to control the color of the light emitted by the grains of the LED wafer 100.

The sixth figure shows a side view of a wafer assembly 600 after the deposition of a phosphor layer 602 by the wafer assembly 300 shown in FIG. For example, the phosphor powder deposition can be performed by a deposition apparatus using the following techniques:

1. Electrophoretic Deposition (EPD)

2. Spin coating

3. Spraying

4. Droplet deposition

5. Vacuum evaporation

The phosphor deposition process controls the thickness of the phosphor layer, thereby controlling the color of light emitted from the LED dies. After deposition, the phosphor powder is allowed to cure. As such, any suitable phosphor deposition process can be used to supply a layer of phosphor powder of appropriate thickness onto the wafer assembly 300. Still further, any suitable phosphor material can be used to achieve the resulting illumination with any desired color.

The seventh diagram shows a side view of a wafer assembly 700 after the wafer assembly 600 shown in FIG. 6 removes the photoresist columns 402. For example, in one implementation, the photoresist columns 402 are exposed by the yellow lithography device and the photoresist is applied to a suitable photoresist developer to remove the photoresist columns. Once the photoresist columns 402 are removed, the phosphor layer includes a phosphor region 702 overlying the surface of the LED wafer 100, and a recess 704 through which the p and n contacts are exposed. These pockets 704 allow wire bonding to the bare contacts.

The eighth diagram shows a top view of the combination 700 shown in the seventh diagram, and a detailed view of the region 404 is provided from the perspective of the top view indicator 412. The top view shown in the eighth diagram provides a detailed illustration of the region 404 after removal of the photoresist columns 406, 408, and 410. Once the photoresist columns are removed, the p and n contacts underneath are exposed. For example, removing the photoresist columns 406, 408, and 410 exposes contacts 802, 804, and 806, respectively. Also shown is the surface of the semiconductor that is now covered by the phosphor powder deposit 808.

The ninth diagram shows a wafer assembly 900 after the wafer assembly 700 of FIG. 7 has removed the carrier wafer. For example, the heat release strip 204 is heated to remove the sapphire carrier wafer 202, thus leaving a phosphor containing powder The LED wafer 100 of 702 is deposited.

The tenth graph shows a singulation process performed on the wafer assembly 900. The die cutting process is used to cut the LED wafer assembly 900 into individual dies. In one implementation, the die cutting is performed using a front end laser cutting device that cuts individual dies (ie, 1002, 1004, and 1006).

The eleventh figure shows an associated clor chart 1100 of two parameters (X and Y) with color temperature. For example, the color map 1100 provides an X value along the horizontal axis and a Y value along the vertical axis. Thus, as indicated by the dashed line, the X value of 0.32 corresponds to the Y value of 0.33 to a color temperature of approximately 6000 K (Kelvin). The color map 1100 provides a mechanism for the X and Y values to accurately identify a particular color for the purpose of grading and classifying the dies.

In one implementation, the wafer 900 shown in FIG. 9 is detected and tested using a computerized detection device for the purpose of correlating X and Y values to each die. Simultaneous detection of the entire wafer is more efficient than detecting individual grains after grain cutting. During the probing period, each die is energized and determines the characteristics of many grains. For example, the detection device includes contact points for contacting electrical contacts of each of the dies in the wafer 900. The electrical contacts are exposed through the recesses 704 in the phosphor deposition and are accessible. Once the dies are energized, the detection device measures color temperature, luminance output, voltage, current, and any other operational parameters for each die. In one aspect, the measured parameters for each die are mapped to X and Y values according to the color map 1100. As such, it is associated with its own X and Y values before each die cut.

The twelfth figure shows a chart 1200 and an associated rating table 1202 that can be used for LED die classification and grading prior to die cutting. For example, chart 1200 defines some rankings, each including a range of X and Y values for the color table 1100 from the eleventh image. In this example, the rating D4 includes 0.32 The X value and the Y value of 0.33.

Reference is now made to the rating table 1202, in which a numerical configuration is displayed, such as a rating D4 shown as 1204, associated with a range of X and Y values including 0.32 and 0.33, respectively. The ANSI color temperature for this range is also displayed.

As such, as each die is separated from the wafer during die cutting, its associated X and Y values can be classified into appropriate ratings using the rating table 1202. The dies within each grading are then placed on the tape or packaged using any other packaging method, resulting in a group of dies that will have excellent color consistency. For example, in one implementation, the computerized classification device is used to classify and classify the grains below the X and Y values known to be associated with each die.

A thirteenth diagram shows a method of performing wafer level phosphor powder deposition in accordance with the present invention. For example, method 1300 can be used to perform phosphor powder deposition as described above with respect to wafer 100.

Within block 1302, an LED wafer is obtained from the process, for example, the wafer 100 is obtained for use in a wafer level phosphor deposition process. In one implementation, the wafer 100 includes more than one hundred LED dies.

At block 1304, a support carrier is attached to the LED wafer. For example, the sapphire support carrier 202 is attached to the LED wafer using the thermal release strip 204. The support carrier is used to support the LED wafer during the wafer level phosphor deposition process. In one implementation, the wafer 100 is assembled onto the carrier wafer 202 containing the thermal release strip 204 using any suitable automated assembly.

At block 1306, a photoresist layer is applied to the LED wafer. In one implementation, the photoresist layer is applied using a spin coating process. For example, the photoresist layer is applied to the LED wafer 100 and has a thickness of about two hundred microns. In one implementation, any suitable photoresist deposition device can be used to apply the photoresist material 302 to the wafer combination 200.

At block 1308, a portion of the photoresist layer is removed such that the photoresist pillars cover the p and n contacts of the LED wafer. For example, as shown in the fourth figure, the yellow lithography device uses light to transfer the geometric pattern from the reticle to the photosensitive photoresist layer. The exposed portion of the photoresist layer is then removed using a photoresist developer leaving the unexposed portions. The unexposed portion is a photoresist column 402. The fifth figure shows a top view illustrating how the photoresist columns cover the p and n contacts of the LED wafer.

At block 1310, phosphor powder is deposited on the surface of the LED wafer. As shown in the sixth figure, phosphor powder is deposited on the surface of the LED wafer and surrounds the photoresist columns 402. For example, the deposition apparatus applies the phosphor powder to the surface of the LED wafer using at least one of a spin coating, an EPD, and a jetting process.

At block 1312, the photoresist columns are removed to expose the p and n contacts, for example, in one implementation, by exposing the photoresist columns 402 and applying a suitable photoresist developer, The photoresist columns. Once the photoresist columns 402 are removed, the phosphor layer includes a phosphor region 702 covering the surface of the LED wafer 100, and a recess 704 exposing the p and n contacts through the phosphor layer.

At block 1314, the carrier wafer has been removed, such as by heating the thermal release strip to release the sapphire carrier wafer. In one implementation, the wafer 100 is removed from the carrier wafer 202 using any suitable automated assembly.

At block 1316, the wafer is probed and tested to determine color temperature, brightness output, power consumption, and any other LED characteristics. In addition, the measured color temperature of each die is associated with the X and Y values according to the color map 1100. In one implementation, the wafer is detected and tested using a computerized detection device.

At block 1318, a die dicing process is performed to divide or diced the LED wafer into individual dies. In one implementation, the die cutting is performed using a front end laser cutting process to cut the LED wafer 900 into individual dies. In one implementation, the die cutting is performed using a front end laser cutting device, and the LED wafer assembly 900 is cut into individual dies.

At block 1320, the grains are sorted and classified. For example, based on the hierarchical guide 1200 and the rating table 1202, the grains are ranked using the X and Y values determined during the detection and testing of the block 1316. For example, the level guide 1200 defines one or more ratings associated with the X and Y values. The rankings are further defined within the rating table 1202. The rating table 1202 cross-references the X and Y values of each of the dies to determine the grading number of the dies to be grouped. For example, in one implementation, the grains are graded and classified using computerized grading devices below the X and Y values known to be associated with each die.

Accordingly, wafer level phosphor powder deposition is performed in accordance with operational method 1300 of the present invention. Please note that method 1300 is only one implementation, and the operations of method 1300 can be rearranged or modified within the scope of many aspects. As such, other implementations can be performed in the many aspects of the aspects described herein.

Figure 14 shows an exemplary apparatus 1400 for performing wafer level phosphor powder deposition. For example, device 1400 is suitable for use in producing the semiconductor wafer 600 shown in FIG. In one aspect, the apparatus 1400 is implemented using one or more modules arranged to provide the functionality described herein. For example, in one aspect, each module contains hardware and/or hardware execution software.

The apparatus 1400 includes a first module including means (1402) for covering a semiconductor wafer with a selected thickness of photoresist material, which in one aspect comprises a photoresist deposition apparatus.

The device 1400 also includes a second module including the device (1404), for removing a portion of the photoresist material to expose a portion of the semiconductor wafer such that electrical contacts associated with the LED dies remain unexposed, including a yellow lithography device in one aspect .

The apparatus 1400 includes a third module including means (1406) for depositing phosphor on the exposed portion of the semiconductor wafer, which in one aspect comprises a phosphor deposition apparatus.

The description of the disclosed aspects is provided to enable any person skilled in the art to make or use the invention. A person skilled in the art will appreciate that the various modifications can be made to the various embodiments, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the details of The word "demonstration" is used exclusively to mean "being a model, instance or description". Any aspect described here as "demonstration" does not need to be interpreted as good or superior to other aspects.

Thus, while the description of the wafer level phosphor powder deposition system has been illustrated and described in this specification, it will be appreciated that many variations can be made in the embodiments without departing from the spirit or essential characteristics of the invention. Therefore, the disclosure and description of the present specification are intended to be illustrative and not restrictive, and the scope of the invention is set forth in the following claims.

100‧‧‧LED semiconductor wafer

102‧‧‧ surface

200‧‧‧ wafer combination

202‧‧‧ Carrier Wafer

204‧‧‧Hot release belt

300‧‧‧ wafer combination

302‧‧‧Photoresist material

400‧‧‧ wafer combination

402‧‧‧Light-resistant column

404‧‧‧Area

406‧‧‧Light-resistant column

408‧‧‧Light Bar

410‧‧‧Light Bar

412‧‧‧ Top view indicators

502‧‧‧ surface

600‧‧‧ wafer combination

602‧‧‧Fluorescent layer

700‧‧‧ wafer combination

702‧‧‧Fluorescent powder area

704‧‧‧ recess

802‧‧‧Contacts

804‧‧‧Contacts

806‧‧‧Contacts

808‧‧‧Fluorescent powder deposition

900‧‧‧ wafer combination

1002‧‧‧ grain

1004‧‧‧ grain

1006‧‧‧ grain

1100‧‧‧ color map

1200‧‧‧ Chart

1202‧‧‧ rating scale

1204‧‧‧Class D4

1400‧‧‧ demonstration equipment

1402‧‧‧ device

1404‧‧‧ device

1406‧‧‧ device

The above aspects will be more readily understood by reference to the detailed description of the invention and the accompanying drawings, in which the first figure shows a side view of an exemplary LED semiconductor wafer obtained from a wafer process; One of the wafers of the first figure attached to a carrier wafer demonstrates a side view of the wafer assembly; the third figure shows the wafer combination of the second figure and further includes a photoresist layer; the fourth figure shows the removal of the photoresist The wafer combination of the third figure after the layer selection portion; the fifth figure shows a partial top view of the wafer combination of the fourth figure; the sixth figure shows the wafer combination of the fourth figure after the deposition of the phosphor layer The seventh figure shows the wafer combination of the sixth figure after removing the photoresist column; the eighth figure shows a partial top view of the wafer combination of the seventh figure; the ninth figure shows the seventh figure after the carrier wafer is removed; The wafer combination; the tenth figure shows that the die cutting process is performed on the wafer combination of the seventh figure to obtain individual LED semiconductor grains; and the eleventh figure shows one of the X and Y values accompanying the color temperature. Figure; Figure 12 shows the classification and classification of LED dies FIG exemplary color grading table; FIG thirteenth show an exemplary method for performing wafer level phosphor deposits; and a display for performing a fourteenth FIG wafer level phosphor exemplary deposition apparatus.

1402, 1404, 1406‧‧‧ devices

Claims (16)

A method of depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, the method comprising: covering the semiconductor wafer with a photoresist having a selected thickness of a first height; removing a portion of the light Resisting material, exposing a portion of the semiconductor wafer and retaining a layer of residual photoresist material to form a plurality of electrical contacts having the first height covering the LED die bonding to avoid exposure, wherein the remaining residue a layer of photoresist material to form a plurality of pillars having the first height comprising substantially aligning a bottom surface of all pillars with a plane; and depositing a phosphor powder having a height lower than the first height on the semiconductor wafer Waiting for the exposed portion; and attaching a carrier wafer to support the semiconductor wafer. The method for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies according to claim 1, further comprising removing the remaining photoresist material after depositing the phosphor powder to expose the electrical connections point. The method of depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 2, further comprising performing a die dicing process to dicing the dies from the semiconductor wafer, To form individual grains. An LED die fabricated using a method of phosphor powder deposition on a semiconductor wafer comprising a plurality of LED dies as in claim 3 of the patent application. The method for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies according to claim 2, further comprising detecting the electrical contacts to determine a plurality of colors combined with the dies temperature. A method of depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 5, further comprising mapping the color temperatures to X and Y values associated with a color map. The method for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies according to claim 6 further comprises performing a die dicing process, cutting the dies from the semiconductor wafer to Individual dies are formed, each of which has an associated X and Y value. A method of depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 7, further comprising: identifying one or more gradations in a grading table, wherein each grading comprises X And ranges of Y values; and according to the rating table, the individual crystal grains are classified according to their associated X and Y values. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, the apparatus comprising: means for covering the semiconductor wafer with a photoresist having a selected thickness of a first height; a device for removing a portion of the photoresist material, exposing a portion of the semiconductor wafer and retaining a layer of residual photoresist material to form a plurality of electrical contacts having the first height pillar covering the LED die bonding to avoid Exposed, wherein the remaining layer of photoresist material is retained to form a plurality of pillars having the first height comprising substantially aligning the bottom surfaces of all of the pillars to a plane; means for exposing the semiconductor wafers And depositing a phosphor having a height lower than the first height; and means for detecting the electrical contacts to determine a plurality of color temperatures associated with the LED dies, respectively. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 9, further comprising means for depositing the phosphor powder to remove remaining photoresist material to expose Out of these electrical contacts. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 10, further comprising means for performing a die cutting process, cutting the semiconductor wafer from the semiconductor wafer Grains to form individual grains. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 9, further comprising means for mapping the color temperatures to X and associated with a color map Y value. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 12, further comprising means for performing a die cutting process, cutting the semiconductor wafer from the semiconductor wafer The grains are formed to form individual grains, each having an associated X and Y value. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies according to claim 13 of the patent application, further comprising: means for identifying one or more gradations in a grading table, wherein each A grading includes a range of X and Y values; and means for classifying the individual dies according to their associated X and Y values in accordance with the grading table. An apparatus for depositing phosphor powder on a semiconductor wafer comprising a plurality of LED dies, as in claim 9, further comprising means for attaching a carrier wafer to support the semiconductor wafer. An LED die prepared by a process comprising the following steps: Covering a semiconductor wafer comprising a plurality of LED dies with a photoresist having a selected thickness of a first height; removing a portion of the photoresist material, exposing a portion of the semiconductor wafer and leaving a layer of residual photoresist material to Forming a plurality of electrical contacts having the first height covering the LED dies to avoid exposure, wherein the remaining photoresist layer is retained to form a plurality of pillars having the first height comprising substantially The bottom surface of all the pillars is aligned with a plane; a phosphor having a height lower than the first height is deposited on the exposed portion of the semiconductor wafer; and the remaining photoresist material is removed to expose the LED die And electrical contacts; detecting the electrical contacts to determine a plurality of color temperatures associated with the LED dies; and performing a die dicing process to dicing the LED dies from the semiconductor wafer.