TWI593768B - Film for package of pre-installed type semiconductor - Google Patents

Film for package of pre-installed type semiconductor Download PDF

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Publication number
TWI593768B
TWI593768B TW102132545A TW102132545A TWI593768B TW I593768 B TWI593768 B TW I593768B TW 102132545 A TW102132545 A TW 102132545A TW 102132545 A TW102132545 A TW 102132545A TW I593768 B TWI593768 B TW I593768B
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Taiwan
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film
semiconductor
component
semiconductor sealing
sealing
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TW102132545A
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Chinese (zh)
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TW201410820A (en
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吉田真樹
川本里美
寺木慎
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納美仕有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Epoxy Resins (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Compositions Of Macromolecular Compounds (AREA)

Description

先設置型半導體封裝用膜 First set type semiconductor package film

本發明係關於先設置型半導體密封用膜,詳而言之,係關於覆晶接合(flip chip bonding)所使用之先設置型半導體密封用膜。 The present invention relates to a film for a semiconductor sealing film which is provided first, and more specifically relates to a film for a semiconductor sealing film which is used first in flip chip bonding.

近年來,覆晶接合係作為可對應半導體裝置之配線等更為高密度化、高頻化之半導體晶片的封裝方式而被利用。一般而言,於覆晶接合中,係以被稱為底部填充劑(underfill)之材料密封半導體晶片與基板之間隙。 In recent years, the flip-chip bonding system has been used as a packaging method for a semiconductor wafer which is more dense and high-frequency in accordance with wiring such as a semiconductor device. In general, in flip chip bonding, a gap between a semiconductor wafer and a substrate is sealed with a material called an underfill.

以往,就覆晶接合而言,係進行於焊接等接合半導體晶片與基板後,於半導體晶片與基板之間隙填充熱硬化性之液狀密封樹脂組成物之底部填充劑,以製造半導體裝置之方法。近年來,首先,係於基板塗佈底部填充劑,負載半導體晶片後,藉由同時進行底部填充劑之硬化以及半導體晶片與基板之連接,而可縮短步驟及縮短硬化時間,其結果為可以低成本且低能量來製作半導體裝置之先供給型覆晶接合製程受到注目,而傾向檢討此種製程之液狀密封材樹脂組成物(以下稱為先供給型液狀密封樹 脂組成物)。 In the conventional method, a flip-chip bonding is performed by bonding a semiconductor wafer and a substrate to a gap between a semiconductor wafer and a substrate, and filling an underfill of a thermosetting liquid sealing resin composition to form a semiconductor device. . In recent years, first, after the underfill is applied to the substrate, after the semiconductor wafer is loaded, the hardening of the underfill and the connection of the semiconductor wafer and the substrate are simultaneously performed, whereby the step and the hardening time can be shortened, and as a result, the curing time can be low. The supply-type flip-chip bonding process for manufacturing a semiconductor device at a low cost and low in energy is attracting attention, and the liquid sealing resin composition tending to review such a process (hereinafter referred to as a first supply type liquid sealing tree) Fat composition).

然而,使用先供給型液狀密封樹脂組成物之覆晶接合製程,係有先供給型液狀密封樹脂組成物往半導體晶片上面溢出之問題。第1圖係表示用於說明使用先供給型液狀密封樹脂組成物之覆晶接合製程中的溢出現象之截面的模式圖。第1圖係於形成有配線22之基板21上塗佈先供給型液狀密封樹脂組成物20後,負載形成有凸出式接點(bump)23之半導體晶片24的圖。此時,若先供給型液狀密封樹脂組成物20之供給量多時,會有所謂「於半導體晶片24之側面溢出先供給型液狀密封樹脂組成物20而產生溢出物20B,且再於半導體晶片24的上面溢出先供給型液狀密封樹脂組成物20而產生溢出物20C」的問題。 However, the flip chip bonding process using the first supply type liquid sealing resin composition has a problem that the first supply type liquid sealing resin composition overflows onto the semiconductor wafer. Fig. 1 is a schematic view for explaining a cross section of an overflow phenomenon in a flip chip bonding process using a first supply type liquid sealing resin composition. Fig. 1 is a view showing a semiconductor wafer 24 on which a bump 23 is formed by applying a supply-type liquid sealing resin composition 20 onto a substrate 21 on which a wiring 22 is formed. In this case, when the supply amount of the liquid-type sealing resin composition 20 is large, the overflow of the first supply-type liquid sealing resin composition 20 is generated on the side surface of the semiconductor wafer 24, and the overflow 20B is generated. The upper surface of the semiconductor wafer 24 overflows with the supply of the liquid sealing resin composition 20 to cause the overflow 20C.

為了解決此問題,係研究替代先供給型液狀密封樹脂組成物之使用先設置型半導體密封用膜之封裝方法(以下稱為先設置型覆晶封裝)。於先設置型覆晶封裝中,由於藉由可先設置型半導體密封用膜之厚度與面積控制先設置型半導體密封用膜之供給量,而使先設置型半導體密封用膜之供給量變得容易控制。此先設置型半導體密封用膜中,除了一般作為密封材之特性以外,係要求可撓性、和為了封裝覆晶而在例如60至80℃之預熱時不硬化。又,先設置型覆晶封裝與先供給型相同,亦可製作以低成本且低能量封裝覆晶之半導體裝置。 In order to solve this problem, a method of encapsulating a film for a semiconductor sealing film using a first-prepared type liquid sealing resin composition (hereinafter referred to as a first-arrange type flip chip package) has been studied. In the pre-arranged flip-chip package, the supply amount of the film for the first-prepared semiconductor sealing is facilitated by controlling the supply amount of the film for the semiconductor sealing film of the first-prepared semiconductor sealing film control. In the film for semiconductor sealing of the first-preparation type, in addition to the characteristics generally used as the sealing material, flexibility is required, and it is not hardened at the time of preheating at, for example, 60 to 80 ° C for packaging flip chip. Further, the first type of flip chip package is the same as the first supply type, and a semiconductor device which is flipped with a low cost and low energy package can be fabricated.

作為先設置型半導體密封用膜之成分,思及使用環氧樹脂以滿足一般密封材之要求,再者,使用潛 在性硬化劑以在成膜後硬化。作為使用潛在性硬化劑之環氧樹脂組成物,專利文獻1係揭示一種包含(A)環氧樹脂、(B)可溶解於環氧樹脂之熱塑性樹脂、(C)於70至90℃活性化之加熱硬化型的潛在性硬化劑之環氧樹脂組成物。惟,此環氧樹脂組成物因潛在性硬化劑係於70至90℃活性化,該環氧樹脂組成物會硬化,而無法使用作為先設置型半導體密封用膜。 As a component of the film for the first-prepared semiconductor sealing, it is considered to use an epoxy resin to meet the requirements of a general sealing material, and further, to use a latent The hardener is hardened after film formation. As an epoxy resin composition using a latent curing agent, Patent Document 1 discloses an activation of (A) an epoxy resin, (B) a thermoplastic resin soluble in an epoxy resin, and (C) activation at 70 to 90 ° C. An epoxy resin composition of a heat-curing latent curing agent. However, since the epoxy resin composition is activated by the latent curing agent at 70 to 90 ° C, the epoxy resin composition is hardened, and the film for the first-prepared semiconductor sealing cannot be used.

另一方面,專利文獻2揭示一種膠囊型硬化劑作為潛在性硬化劑,其係包含含有胺系硬化劑(A)之核、及包覆該核之膠囊膜,該膠囊膜包含以胺系硬化劑(A)作為硬化劑之環氧樹脂之硬化物。然而4,由於該膠囊型硬化劑係以「即使於低溫或短時間之硬化條件,仍可得到高連接可靠度、接合強度、及高密封性」為目的(專利文獻2之「發明之揭示」的第2至5行),故於用以封裝覆晶之預熱時即硬化,如此一來便無法使用作為先設置型半導體密封用膜之潛在性硬化劑。 On the other hand, Patent Document 2 discloses a capsule type curing agent as a latent curing agent, which comprises a core containing an amine-based curing agent (A) and a capsule film covering the core, the capsule film comprising an amine-based hardening agent. The agent (A) is a cured product of an epoxy resin as a hardener. However, the capsule type hardener is intended to have high connection reliability, joint strength, and high sealing property even under low temperature or short-term hardening conditions (Patent Document 2, "Disclosure of Invention") The second to fifth lines are hardened when the pre-heating of the flip chip is used, so that the latent hardener which is a film for the first-prepared semiconductor encapsulation cannot be used.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開平6-9758號公報 [Patent Document 1] Japanese Patent Laid-Open No. Hei 6-9758

[專利文獻2]國際公開第2004/037885號 [Patent Document 2] International Publication No. 2004/037885

本發明係以提供一種在用以封裝覆晶之預 熱時不會硬化,而在封裝覆晶時硬化之可用於先設置型覆晶封裝中之先設置型半導體密封用膜為課題。 The present invention provides a pre-conditioning for encapsulation It is not hardened when it is heated, and it is a problem that it can be used for the first-type semiconductor sealing film in the first type of flip chip package.

本發明係關於藉由具有以下構造而解決上述問題之先設置型半導體密封用膜。 The present invention relates to a film for pre-installed semiconductor encapsulation which solves the above problems by having the following structure.

〔1〕一種先設置型半導體密封用膜,其特徵為包含(A)液狀環氧樹脂、(B)熱塑性樹脂、(C)硬化劑、(D)經50至100℃加熱處理之潛在性硬化促進劑及(E)無機填料。 [1] A film for pre-installed semiconductor encapsulation characterized by comprising (A) a liquid epoxy resin, (B) a thermoplastic resin, (C) a hardener, and (D) a heat treatment at 50 to 100 ° C a hardening accelerator and (E) an inorganic filler.

〔2〕如上述〔1〕所記載之先設置型半導體密封用膜,其中,相對於先設置型半導體密封用膜100質量份,(B)成分為10至30質量份。 [2] The film for pre-installed semiconductor encapsulation according to the above [1], wherein the component (B) is 10 to 30 parts by mass based on 100 parts by mass of the film for semiconductor sealing of the first type.

〔3〕如上述〔1〕所記載之先設置型半導體密封用膜,其中,相對於(A)成分與(B)成分之合計量100質量份,(B)成分為15至65質量份。 [3] The film for semiconductor sealing according to the above-mentioned [1], wherein the component (B) is 15 to 65 parts by mass based on 100 parts by mass of the total of the components (A) and (B).

〔4〕如上述〔1〕所記載之先設置型半導體密封用膜,其中,相對於先設置型半導體密封用膜100質量份,(D)成分為2至5質量份。 [4] The film for pre-installed semiconductor encapsulation according to the above [1], wherein the component (D) is 2 to 5 parts by mass based on 100 parts by mass of the film for semiconductor sealing of the first type.

〔5〕如上述〔1〕所記載之先設置型半導體密封用膜,其中,相對於先設置型半導體密封用膜為100質量份,(E)成分為40至70質量份。 [5] The film for pre-installed semiconductor encapsulation according to the above [1], wherein the film (E) is 40 to 70 parts by mass based on 100 parts by mass of the film for semiconductor sealing of the first type.

〔6〕一種使用上述〔1〕所記載之先設置型半導體密封用膜所製造之半導體裝置。 [6] A semiconductor device produced by using the film for pre-installed semiconductor sealing described in the above [1].

根據本發明〔1〕,可提供一種在用以封裝覆 晶之預熱時不會硬化,而在封裝覆晶時硬化,而可用於先設置型覆晶封裝之先設置型半導體密封用膜。 According to the invention [1], a cover can be provided for use in packaging The crystal is not hardened during preheating, and is hardened when the package is flipped, and can be used for the first-prepared semiconductor sealing film which is provided in the flip chip package.

根據本發明〔6〕,可得到可以低成本、低能量來封裝先設置型覆晶所製造之半導體裝置。 According to the invention [6], it is possible to obtain a semiconductor device which can be packaged by a conventionally mounted flip chip at a low cost and with low energy.

1、2‧‧‧半導體裝置 1, 2‧‧‧ semiconductor devices

10‧‧‧先設置型半導體密封用膜 10‧‧‧First-set semiconductor sealing film

10A、30A‧‧‧硬化之先設置型半導體密封用膜 10A, 30A‧‧‧ Hardened first-set semiconductor sealing film

11、21、31‧‧‧基板 11, 21, 31‧‧‧ substrates

12、22‧‧‧配線 12, 22‧‧‧ wiring

13、23‧‧‧凸出式接點 13, 23‧‧‧ protruding contacts

14、24、34‧‧‧半導體晶片 14, 24, 34‧‧‧ semiconductor wafer

20‧‧‧先供給型液狀密封樹脂組成物 20‧‧‧First supply liquid sealing resin composition

20B、20C‧‧‧溢出物 20B, 20C‧‧‧ spills

35‧‧‧剪切工具(Shear tool) 35‧‧‧Shear tool

第1圖係用於說明使用先供給型液狀密封樹脂組成物之覆晶接合製程中之溢出物現象之截面的模式圖。 Fig. 1 is a schematic view for explaining a cross section of a phenomenon of a spill in a flip chip bonding process using a first supply type liquid sealing resin composition.

第2圖係用於說明使用半導體密封用膜封裝之覆晶之截面的模式圖。 Fig. 2 is a schematic view for explaining a cross section of a flip chip using a film for semiconductor encapsulation.

第3圖係表示實施例1所用之(D)成分的DSC測量結果之圖。 Fig. 3 is a view showing the results of DSC measurement of the component (D) used in Example 1.

第4圖係實施例7之截面之掃描式電子顯微鏡照片。 Fig. 4 is a scanning electron micrograph of the cross section of Example 7.

第5圖係實施例1之截面之掃描式電子顯微鏡照片。 Fig. 5 is a scanning electron micrograph of the cross section of Example 1.

第6圖係比較例1之截面之掃描式電子顯微鏡照片。 Fig. 6 is a scanning electron micrograph of the cross section of Comparative Example 1.

第7圖係說明基板與半導體晶片之接合強度的評估方法之模式圖。 Fig. 7 is a schematic view showing a method of evaluating the bonding strength between the substrate and the semiconductor wafer.

本發明之先設置型半導體密封用膜(以下稱為半導體密封用膜)特徵為包含(A)液狀環氧樹脂、(B)熱塑性樹脂、(C)硬化劑、(D)經50至100℃加熱處理之潛在性硬化促進劑及(E)無機填料。 The film for semiconductor sealing according to the present invention (hereinafter referred to as a film for semiconductor sealing) is characterized by comprising (A) a liquid epoxy resin, (B) a thermoplastic resin, (C) a curing agent, and (D) 50 to 100. The potential hardening accelerator and the (E) inorganic filler which are heat treated at °C.

(A)成分可賦予半導體密封用膜硬化性、耐熱性、接合性,並可賦予硬化後之半導體密封用膜耐久性。 (A)成分可列舉為液狀雙酚A型環氧樹脂、液狀雙酚F型環氧樹脂、液狀萘型環氧樹脂、液狀胺基酚型環氧樹脂、液狀聯苯型環氧樹脂、液狀氫化雙酚型環氧樹脂、液狀脂環式環氧樹脂、液狀醇醚型環氧樹脂、液狀環狀脂肪族型環氧樹脂、液狀茀型環氧樹脂等,基於硬化性、耐熱性、接合性、耐久性之觀點,較佳為液狀萘型環氧樹脂、液狀雙酚F型環氧樹脂、液狀雙酚A型環氧樹脂、液狀胺基酚型環氧樹脂、及液狀聯苯型環氧樹脂。再者,基於反應性、硬化密度之觀點,(A)成分之環氧基當量較佳為80至250g/eq。市售品可列舉為新日鐵化學製之雙酚A型環氧樹脂(商品名:YD-128)、新日鐵化學製之雙酚F型環氧樹脂(商品名:YDF870GS)、三菱化學製之胺基酚型環氧樹脂(等級:JER630、JER630LSD)、DIC製之萘型環氧樹脂(商品名:HP4032D)、邁圖高新材料日本公司(Momentive Performance Materials Japan)製(商品名:TSL9906)等。(A)成分可單獨使用亦可併用2種以上該等者。 The component (A) can impart film hardenability, heat resistance, and bondability for semiconductor sealing, and can provide durability of the film for semiconductor sealing after curing. The component (A) may be a liquid bisphenol A epoxy resin, a liquid bisphenol F epoxy resin, a liquid naphthalene epoxy resin, a liquid aminophenol type epoxy resin, or a liquid biphenyl type. Epoxy resin, liquid hydrogenated bisphenol epoxy resin, liquid alicyclic epoxy resin, liquid alcohol ether epoxy resin, liquid cyclic aliphatic epoxy resin, liquid epoxy resin From the viewpoints of hardenability, heat resistance, jointability, and durability, liquid naphthalene type epoxy resin, liquid bisphenol F type epoxy resin, liquid bisphenol A type epoxy resin, liquid form are preferable. Aminophenol type epoxy resin and liquid biphenyl type epoxy resin. Further, the epoxy group equivalent of the component (A) is preferably from 80 to 250 g/eq from the viewpoint of reactivity and hardening density. Commercially available products are bisphenol A type epoxy resin (trade name: YD-128) manufactured by Nippon Steel Chemical Co., Ltd., bisphenol F type epoxy resin manufactured by Nippon Steel Chemical Co., Ltd. (trade name: YDF870GS), Mitsubishi Chemical Corporation Aminophenol-based epoxy resin (grade: JER630, JER630LSD), DIC-made naphthalene epoxy resin (trade name: HP4032D), Momentive Performance Materials Japan (product name: TSL9906) )Wait. The component (A) may be used singly or in combination of two or more.

(B)成分可賦予半導體密封用膜可撓性。(B)成分可列舉為苯氧基樹脂、聚醯亞胺樹脂、聚乙烯樹脂、聚苯乙烯樹脂、聚酯、聚醚、聚醯胺、聚醚酯醯胺,基於減緩硬化後之半導體密封用膜之內部應力之觀點,較佳為苯氧基樹脂。於本文中,苯氧基樹脂係藉由二價酚與環氧氯丙烷(epichlorohydrin,亦稱表氯醇)直接反應之方法、或藉由二價酚之二環氧丙醚與二價酚之加成聚合反應所合成之高分子多羥基聚醚(熱塑性樹脂),稱為重量平均分子量 10,000以上之高分子。重量平均分子量較佳為10,000至100,000,更佳為40,000至80,000。於本文中,重量平均分子量係使用經由凝膠滲透層析法(GPC)之標準聚苯乙烯之標準曲線作為之值。 The component (B) can impart flexibility to the film for semiconductor sealing. The component (B) can be exemplified by a phenoxy resin, a polyimide resin, a polyethylene resin, a polystyrene resin, a polyester, a polyether, a polydecylamine, a polyether ester decylamine, and a semiconductor seal based on slowing hardening. From the viewpoint of the internal stress of the film, a phenoxy resin is preferred. As used herein, a phenoxy resin is a method of directly reacting a divalent phenol with epichlorohydrin (also known as epichlorohydrin) or by a divalent phenol of diglycidyl ether and a divalent phenol. Polymer polyhydroxy polyether (thermoplastic resin) synthesized by addition polymerization, called weight average molecular weight More than 10,000 polymers. The weight average molecular weight is preferably from 10,000 to 100,000, more preferably from 40,000 to 80,000. As used herein, the weight average molecular weight is a standard curve of standard polystyrene via gel permeation chromatography (GPC).

二價酚類可列舉為雙酚A、雙酚F、雙酚S、二羥基萘、雙酚D、雙酚E、雙酚Z、雙酚茀、雙甲酚茀、聯苯酚、鄰苯二酚、間苯二酚、氫醌、2,5-二第三丁基氫醌、或溴化雙酚A等鹵化雙酚類;10-(2,5-二羥基苯基)-10-二氫-9-氧雜-10-膦菲-10-氧化物、10-(2,7-二羥基萘基)-10-二氫-9-氧雜-10-膦菲-10-氧化物、二苯基氧膦基氫醌、二苯基氧膦基萘醌、環伸辛基氧膦基-1,4-苯二酚、或環辛烯基氧膦基-1,4-萘二酚等含膦酚類等,苯氧基樹脂可列舉藉由該等二價酚類與環氧氯丙烷直接反應所製造者、或藉由上述二價酚類與該等酚類之二環氧丙醚化合物之加成聚合反應所合成者。(B)成分更佳為雙酚A型苯氧基樹脂、雙酚F型苯氧基樹脂、雙酚A-雙酚F共聚合型苯氧基樹脂等。當(B)成分為苯氧基樹脂時,被認為會減緩硬化後之先設置型半導體密封用膜之內部應力,故半導體晶片-基板間之壓力減緩,又,因半導體晶片-基板間存在(B)成分而提升貼合性。(B)成分之市售品可列舉為新日鐵化學製之苯氧基樹脂(商品名:YP-50S)等。(B)成分可單獨使用亦可併用2種以上該等者。 The divalent phenols may be exemplified by bisphenol A, bisphenol F, bisphenol S, dihydroxynaphthalene, bisphenol D, bisphenol E, bisphenol Z, bisphenol oxime, biscresol oxime, biphenol, ortho-benzene. Halogenated bisphenols such as phenol, resorcinol, hydroquinone, 2,5-di-t-butylhydroquinone, or brominated bisphenol A; 10-(2,5-dihydroxyphenyl)-10-di Hydrogen-9-oxa-10-phosphinophen-10-oxide, 10-(2,7-dihydroxynaphthyl)-10-dihydro-9-oxa-10-phosphinophen-10-oxide, Diphenylphosphinylhydroquinone, diphenylphosphinylnaphthoquinone, cyclooctylphosphinyl-1,4-benzenediol, or cyclooctenylphosphinyl-1,4-naphthalenediol The phenoxy resin, etc., may be exemplified by a direct reaction of the divalent phenols with epichlorohydrin, or by the above-mentioned divalent phenols and diphenols of the phenols. The synthesis of an ether compound by addition polymerization. The component (B) is more preferably a bisphenol A type phenoxy resin, a bisphenol F type phenoxy resin, or a bisphenol A-bisphenol F copolymerization type phenoxy resin. When the component (B) is a phenoxy resin, it is considered that the internal stress of the film for the first-prepared semiconductor sealing after hardening is slowed down, so that the pressure between the semiconductor wafer and the substrate is slowed down, and the semiconductor wafer-substrate is present ( B) ingredients to improve fit. A commercially available product of the component (B) is phenoxy resin (trade name: YP-50S) manufactured by Nippon Steel Chemical Co., Ltd., and the like. The component (B) may be used singly or in combination of two or more.

(C)成分只要係具有(A)成分之硬化能力者即可,(C)成分可列舉為酚系硬化劑、胺系硬化劑、酸酐系 硬化劑,基於反應性、安定性之觀點,較佳為酚系硬化劑。酚系硬化劑可列舉為酚酚醛清漆(phenol novolac)樹脂、甲酚酚醛清漆樹脂(cresol novolac)等,較佳為酚酚醛清漆樹脂。胺系硬化劑可列舉為鏈狀脂肪族胺、環狀脂肪族胺、脂肪芳香族胺、芳香族胺等,較佳為芳香族胺。酸酐系硬化劑可列舉:四氫酞酸酐、六氫酞酸酐、甲基四氫酞酸酐、甲基六氫酞酸酐、甲基納迪克酸酐(methyl nadic anhydride)、氫化甲基納迪克酸酐、三烷基四氫酞酸酐、甲基環己烯四羧酸二酸酐、酞酸酐、苯偏三酸酐(trimellitic anhydride)、焦蜜石酸二酐(pyromellitic dianhydride)、二苯基酮四羧酸二酸酐、乙二醇雙苯偏三酸酐、甘油雙(苯偏三酸酐)單乙酸酯、十二烯琥珀酸酐、脂肪族二鹼基多元酸酐、氯橋酸酐(chlorendic anhydride)、甲基丁烯基四氫酞酸酐、烷化四氫酞酸酐、甲基海米酸酐(methyl himic anhydride)、經烯基置換之琥珀酸酐、戊二酸酐等,較佳為甲基丁烯基四氫酞酸酐。市售品可列舉:DIC製之酚樹脂硬化劑(商品名:KA-1160)、明和化成製之酚硬化劑(商品名:MEH8000、MEH8005)、日本化藥製之胺硬化劑(商品名:Kayahard A-A)、三菱化學製之酸酐(等級:YH306、YH307)、日立化成工業製之3-甲基-六氫酞酸酐或4-甲基-六氫酞酸酐(商品名:HN-5500)等。(C)成分可單獨使用亦可併用2種以上該等者。 The component (C) may be any one having the curing ability of the component (A), and the component (C) may be a phenolic curing agent, an amine curing agent or an acid anhydride system. The curing agent is preferably a phenolic curing agent from the viewpoint of reactivity and stability. The phenolic curing agent may, for example, be a phenol novolac resin or a cresol novolac resin, and is preferably a phenol novolak resin. The amine-based curing agent may, for example, be a chain aliphatic amine, a cyclic aliphatic amine, a fatty aromatic amine or an aromatic amine, and is preferably an aromatic amine. Examples of the acid anhydride-based curing agent include tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methyl nadic anhydride, hydrogenated methyl nadic anhydride, and three. Alkyl tetrahydrophthalic anhydride, methylcyclohexene tetracarboxylic acid dianhydride, phthalic anhydride, trimellitic anhydride, pyromellitic dianhydride, diphenyl ketone tetracarboxylic dianhydride , ethylene glycol diphenyl trimellitic anhydride, glycerol bis(benzene trimellitic anhydride) monoacetate, dodecene succinic anhydride, aliphatic dibasic polybasic acid anhydride, chlorendic anhydride, methylbutenyl Tetrahydrophthalic anhydride, alkylated tetrahydrophthalic anhydride, methyl himic anhydride, alkenyl substituted succinic anhydride, glutaric anhydride, etc., preferably methylbutenyltetrahydrophthalic anhydride. Commercially available products include a phenol resin hardener (trade name: KA-1160), a phenolic hardener (trade name: MEH8000, MEH8005) manufactured by Minghe Chemical Co., Ltd., and an amine hardener made from Nippon Chemical Co., Ltd. (trade name: Kayahard AA), an anhydride of Mitsubishi Chemical (grade: YH306, YH307), 3-methyl-hexahydrophthalic anhydride or 4-methyl-hexahydrophthalic anhydride (trade name: HN-5500) manufactured by Hitachi Chemical Co., Ltd. . The component (C) may be used singly or in combination of two or more.

藉由(D)成分,可在用以封裝覆晶之預熱時不使半導體密封用膜硬化,而在封裝覆晶時使半導體密封 用膜硬化。於本文中,潛在性硬化促進劑係以胺酯樹脂等為殼(shell),硬化促進劑為核(core)而微膠囊化者,雖為與環氧樹脂母料化(master batch)者,但基於作業性、硬化速度、保存安定性之觀點,仍然較佳。藉由以50至100℃加熱處理已與環氧樹脂母料化之潛在性硬化促進劑,被認為殼之胺酯樹脂會適度地聚合。當潛在性硬化促進劑之加熱處理溫度未達50℃,則預熱時之安定性、覆晶封裝之連接性會不充足;當潛在性硬化促進劑之加熱處理溫度超過100℃,則會導致環氧樹脂與潛在性硬化促進劑之母料半硬化或硬化。(D)成分之加熱處理溫度較佳為60至100℃,更佳為70至100℃,再更佳為70至90℃。 By the component (D), the semiconductor sealing film can be hardened during the preheating for the package flip chip, and the semiconductor can be sealed during the package flip chip. Hardened with a film. In this context, the latent hardening accelerator is a shell with an amine ester resin or the like, and the hardening accelerator is a core and microencapsulated, although it is a master batch with an epoxy resin. However, it is still preferable from the viewpoints of workability, hardening speed, and preservation stability. The chiral urethane resin is considered to be moderately polymerized by heat-treating the latent curing accelerator which has been subjected to the masterbatch of the epoxy resin at 50 to 100 °C. When the heat treatment temperature of the latent hardening accelerator is less than 50 ° C, the stability during preheating and the connectivity of the flip chip package may be insufficient; when the heat treatment temperature of the latent hardening accelerator exceeds 100 ° C, it may result in The masterbatch of epoxy resin and latent hardening accelerator is semi-hardened or hardened. The heat treatment temperature of the component (D) is preferably from 60 to 100 ° C, more preferably from 70 to 100 ° C, still more preferably from 70 to 90 ° C.

(D)成分之加熱處理時間較佳為6至72小時。又,(D)成分之加熱處理溫度為50℃時,較佳為48小時以上,(D)成分之加熱處理溫度為100℃時,較佳為48小時以下,更佳為12小時以下。 The heat treatment time of the component (D) is preferably from 6 to 72 hours. Further, when the heat treatment temperature of the component (D) is 50 ° C, it is preferably 48 hours or longer, and when the heat treatment temperature of the component (D) is 100 ° C, it is preferably 48 hours or shorter, more preferably 12 hours or shorter.

再者,(D)成分之反應開始溫度較佳為110至150℃,更佳為120至142℃。於本文中,係以DSC(示差掃描熱量測量)測量反應開始溫度。於本文中,反應開始溫度係指(D)成分在半導體密封用膜中,潛在性硬化劑使硬化反應開始之溫度,在DSC中,係觀察(D)成分開始發熱之溫度。 Further, the reaction starting temperature of the component (D) is preferably from 110 to 150 ° C, more preferably from 120 to 142 ° C. Herein, the reaction initiation temperature is measured by DSC (differential scanning calorimetry). Herein, the reaction initiation temperature means the temperature at which the (D) component is in the film for semiconductor sealing, the latent curing agent causes the hardening reaction to start, and in the DSC, the temperature at which the component (D) starts to heat is observed.

作為潛在性硬化促進劑,基於保存安定性之觀點,較佳為以胺酯樹脂等微膠囊化之咪唑化合物硬化促進劑;基於作業性、硬化速度、保存安定性之點,更佳 為分散於液狀雙酚A型等液狀環氧樹脂中,而經母料化之微膠囊化咪唑化合物硬化促進劑。咪唑硬化劑可列舉:2-甲基咪唑、2-十一基咪唑、2-十七基咪唑、2-乙基-4-甲基咪唑、2-苯基咪唑、2-苯基-4-甲基咪唑、2,4-二胺基-6-[2’-甲基咪唑基-(1’)]乙基-s-三、2-苯基-4,5-二羥基甲基咪唑、2-苯基-4-甲基-5-羥基甲基咪唑、2,3-二氫-1H-吡咯并[1,2-a]苯并咪唑等,而基於硬化速度、作業性、耐濕性之觀點,較佳為2,4-二胺基-6-[2’-甲基咪唑基-(1’)]乙基-s-三、2,4-二胺基-6-[2’-十一基咪唑基-(1)-乙基-s-三、2,4-二胺基-6-[2’-乙基-4-甲基咪唑基-(1’)1-乙基-s-三等。 The latent curing accelerator is preferably a microencapsulated imidazole compound hardening accelerator such as an amine ester resin, and is preferably dispersed in the viewpoint of workability, curing speed, and storage stability. In the liquid epoxy resin such as liquid bisphenol A type, the masterbatch microencapsulated imidazole compound hardening accelerator. Examples of the imidazole hardener include 2-methylimidazole, 2-undecylimidazole, 2-heptadecylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4- Methylimidazole, 2,4-diamino-6-[2'-methylimidazolyl-(1')]ethyl-s-three , 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, 2,3-dihydro-1H-pyrrolo[1,2-a Benzimidazole or the like, and based on the hardening speed, workability, and moisture resistance, 2,4-diamino-6-[2'-methylimidazolyl-(1')]ethyl- is preferred. S-three 2,4-Diamino-6-[2'-undecylimidazolyl-(1)-ethyl-s-three 2,4-Diamino-6-[2'-ethyl-4-methylimidazolyl-(1')1-ethyl-s-three Wait.

與環氧樹脂母料化之潛在性硬化促進劑之市售品,可列舉:旭化成E-materials製之微膠囊化咪唑化合物硬化劑(商品名:NOVACURE4982(極厚型)、NOVACURE3932(中厚型)、NOVACURE4921(薄型)、HX3722、HXA3932HP)等,較佳為旭化成E-materials製之微膠囊化咪唑化合物硬化劑(商品名:NOVACURE4982(極厚型))。於本文中,極厚型係膠化溫度為140至150℃之潛在性硬化促進劑,中厚型係膠化溫度為100至110℃之潛在性硬化促進劑,薄型係膠化溫度為70至80℃之潛在性硬化促進劑。膠化溫度係以依照JIS K5600-9-1測量膠化時間未達5分鐘時之溫度。(D)成分可單獨使用亦可併用2種以上該等者。 A commercially available product of a latent curing accelerator which is an epoxy resin masterbatch includes a microencapsulated imidazole compound hardener manufactured by Asahi Kasei E-materials (trade name: NOVACURE4982 (very thick type), NOVACURE3932 (medium thick type) ), NOVACURE 4921 (thin type), HX3722, HXA3932HP), etc., preferably a microencapsulated imidazole compound hardener (trade name: NOVACURE 4982 (very thick type)) manufactured by Asahi Kasei E-materials. In this paper, the extremely thick type is a latent hardening accelerator with a gelation temperature of 140 to 150 ° C, the medium thick type is a latent hardening accelerator with a gelation temperature of 100 to 110 ° C, and the thin type gelatinization temperature is 70 to A latent hardening accelerator at 80 °C. The gelation temperature was measured at a temperature at which the gelation time was less than 5 minutes in accordance with JIS K5600-9-1. The component (D) may be used singly or in combination of two or more.

藉由(E)成分,可調整硬化後之半導體密封用膜之彈性率及熱膨脹係數。(E)成分可列舉為矽酸膠 (colloidal silica)、疏水性氧化矽、細微氧化矽、奈米氧化矽等的氧化矽填料(silica filler);氮化鋁、氧化鋁、氮化矽、氮化硼,基於泛用性、電子特性等之觀點,較佳為氧化矽填料。再者,(E)成分之平均粒徑(非粒狀時係其平均最大徑)並無特別限定,係0.05至50μm,較佳為使填料均勻分散於半導體密封用膜中。未達0.05μm時,在封裝時半導體密封用膜之黏度會上升,而有流動性惡化之疑慮。若超過50μm,會變得難以使填料均勻存在於半導體密封用膜中,且有難以將半導體與基板之連接之疑慮。(E)成分之平均粒徑更佳為0.1至30μm,再更佳為0.1至5μm。市售品可列舉:ADMATECHS製之氧化矽(製品名:SO-E2,平均粒徑:0.5μm)、DENKA製之氧化矽((商品名:FB-5D,平均粒徑:5μm)、扶桑化學工業製之(製品名:SP03B,平均粒徑:300nm)等。於本文中,(E)成分之平均粒徑係藉由動態光散射型奈米軌跡粒度分析儀測量。(E)成分可單獨使用亦可併用2種以上該等者。 The elastic modulus and thermal expansion coefficient of the film for semiconductor sealing after curing can be adjusted by the component (E). (E) component can be cited as citric acid gum (colloidal silica), hydrophobic cerium oxide, fine cerium oxide, nano cerium oxide, etc. silica filler; aluminum nitride, aluminum oxide, tantalum nitride, boron nitride, based on versatility, electronic properties From the viewpoint of the like, a cerium oxide filler is preferred. In addition, the average particle diameter of the component (E) (the average maximum diameter in the case of non-granularity) is not particularly limited, but is preferably 0.05 to 50 μm, and it is preferred to uniformly disperse the filler in the film for semiconductor sealing. When the thickness is less than 0.05 μm, the viscosity of the film for semiconductor sealing increases during packaging, and there is a concern that the fluidity is deteriorated. When it exceeds 50 μm, it becomes difficult to uniformly deposit the filler in the film for semiconductor sealing, and it is difficult to connect the semiconductor to the substrate. The average particle diameter of the component (E) is more preferably from 0.1 to 30 μm, still more preferably from 0.1 to 5 μm. Commercially available products include: cerium oxide manufactured by ADMATECHS (product name: SO-E2, average particle diameter: 0.5 μm), cerium oxide manufactured by DENKA (trade name: FB-5D, average particle diameter: 5 μm), hibiscus chemistry Industrial production (product name: SP03B, average particle diameter: 300 nm), etc. In this paper, the average particle size of the component (E) is measured by a dynamic light scattering type nano-track particle size analyzer. (E) component can be separately Two or more of these may be used in combination.

相對於半導體密封用膜100質量份,半導體密封用膜較佳為包含(B)成分7至30質量份,更佳為包含10至30質量份。若7質量份以上,則半導體密封用膜之可撓性變得充足,若為30質量份以下,則半導體密封用膜具有充足的可撓性。若30重量份以上,則半導體密封薄膜容易變脆,而變得難以維持具有可撓性之薄膜狀。 The film for semiconductor encapsulation preferably contains 7 to 30 parts by mass of the component (B), and more preferably 10 to 30 parts by mass, based on 100 parts by mass of the film for semiconductor sealing. When the amount is 7 parts by mass or more, the flexibility of the film for semiconductor encapsulation is sufficient, and when it is 30 parts by mass or less, the film for semiconductor encapsulation has sufficient flexibility. When it is 30 parts by weight or more, the semiconductor sealing film is liable to become brittle, and it becomes difficult to maintain a flexible film shape.

再者,相對於(A)成分與(B)成分之合計量100質量份,半導體密封用膜之(B)成分較佳為15至65質 量份,更佳為15至55質量份。此係因為只要在15質量份以上,則半導體密封用膜之可撓性變得充足,若65質量份以下,則半導體密封用膜具有充足的可撓性。 In addition, the component (B) of the semiconductor sealing film is preferably 15 to 65 in terms of 100 parts by mass of the total of the components (A) and (B). The amount is preferably from 15 to 55 parts by mass. When the amount is 15 parts by mass or more, the flexibility of the film for semiconductor encapsulation is sufficient, and when it is 65 parts by mass or less, the film for semiconductor encapsulation has sufficient flexibility.

(C)成分之硬化劑當量較佳為(A)成分之環氧基當量的0.1至1.1倍,未達0.1倍時,與(A)成分之硬化易變得不充足,而接合易變得不充足。另一方面,(C)成分之硬化劑當量超過1.1倍時,與(A)成分之硬化易變得不充足,變得易產生空隙(void)。再者,(C)成分之硬化劑當量較佳為(B)成分之官能基當量的0.1至0.5倍,未達0.1倍時,硬化易變得不充足,超過0.5倍時,硬化後易變得又硬又脆。基於上述,相對於(A)成分之環氧基當量與(B)成分之官能基當量之合計量,(C)成分之硬化劑當量較佳為0.2至1.6倍。於本文中,(C)成分之硬化劑當量是例如,(C)成分為酚系硬化劑時之酚當量、胺系硬化劑時之胺當量、酸酐系硬化劑時之酸酐當量。 The hardener equivalent of the component (C) is preferably from 0.1 to 1.1 times the epoxy equivalent of the component (A). When the amount is less than 0.1, the hardening of the component (A) tends to be insufficient, and the bonding tends to become insufficient. Insufficient. On the other hand, when the hardener equivalent of the component (C) exceeds 1.1 times, the hardening of the component (A) tends to be insufficient, and voids are likely to occur. Further, the curing agent equivalent of the component (C) is preferably from 0.1 to 0.5 times the functional group equivalent of the component (B), and when it is less than 0.1 times, the curing tends to be insufficient, and when it exceeds 0.5 times, it is liable after hardening. It is hard and brittle. Based on the above, the hardener equivalent of the component (C) is preferably 0.2 to 1.6 times the total amount of the epoxy group equivalent of the component (A) and the functional group equivalent of the component (B). In the present invention, the curing agent equivalent of the component (C) is, for example, a phenol equivalent in the case where the component (C) is a phenol-based curing agent, an amine equivalent in the case of an amine-based curing agent, and an acid anhydride equivalent in the case of an acid-based curing agent.

為了可在用以封裝覆晶之預熱時不使半導體密封用膜硬化,而在封裝覆晶時使半導體密封用膜硬化,相對於半導體密封用膜為100質量份,(D)成分較佳為2至5質量份。又,潛在性硬化劑在與環氧樹脂母料化時,(D)成分之較佳量理當是計算母料中之潛在性硬化劑的量。 In order to cure the film for semiconductor encapsulation without pre-heating the film for flip chip coating, the film for semiconductor encapsulation is cured at the time of encapsulation, and the component (D) is preferably 100 parts by mass with respect to the film for semiconductor encapsulation. It is 2 to 5 parts by mass. Further, when the latent hardener is mastered with the epoxy resin, the preferred component of the component (D) is to calculate the amount of the latent hardener in the masterbatch.

基於硬化後之半導體密封用膜之彈性率與熱膨脹係數之觀點,相對於先設置型半導體密封用膜為100質量份,(E)成分較佳為30至80質量份,更佳為40至70質量份。 The component (E) is preferably 30 to 80 parts by mass, more preferably 40 to 70, in terms of the modulus of elasticity and the coefficient of thermal expansion of the film for semiconductor sealing after curing. Parts by mass.

於半導體密封用膜,在無損本發明之目的的範圍內,依需要可再調配防止配線或凸出式接點遷移(migration)用之離子捕捉劑、松香系助焊劑、酸酐系、醯肼系、羧酸系等助焊劑;矽烷偶合劑等偶合劑、碳黑等的顏料;染料、消泡劑、抗氧化劑、整平劑、搖變劑(thixotropy)、壓力減緩劑、其他添加劑等。基於隱蔽性之觀點,特佳為添加碳黑。又,基於抑制封裝覆晶時之空隙之觀點,較佳為不含有機溶劑,特別是不含低沸點之有機溶劑。 In the film for semiconductor sealing, an ion trapping agent for preventing wiring or protruding contact migration, a rosin-based flux, an acid anhydride system, and an anthraquinone system can be further added as needed within the scope of the object of the present invention. A flux such as a carboxylic acid; a coupling agent such as a decane coupling agent; a pigment such as carbon black; a dye, an antifoaming agent, an antioxidant, a leveling agent, a thixotropy, a pressure reducing agent, and other additives. Based on the point of view of concealment, it is particularly preferable to add carbon black. Moreover, it is preferable to contain no organic solvent, especially an organic solvent which does not contain a low boiling point, from the viewpoint of suppressing the void at the time of a package-molding.

基於覆晶與基板之間隙、以及半導體晶片之凸出式接點的高度與基板之配線的高度之觀點,半導體密封用膜之厚度較佳為10至100μm。 The thickness of the film for semiconductor sealing is preferably from 10 to 100 μm from the viewpoint of the gap between the flip chip and the substrate, and the height of the bump of the semiconductor wafer and the height of the wiring of the substrate.

基於抑制貼合時之空隙、抑制封裝覆晶封時之空隙之觀點,半導體密封用膜之熔融黏度較佳為10,000至40,000PA.s。 The film for semiconductor sealing preferably has a melt viscosity of 10,000 to 40,000 PA from the viewpoint of suppressing the void at the time of bonding and suppressing the void at the time of sealing the package. s.

於支撐物上塗佈半導體密封用膜形成用組成物,接者使之乾燥,可形成半導體密封用膜。支撐物可列舉為聚對酞酸乙二酯(PET)膜等。 A film-forming composition for semiconductor sealing is applied onto a support, and the film is dried to form a film for semiconductor sealing. The support may be exemplified by a polyethylene terephthalate (PET) film or the like.

半導體密封用膜形成用組成物係可藉由依需要一邊同時或分別加熱處理(A)成分至(E)成分及其他添加劑等,一邊將之攪拌、熔融、混合、分散而得到。此等混合、攪拌、分散等之裝置並無特別限定,可使用具備攪拌、加熱裝置之擂潰機(mincer)、三輥磨機(triple roll mill)、球磨機(ball mill)、行星式攪拌機(planetary mixer)、珠磨機 (beads mill)等。再者,亦可將該等裝置適當組合而使用。 The composition for forming a film for semiconductor sealing can be obtained by stirring, melting, mixing, and dispersing the components (A) to (E) and other additives at the same time or separately as needed. The apparatus for mixing, stirring, dispersing, and the like is not particularly limited, and a mincer having a stirring and heating device, a triple roll mill, a ball mill, and a planetary mixer may be used. Planetary mixer) (beads mill) and so on. Further, these devices may be used in combination as appropriate.

於支撐物上塗佈半導體密封用膜形成用組成物之方法並無特別限定,但基於薄膜化、控制膜厚之點,較佳為微凹版法、狹縫(slot die)法、刮刀(doctor blade)法。 The method of applying the composition for forming a film for semiconductor encapsulation on the support is not particularly limited. However, it is preferably a micro-gravure method, a slot die method, or a doctor blade based on the thickness of the film and the thickness of the film. Blade) method.

支撐物上所塗佈之半導體密封用膜形成用組成物之乾燥條件,係可依塗佈厚度等適當設定,例如,可於60至120℃進行1至30分鐘左右。如此所得之半導體密封用膜係未硬化狀態。 The drying conditions of the film-forming composition for semiconductor sealing applied to the support can be appropriately set depending on the coating thickness and the like, and can be, for example, about 60 to 120 ° C for about 1 to 30 minutes. The film for semiconductor sealing obtained in this way is in an unhardened state.

第2圖表示用於說明使用半導體密封用膜之覆晶封裝之截面的模式圖。如第2(A)圖所示,首先,準備形成有配線12之基板11。接著,如第2(B)圖所示,於形成有配線12之基板11上設置半導體密封用膜10,預熱之。之後,如第2(C)圖所示,係以對應基板11上之配線12之方式對準半導體晶片14上所形成之凸出式接點13的位置。於本文中,配線12與凸出式接點13係一起於表面形成焊接層。最後,如第2(D)圖所示,使基板11上之配線12與半導體晶片14上之凸出式接點13接觸後,加熱,於基板11上之配線12與半導體晶片14上之凸出式接點13進行焊接接合之同時進行半導體密封用膜之硬化。使半導體密封用膜成為已硬化之先設置型半導體密封用膜10A。 Fig. 2 is a schematic view for explaining a cross section of a flip chip package using a film for semiconductor encapsulation. As shown in the second (A) diagram, first, the substrate 11 on which the wiring 12 is formed is prepared. Next, as shown in FIG. 2(B), the semiconductor sealing film 10 is provided on the substrate 11 on which the wiring 12 is formed, and is preheated. Thereafter, as shown in Fig. 2(C), the position of the protruding contact 13 formed on the semiconductor wafer 14 is aligned so as to correspond to the wiring 12 on the substrate 11. Herein, the wiring 12 and the protruding contact 13 are formed together to form a solder layer on the surface. Finally, as shown in FIG. 2(D), after the wiring 12 on the substrate 11 is brought into contact with the protruding contacts 13 on the semiconductor wafer 14, the wiring 12 on the substrate 11 and the semiconductor wafer 14 are heated. The output contact 13 is subjected to solder bonding while curing the film for semiconductor sealing. The film for semiconductor sealing is made into the film 16A for the pre-installed semiconductor sealing which has been hardened.

半導體密封用膜之覆晶封裝時之硬化,較佳為於180至300℃進行5至30秒,基於提升生產性之觀點,特佳為於15秒以內使之硬化。 The hardening at the time of flip chip mounting of the film for semiconductor encapsulation is preferably carried out at 180 to 300 ° C for 5 to 30 seconds, and it is particularly preferable to harden it within 15 seconds from the viewpoint of improving productivity.

藉此,本發明之先設置型半導體密封用膜在用以封裝覆晶之預熱時不會硬化,而係在封裝覆晶時硬化,故可使用於先設置型覆晶封裝。再者,亦可在封裝後加入加熱步驟,以促進半導體密封薄膜之硬化。 Thereby, the film for pre-installed semiconductor encapsulation of the present invention does not harden during preheating for encapsulating the flip chip, and is hardened when the package is flipped, so that it can be used for the pre-disposable flip chip package. Furthermore, a heating step may be added after packaging to promote hardening of the semiconductor sealing film.

(實施例) (Example)

本發明係藉由實施例說明,但本發明並不限定於該等者。又,以下之實施例中,只要未另行限制份、%時,即表示質量份、質量%。 The present invention has been described by way of examples, but the invention is not limited thereto. Further, in the following examples, the parts by mass and the % by mass are not limited unless otherwise limited.

[實施例1至21、比較例1至5、參考例1至2] [Examples 1 to 21, Comparative Examples 1 to 5, and Reference Examples 1 to 2]

以表1至3所示之調配方式,調整半導體密封用膜形成用組成物。混合(A)至(D)成分後,將(E)成分混合於甲基乙酮,得到半導體密封用膜形成用組成物。使用刮刀塗佈所得之半導體密封用膜形成用組成物後,進行乾燥,得到厚度為50μm之半導體密封用膜。再者,表1至3中表示以NETZSCH製之DSC(型號:DSC204 F1 Phoenix)測量之(D)成分之反應開始溫度。又,表3中,使用咪唑替代(D)成分之比較例4、5中,反應開始溫度或活性開始溫度之欄內表示咪唑之活性開始溫度。於本文中,活性開始溫度係指咪唑單體活性化之溫度,以DSC自開始發熱的溫度測量。第3圖係表示實施例1所用之(D)成分的DSC測量結果。第3圖之折線表示基準線。由第3圖可知,實施例1所用之(D)成分之開始發熱溫度為110℃。 The composition for forming a film for semiconductor sealing was adjusted in the manner shown in Tables 1 to 3. After mixing the components (A) to (D), the component (E) is mixed with methyl ethyl ketone to obtain a film-forming composition for semiconductor sealing. The obtained composition for forming a film for semiconductor encapsulation was applied by a doctor blade, and then dried to obtain a film for semiconductor sealing having a thickness of 50 μm. Further, Tables 1 to 3 show the reaction starting temperatures of the component (D) measured by DSC (model: DSC204 F1 Phoenix) manufactured by NETZSCH. Further, in Table 3, in Comparative Examples 4 and 5 in which imidazole was used instead of the component (D), the activity starting temperature of imidazole was indicated in the column of the reaction initiation temperature or the activity starting temperature. As used herein, the activity onset temperature refers to the temperature at which the imidazole monomer is activated, as measured by the temperature at which DSC begins to heat up. Fig. 3 is a graph showing DSC measurement results of the component (D) used in Example 1. The broken line in Fig. 3 indicates the reference line. As is apparent from Fig. 3, the starting temperature of the component (D) used in Example 1 was 110 °C.

先設置時之安定性之評估 Assessment of stability when setting first

為了評估先設置型覆晶封裝中之先設置時之安定性,係以Visco analyser製之VAR100測量半導體密封用膜之最低熔融黏度(初期之最低熔融黏度)。接著,以相同方式測量保持於70℃下3小時後之最低熔融黏度。以下述式求得先設置時之安定性(單位:%):(先設置時之安定性)=(3小時後之最低熔融黏度)/(初期之最低熔融黏度)×100。設置時之安定若為160%以下,則為良好。表1至表3係表示設置時之安定性之評估結果。 In order to evaluate the stability in the first setting of the flip chip package, the lowest melt viscosity (initial minimum melt viscosity) of the film for semiconductor sealing was measured by VAR100 manufactured by Visco analyser. Next, the lowest melt viscosity after maintaining at 70 ° C for 3 hours was measured in the same manner. The stability at the first setting (unit: %) was obtained by the following formula: (stability at the time of setting first) = (the lowest melt viscosity after 3 hours) / (the lowest melt viscosity at the beginning) × 100. If the stability at the time of setting is 160% or less, it is good. Tables 1 to 3 show the results of the evaluation of the stability at the time of setting.

基板上之配線與半導體晶片上之凸出式接點的連接性之評估 Evaluation of the connectivity of the wiring on the substrate to the bump contacts on the semiconductor wafer

準備寬度7mm、長度7mm、厚度125μm之Si晶片,該晶片上形成有544個以50μm為間距(pitch)之30μm的凸出式接點。凸出式接點係焊接加蓋於Cu柱(Cu pillar)之凸出式接點。再者,準備具有對應於矽晶片之凸出式接點圖案之配線、且基板厚度為350μm之環氧玻璃基板(epoxyepoxy glass substrate)。將半導體密封用膜載置前述之具有配線之基板,於70℃進行預熱。在經預熱之基板上的配線之上,使用覆晶接合器,以載重30N,200℃使Si晶片上之凸出式接點與基板上配線接觸1.2秒後,升溫,保持於280℃ 10秒後,冷卻至200℃,自覆晶接合器取出,製作評估樣本。以安捷倫科技股份有限公司(Agilent Technologies)製之萬用電表(型號:HP34401A)測量Si晶片上之凸出式接點與基板上之配線間的電阻值(resistance value),電阻值未達設計值之1.1倍的情形為「◎」,設計值之1.1倍以上而在測量器之測量範圍的情形為「○」,因在測量器之測量範圍外而無法測量的情形為「×」。於本文中,電阻值之設計值為29Ω。表1至表3係表示基板上之配線與半導體晶片上之凸出式接點的連接性之評估結果(表中記載為連接性)。 An Si wafer having a width of 7 mm, a length of 7 mm, and a thickness of 125 μm was prepared, and 544 protruding contacts of 30 μm with a pitch of 50 μm were formed on the wafer. The male contacts are soldered to the protruding contacts of the Cu pillar. Further, an epoxy epoxy glass substrate having a wiring corresponding to the bump contact pattern of the germanium wafer and having a substrate thickness of 350 μm was prepared. The semiconductor sealing film was placed on the substrate having the wiring described above, and preheated at 70 °C. On the pre-heated substrate, using a flip chip bonder, the bump contacts on the Si wafer were brought into contact with the wiring on the substrate for 1.2 seconds at a load of 30 N, 200 ° C, and then the temperature was raised and maintained at 280 ° C. After the second, it was cooled to 200 ° C and taken out from the flip chip bonder to prepare an evaluation sample. The resistance value of the bump contact on the Si wafer and the wiring on the substrate was measured by a universal meter (Model: HP34401A) manufactured by Agilent Technologies. Value), the case where the resistance value is less than 1.1 times the design value is "◎", and the design value is 1.1 times or more and the measurement range of the measuring device is "○", which cannot be measured because it is outside the measuring range of the measuring device. The situation is "X". In this paper, the design value of the resistance value is 29Ω. Tables 1 to 3 show the results of evaluation of the connectivity between the wiring on the substrate and the bump contact on the semiconductor wafer (the connection is described as connectivity).

第4圖表示實施例7之截面之掃描式電子顯微鏡照片。第5圖表示實施例1之截面之掃描式電子顯微鏡照片。第6圖表示比較例1之截面之掃描式電子顯微鏡照片。第4圖係連接性評估之結果為「◎」的情形,第5圖為「○」的情形,第6圖為「×」的情形。第6圖中,基板上之配線與半導體晶片上之凸出式接點之間殘留有半導體密封用膜。 Fig. 4 is a scanning electron micrograph of the cross section of Example 7. Fig. 5 is a scanning electron micrograph of the cross section of Example 1. Fig. 6 is a scanning electron micrograph of the cross section of Comparative Example 1. Fig. 4 shows the case where the result of the connectivity evaluation is "◎", the fifth picture shows the case of "○", and the sixth picture shows the case of "x". In Fig. 6, a film for semiconductor sealing remains between the wiring on the substrate and the bump contact on the semiconductor wafer.

空隙產生率之評估 Evaluation of void generation rate

以超音波顯微鏡測量為了評估基板上之配線與半導體晶片上之凸出式接點的連接性所製作之評估樣本,進行空隙產生率之評估。以下述式求得空隙產生率(單位:%):(空隙產生率)=(空隙面積)/(晶片面積)×100。表1至表3係表示空隙產生率之評估結果。 The evaluation of the void generation rate was performed by measuring the evaluation sample prepared by evaluating the connection between the wiring on the substrate and the bump contact on the semiconductor wafer by an ultrasonic microscope. The void generation rate (unit: %) was determined by the following formula: (void generation rate) = (void area) / (wafer area) × 100. Tables 1 to 3 show the results of evaluation of the void generation rate.

基板與半導體晶片的接合強度之評估 Evaluation of bonding strength between substrate and semiconductor wafer

使用為了評估基板上之配線與半導體晶片上之凸出式接點的連接性所製作之評估樣本。第7圖表示說明基板與半導體晶片之接合強度的評估方法之模式圖。準備於150℃乾燥20分鐘之FR-4基板作為基板31,並準備附有 2mm見方的SiN膜之Si晶片作為半導體晶片34。將1mm見方之半導體密封用膜載置於基板31上,於半導體密封用膜上設置(mounting)半導體晶片34。之後,以160℃ 60分鐘使半導體密封用膜硬化,形成硬化之半導體密封用膜30A。使用AIKOH ENGINEERING製之桌上強度實驗器(型號:1605HTP)測量剪切強度(單位:N/mm2)。剪切強度若為3.0N/mm2以上則為良好。表1至表3係表示基板與半導體晶片之剪切強度(表中記載為接合強度)之評估結果。 Evaluation samples made to evaluate the connectivity of the wiring on the substrate to the bump contacts on the semiconductor wafer were used. Fig. 7 is a schematic view showing a method of evaluating the bonding strength between the substrate and the semiconductor wafer. An FR-4 substrate which was dried at 150 ° C for 20 minutes was prepared as the substrate 31, and a Si wafer to which a 2 mm square SiN film was attached was prepared as the semiconductor wafer 34. A film for semiconductor sealing of 1 mm square is placed on the substrate 31, and a semiconductor wafer 34 is mounted on the film for semiconductor sealing. Thereafter, the film for semiconductor sealing was cured at 160 ° C for 60 minutes to form a cured film for semiconductor sealing 30A. The shear strength (unit: N/mm 2 ) was measured using a table strength tester (model: 1605HTP) manufactured by AIKOH ENGINEERING. When the shear strength is 3.0 N/mm 2 or more, it is good. Tables 1 to 3 show the results of evaluation of the shear strength of the substrate and the semiconductor wafer (the joint strength is described in the table).

總結實驗結果,實施例1至21全部的先設置時之安定性、基板上之配線與半導體晶片上之凸出式接點的連接性、空隙產生率、基板與半導體晶片的接合強度之評估結果皆為良好。特別是實施例2至18、20中,基板上之配線與半導體晶片上之凸出式接點的連接性之評估結果係非常良好。相對於此,以40℃加熱處理潛在性硬化促進劑之比較例1的先設置時之安定性與連接性不佳;以110℃加熱處理潛在性硬化促進劑之比較例2,在加熱處理環氧樹脂與潛在性硬化劑之母料時,母料會半硬化,因而無法混合半導體密封用膜形成用組成物。使用未經加熱處理之潛在性硬化促進劑之比較例3,其先設置時之安定性與連接性不佳。參考例1在加熱處理環氧樹脂與潛在性硬化劑之母料時,母料會硬化,因而無法混合半導體密封用膜形成用組成物。使用咪唑1替代(D)成分之比較例4之空隙產生率高。使用咪唑2替代(D)成分之比較例5的基板上之配線與半導體晶片上之凸出式接點的連接性不佳,而導致於先設置時之安定性之評估實驗中便半硬化。使用於50℃經12小時之加熱處理之潛在性硬化劑作為(D)成分之參考例2的先設置時之安定性與連接性不佳。 Summarizing the experimental results, the stability of all of Examples 1 to 21, the connection between the wiring on the substrate and the bump contact on the semiconductor wafer, the void generation rate, and the evaluation results of the bonding strength between the substrate and the semiconductor wafer were summarized. All are good. In particular, in Examples 2 to 18 and 20, the evaluation results of the connection between the wiring on the substrate and the protruding contact on the semiconductor wafer were very good. On the other hand, Comparative Example 1 in which the latent curing accelerator was heat-treated at 40° C. had poor stability and connectivity at the time of first setting; Comparative Example 2 in which the latent curing accelerator was heat-treated at 110° C., in the heat treatment ring In the case of the masterbatch of the oxygen resin and the latent curing agent, the master batch is semi-hardened, so that the film forming composition for semiconductor sealing cannot be mixed. In Comparative Example 3, which used a latent curing accelerator which was not heat-treated, the stability and the connectivity were poor at the time of first setting. In Reference Example 1, when the master batch of the epoxy resin and the latent curing agent was heat-treated, the master batch was hardened, and thus the film forming composition for semiconductor sealing could not be mixed. Comparative Example 4 using imidazole 1 in place of (D) component has a high void generation rate. The wiring on the substrate of Comparative Example 5 in which the imidazole 2 was used instead of the (D) component was not well connected to the protruding contact on the semiconductor wafer, and the semi-hardening was evaluated in the evaluation test of the stability at the time of the first setting. The latent curing agent which was subjected to heat treatment at 50 ° C for 12 hours as the component (D) was poorly set in stability and connectivity.

本發明之先設置型半導體密封用膜在用以封裝覆晶之預熱時不會硬化,而在封裝覆晶時硬化,而可用於先設置型覆晶封裝。因此,藉由使用本發明之先設置型半導體密封用膜,可得到以低成本、低能量封裝先設置型覆晶所製造之半導體裝置。 The film for pre-installed semiconductor encapsulation of the present invention does not harden when it is used for preheating of the package flip chip, but is hardened when the package is flipped, and can be used for the pre-disposable flip chip package. Therefore, by using the film for pre-installed semiconductor encapsulation of the present invention, it is possible to obtain a semiconductor device manufactured by low-cost, low-energy package-first type flip chip.

由於本案的圖式為說明溢出物現象之圖、實施之模式圖、實施例之測量結果、評估方法及照片,不足以代表本案技術特徵,故本案無指定代表圖。 Since the drawing of this case is a diagram illustrating the phenomenon of spillage, the mode diagram of the implementation, the measurement results of the embodiment, the evaluation method and the photograph, which are not sufficient to represent the technical features of the case, there is no representative representative figure in this case.

Claims (6)

一種先設置型半導體密封用膜,其係包含(A)液狀環氧樹脂、(B)熱塑性樹脂、(C)硬化劑、(D)經50至100℃加熱處理之潛在性硬化促進劑及(E)無機填料。 A film for pre-installed semiconductor sealing comprising (A) a liquid epoxy resin, (B) a thermoplastic resin, (C) a curing agent, (D) a latent curing accelerator which is heat-treated at 50 to 100 ° C, and (E) Inorganic filler. 如申請專利範圍第1項所述之先設置型半導體密封用膜,其中,相對於先設置型半導體密封用膜為100質量份,(B)成分為10至30質量份。 The film for a semiconductor sealing film according to the first aspect of the invention, wherein the film for the semiconductor sealing film of the first type is 100 parts by mass, and the component (B) is 10 to 30 parts by mass. 如申請專利範圍第1項所述之先設置型半導體密封用膜,其中,相對於(A)成分與(B)成分之合計量為100質量份,(B)成分為15至65質量份。 The film for a semiconductor sealing film according to the first aspect of the invention, wherein the total amount of the component (A) and the component (B) is 100 parts by mass, and the component (B) is 15 to 65 parts by mass. 如申請專利範圍第1項所述之先設置型半導體密封用膜,其中,相對於先設置型半導體密封用膜為100質量份,(D)成分為2至5質量份。 The film for a semiconductor sealing film according to the first aspect of the invention, wherein the film for the semiconductor sealing film of the first type is 100 parts by mass, and the component (D) is 2 to 5 parts by mass. 如申請專利範圍第1項所述之先設置型半導體密封用膜,其中,相對於先設置型半導體密封用膜為100質量份,(E)成分為40至70質量份。 The film for a semiconductor sealing film according to the first aspect of the invention, wherein the film for the semiconductor-sealing type is 100 parts by mass, and the component (E) is 40 to 70 parts by mass. 一種半導體裝置,其係使用申請專利範圍第1項所述之先設置型半導體密封用膜所製造。 A semiconductor device manufactured by using the film for pre-installed semiconductor sealing described in claim 1 of the patent application.
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