TWI593090B - Pixel structure, method for manufacturing the same, and thin film transistor - Google Patents

Description

Pixel structure, manufacturing method thereof and thin film transistor

The present invention relates to a pixel structure, a method of fabricating the same, and a thin film transistor.

Among the various electronic products of household appliances and equipment. Among them, a liquid crystal display using a thin film transistor (TFT) has been widely used. The thin film transistor type liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer, wherein the thin film transistor array substrate is provided with a plurality of thin film transistors arranged in an array, and A thin film transistor corresponds to a configured pixel electrode to form a pixel structure. In the provided thin film transistor, the thin film transistor includes a gate, a drain, a source and a channel layer to constitute a switching element in the pixel structure.

However, among the structures of thin film transistors, the performance of the pixel structure may be affected by this parasitic capacitance due to the problem that parasitic capacitance is generated therein. Further, when parasitic capacitance is generated in the thin film transistor structure, the picture quality of the liquid crystal display may be affected. For example, the parasitic capacitance may cause a problem of uneven brightness and darkness of the liquid crystal display.

An embodiment of the present invention provides a pixel structure in which a parasitic capacitance generated between one of a source and a drain and a gate is reduced by a second insulating layer. Reduce the feedthrough voltage and gate load so that the display panel with pixel structure can have better quality.

One embodiment of the present invention provides a pixel structure including a substrate, a gate, a channel layer, a first insulating layer, a source, a drain, and a second insulating layer. The gate is disposed on the substrate. The channel layer is disposed on the substrate. The first insulating layer is disposed between the gate and the channel layer. The source is electrically connected to the channel layer. The drain is electrically connected to the channel layer. The second insulating layer is disposed between the portion of one of the source and the drain which is perpendicularly projected in the channel layer and the gate, wherein the vertical projection falls on one of the source and the drain of the channel layer. The vertical distance between a portion and the gate is a first distance, and the vertical distance between the source and the drain of one of the source and the drain in the channel layer is a second distance, wherein A distance includes at least a thickness of the second insulating layer, and the first distance is greater than the second distance.

In some embodiments, the vertical projection of the channel layer to the gate falls within the gate.

In some embodiments, the first insulating layer covers the surface of the gate facing away from the substrate, and the second insulating layer is disposed on a portion of the source and the drain and a portion of the channel layer that are vertically projected in the channel layer. between.

In some embodiments, the second insulating layer is disposed between the partial drain and the partial channel layer, and the opposite surfaces of the second insulating layer are completely covered by the partial drain and the partial channel layer, respectively.

In some embodiments, the channel layer, the source, the drain, and the second insulating layer are located between the substrate and the first insulating layer, and the gate is disposed on a surface of the first insulating layer facing away from the substrate.

In some embodiments, the pixel structure further comprises a masking layer. The shielding layer is located between the substrate and the channel layer, wherein a vertical projection of the channel layer to the shielding layer falls within the shielding layer.

In some embodiments, the second insulating layer is disposed on the first insulating layer toward one of the source and the drain and the surface facing the channel layer, and the vertical projection of the second insulating layer to the channel layer falls on the source and One of the bungee poles is within the vertical projection of the channel layer.

In some embodiments, the second insulating layer is disposed on a surface of the first insulating layer facing away from the source and the drain and the back channel layer, and the vertical projection of the second insulating layer to the channel layer falls on the source One of the pole and the bungee is within the vertical projection of the channel layer.

In some embodiments, the second insulating layer has a thickness of from 300 nanometers (nm) to 400 nanometers (nm).

In some embodiments, the pixel structure further includes a gate on array (GOA) unit. The gate driving circuit includes a first conductive unit and a second conductive unit. The first conductive unit is disposed on the substrate and electrically connected to the gate. The second conductive unit is disposed above the first conductive unit.

In some embodiments, the pixel structure further includes a passivation layer and a pixel electrode. The passivation layer is located on the first insulating layer, the channel layer, the second insulating layer, the source and the drain. The passivation layer has via holes to expose at least a portion of the drain. The pixel electrode is located on the passivation layer and is electrically connected to the drain through the through hole. Pixel electrode, 汲 The vertical projection of the passivation layer and the gate on the substrate at least partially overlaps.

One embodiment of the present invention provides a method of fabricating a pixel structure, comprising the following steps. A gate is formed on the substrate. A first insulating layer is formed on the substrate and the gate. Forming a semiconductor layer on the first insulating layer and patterning the semiconductor layer into a channel layer, wherein the channel layer has a source connection portion and a drain connection portion. A second insulating layer is formed and the second insulating layer is patterned such that a vertical projection of the patterned second insulating layer to the channel layer falls within one of the source connection and the drain connection. Forming a metal layer on the first insulating layer, the channel layer and the second insulating layer, and patterning the metal layer into a source and a drain, wherein the source is electrically connected to the source connecting portion, and the drain is electrically connected to the drain And a second insulating layer is located between one of the source and the drain and the gate.

In some embodiments, the patterned semiconductor layer and the patterned second insulating layer are processed through a same half-tone mask process, and the step of patterning the semiconductor layer and patterning the second insulating layer includes The following steps. Forming a second insulating layer on the semiconductor layer and forming a photoresist layer on the second insulating layer. The photoresist layer is exposed through a half-step mask, and the photoresist layer is developed. A first etching process is performed to pattern the semiconductor layer and the second insulating layer, and a portion of the photoresist layer is removed to expose the patterned second insulating layer. A second etching process is performed to remove the partially patterned second insulating layer and expose a portion of the channel layer.

In some embodiments, the method for fabricating the pixel structure further includes the following steps. A passivation layer is formed over the first insulating layer, the channel layer, the second insulating layer, the source and the drain. A via hole is formed in the passivation layer to expose at least a portion of the drain. Forming a pixel electrode on the passivation layer, and electrically connecting the pixel electrode to the drain electrode through the through hole, wherein the pixel electrode, the drain electrode, the passivation layer and the gate are perpendicular to the substrate The projections at least partially overlap.

In some embodiments, the method for fabricating the pixel structure further comprises forming a gate driving circuit unit, wherein the step of forming the gate driving circuit unit comprises the following steps. Forming a first conductive unit on the substrate, wherein the first conductive unit and the gate are formed through the same mask process. Forming a second conductive unit on the second insulating layer, wherein the second conductive unit, the source and the germanium are formed through the same mask process.

One embodiment of the present invention provides a method of fabricating a pixel structure, comprising the following steps. A metal layer is formed on the substrate, and the metal layer is patterned into a source and a drain. A semiconductor layer is formed on the source and the drain, and the semiconductor layer is patterned into a channel layer. A first insulating layer is formed, wherein a vertical projection of the first insulating layer to the channel layer overlaps with a vertical projection of a portion of one of the source and the drain to the channel layer. A second insulating layer is formed on the source, the drain, the channel layer and the first insulating layer. Forming a gate on the second insulating layer.

In some embodiments, the method for fabricating the pixel structure further includes forming a shielding layer on the substrate before the step of forming the metal layer on the substrate, wherein a vertical projection of the channel layer to the shielding layer falls within the shielding layer.

One embodiment of the present invention provides a thin film transistor including a substrate, a gate, a channel layer, a first insulating layer, a first electrode, and a second electrode. The gate is disposed on the substrate. The channel layer is disposed on the substrate. The first insulating layer is disposed between the gate and the channel layer. The first electrode and the second electrode are electrically connected to the channel layer, wherein a first capacitor is formed between the first electrode and the gate, a second capacitor is formed between the second electrode and the gate, and the first capacitor is greater than the second capacitor.

In some embodiments, the difference between the first capacitor and the second capacitor It is about 10pF to 100pF.

One embodiment of the present invention provides a thin film transistor including a substrate, a gate, a channel layer, a first insulating layer, a first electrode, and a second electrode. The gate is disposed on the substrate. The channel layer is disposed on the substrate. The first insulating layer is disposed between the gate and the channel layer. The first electrode and the second electrode are electrically connected to the channel layer, wherein a maximum vertical distance between the first electrode and the gate and a maximum vertical distance between the second electrode and the gate are about 300 angstroms to about 10,000 angstroms.

100A, 100B, 100C, 100D, 100E, 100F‧‧‧ pixel structure

102‧‧‧Substrate

104‧‧‧ gate

106‧‧‧First insulation

107‧‧‧Semiconductor layer

108‧‧‧Channel layer

108d‧‧‧汲pole connection

108s‧‧‧Source connection

109‧‧‧Auxiliary layer

110‧‧‧ source

112‧‧‧汲polar

113, 113a, 113a1, 113a2, 113b, 113b1, 113b2‧‧‧ photoresist layer

114, 114a, 114a1, 114a2, 114b, 114c‧‧‧ second insulation layer

115‧‧‧Half-step mask

116‧‧‧First passivation protective layer

118‧‧‧ Passivation layer

120‧‧‧through hole

122‧‧‧Common electrode

124‧‧‧Second passivation protective layer

126‧‧‧ pixel electrodes

130‧‧‧Gate drive circuit unit

132‧‧‧First Conductive Unit

134‧‧‧Second conductive unit

140‧‧‧Shielding layer

D1‧‧‧First distance

D2‧‧‧Second distance

T1, T2‧‧‧ thickness

Fig. 1 is a cross-sectional view showing the pixel structure of the first embodiment of the present invention.

2A to 2K are cross-sectional views showing the pixel structure of Fig. 1 at different stages of the fabrication flow.

Fig. 3 is a cross-sectional view showing the pixel structure of the second embodiment of the present invention.

Fig. 4 is a cross-sectional view showing the pixel structure of the third embodiment of the present invention.

Fig. 5 is a cross-sectional view showing the pixel structure of the fourth embodiment of the present invention.

Fig. 6 is a cross-sectional view showing the pixel structure of the fifth embodiment of the present invention.

7A to 7G are cross-sectional views showing the pixel structure of Fig. 6 at different stages of the fabrication process.

Fig. 8 is a cross-sectional view showing the pixel structure of the sixth embodiment of the present invention.

9A to 9D are cross-sectional views showing the pixel structure of Fig. 8 at different stages of the fabrication process.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

In view of the parasitic capacitance, there may be a problem of uneven brightness and darkness on the liquid crystal display. In view of the above, in the pixel structure of the present invention, the parasitic capacitance generated between one of the source and the drain and the gate can be reduced by the arrangement of the second insulating layer, thereby reducing the feedthrough voltage and the gate. Extremely loaded, so that the display panel with the pixel structure can have better quality and improve the problem of uneven brightness.

Fig. 1 is a cross-sectional view showing a pixel structure 100A according to a first embodiment of the present invention. The pixel structure 100A includes a substrate 102, a gate 104, a first insulating layer 106, a channel layer 108, a source 110, a drain 112, a second insulating layer 114b, a first passivation protective layer 116, a passivation layer 118, and a common electrode 122. The second passivation protective layer 124 and the pixel electrode 126. Further, the combination of the substrate 102, the gate 104, the channel layer 108, the first insulating layer 106, the source 110, the drain 112, and the second insulating layer 114b may be considered to constitute at least one thin film transistor.

The gate 104 is disposed on the substrate 102. The channel layer 108 is disposed on the substrate 102. The first insulating layer 106 is disposed between the gate 104 and the channel layer 108. In FIG. 1 , the components stacked upward from the substrate 102 are sequentially the gate 104 , the first insulating layer 106 and the channel layer 108 , wherein the first insulating layer 106 covers the surface of the gate 104 facing away from the substrate 102 (ie, the gate 104 ). Upper surface). That is, the painting depicted in Figure 1 The prime structure 100A shows a bottom gate thin film transistor structure. In addition, the source 110 is electrically connected to the channel layer 108 , and the drain 112 is also electrically connected to the channel layer 108 .

In the present embodiment, the second insulating layer 114b is disposed between the drain 112 and the gate 104 that are vertically projected in the channel layer 108. In other embodiments, the second insulating layer 114b is disposed between the source 110 and one of the gates 104 that are disposed in the channel layer 108 in a vertical projection.

In other words, the second insulating layer 114b may be disposed between the one of the source 110 and the drain 112 and the gate 104 which are vertically projected in the channel layer 108. In addition, in the embodiment in which the second insulating layer 114b is disposed between the drain 112 and the gate 104, the second insulating layer 114b may not be disposed between the source 110 and the gate 104. Similarly, in the embodiment in which the second insulating layer 114b is disposed between the source 110 and the gate 104, the second insulating layer 114b may not be disposed between the drain 112 and the gate 104.

Further, the second insulating layer 114b is disposed between a portion of the portion of the drain 112 and a portion of the channel layer 108 that is vertically projected within the channel layer 108. That is, for the surface of the drain 112 facing the gate 104, a portion thereof is the connection channel layer 108, and the other portion is connected to the second insulating layer 114b. In other words, the second insulating layer 114b is disposed between the partial drain 112 and the partial channel layer 108, and the opposite surfaces of the second insulating layer 114b are completely covered by the partial drain 112 and the partial channel layer 108, respectively.

In this configuration, the vertical distance between a portion of the drain 112 that is vertically projected in the channel layer 108 and the gate 104 is a first distance D1, and a vertical projection of a portion of the source 110 that falls within the channel layer 108 is Between gates 104 The vertical distance is the second distance D2, wherein the first distance D1 includes at least the thickness of the second insulating layer 114b, and the second distance D2 is exemplified by the thickness of the second insulating layer 114b. The above description "the first distance D1 includes at least the thickness of the second insulating layer 114b" means that the thickness of the second insulating layer 114b is included in the range of the first distance D1. For example, in the present embodiment, the first distance D1 includes at least the thickness of the second insulating layer 114b, the thickness of the channel layer 108, and the thickness of the first insulating layer 106. Further, the second distance D2 includes at least the thickness of the channel layer 108 and the thickness of the first insulating layer 106. Further, in FIG. 1, the first distance D1 is the vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114b. The second distance D2 is the vertical distance between the source 110 toward the surface of the gate 104 and the channel layer 108 and the surface of the gate 104 toward the channel layer 108 and the source 110.

Since the first distance D1 further includes the thickness of the second insulating layer 114b with respect to the second distance D2, the first distance D1 may be greater than the second distance D2. By the configuration in which the first distance D1 is greater than the second distance D2, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, thereby reducing the feed through voltage and the gate loading. Therefore, after the feedthrough voltage and the gate load generated between the drain 112 and the gate 104 are reduced by this configuration, the display panel to which the pixel structure 100A is applied can have better quality.

In other words, if a first capacitance is formed between the source 110 and the gate 104, a second capacitance is formed between the drain 112 and the gate 104, wherein the first capacitance is, for example, a gate/source capacitance (CGS), and the second capacitance is, for example, It is a gate/drain capacitance (CGD). By the second insulating layer 114b disposed between the drain 112 and the gate 104, the second capacitance can be lowered, so that the first capacitance is greater than the second capacitance. The feedthrough voltage and gate load are reduced. On the other hand, in some embodiments, the thickness of the second insulating layer 114b is exemplified by 300 nanometers (nm) to 400 nanometers (nm). By adjusting the thickness of the second insulating layer 114b, the magnitude of the first distance D1 can be adjusted such that the second capacitance (gate/drain capacitance) is adjustable.

In addition to this, the vertical projection of channel layer 108 to gate 104 falls within gate 104. In other words, the vertical projected area of the channel layer 108 to the substrate 102 is less than or equal to the vertical projected area of the gate 104 to the substrate 102, and the vertical projection of the channel layer 108 to the substrate 102 falls within the range of the vertical projection of the gate 104 to the substrate 102. Or consistent with it. In this configuration, since the gate 104 can shield the light from the substrate 102 toward the channel layer 108 from the side of the channel layer 108, the photocurrent generated by the channel layer 108 due to illumination can be avoided, thereby preventing leakage. .

On the other hand, the first passivation protective layer 116 and the passivation layer 118 are located on the first insulating layer 106, the channel layer 108, the second insulating layer 114b, the source 110 and the drain 112, wherein the passivation layer 118 is located in the first passivation protection. The upper surface of layer 116 covers the first passivation protective layer 116. The first passivation protective layer 116 and the passivation layer 118 have via holes 120 to expose at least a portion of the drain 112. The second passivation protection layer 124 is on the passivation layer 118, and the common electrode 122 is located between the second passivation protection layer 124 and the passivation layer 118.

The pixel electrode 126 is disposed on the passivation layer 118, the common electrode 122, and the second passivation protection layer 124. The pixel electrode 126 is electrically connected to the drain electrode 112 through the through hole 120. The vertical projections of the pixel electrode 126, the drain 112, the passivation layer 118, and the gate 104 on the substrate 102 at least partially overlap. Similarly, since the pixel electrode 126, the drain 112, the passivation layer 118 and the vertical projection of the gate 104 on the substrate 102 at least partially overlap, the gate 104 can be used to shield the back channel layer from the substrate 102. One side of the light 108 is directed to the light of the pixel electrode 126 to prevent the photoreceptor electrode 126 from generating a photocurrent to generate electric leakage.

In summary, in the pixel structure 100A, by providing the second insulating layer 114b, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, thereby reducing the feedthrough voltage and the gate load, so that the application is performed. The display panel of the pixel structure 100A can have better quality and improve the problem of uneven brightness and darkness. On the other hand, the gate 104 in the pixel structure 100A can be used as a light that is incident on the pixel structure 100A from the side of the substrate 102 facing away from the channel layer 108 to prevent the channel layer 108 from generating a photocurrent to cause leakage.

In addition, the pixel structure 100A depicted in FIG. 1 can be completed through the manufacturing process illustrated in FIGS. 2A to 2K, wherein the 2A to 2K drawings illustrate the pixel structure 100A of FIG. 1 in the production process. A cross-sectional view of the different stages. The flow of the method of fabricating the pixel structure will be described below.

In FIG. 2A, the gate 104 is formed on the substrate 102. In this step, a metal layer (not shown) may be formed on the substrate 102, and then the metal layer is patterned to form the gate 104.

In FIG. 2B, the first insulating layer 106, the semiconductor layer 107 and the second insulating layer 114 are sequentially formed, wherein the first insulating layer 106 is formed on the substrate 102 and the gate 104, and the semiconductor layer 107 is formed on the first insulating layer. On the 106, a second insulating layer 114 is formed on the semiconductor layer 107. After the first insulating layer 106, the semiconductor layer 107 and the second insulating layer 114 are sequentially formed, the photoresist layer 113 is further formed on the second insulating layer 114, wherein the photoresist layer 113 is exemplified by a positive photoresist.

In FIG. 2C, the photoresist layer 113 is exposed using a half-step mask 115. After the exposure is completed, the photoresist layer 113 is further subjected to a development process. Since the exposure process to the photoresist layer 113 is performed through the half-step mask 115, the photoresist layer 113a on the second insulating layer 114a has two thicknesses (as shown in FIG. 2D).

In FIG. 2D, a first etching process is performed with the photoresist layer 113a as a mask to pattern the semiconductor layer 107 and the second insulating layer 114b, wherein the semiconductor layer 107 forms a channel layer 108 after patterning, and has a source. The connecting portion 108s and the drain connecting portion 108d, wherein the second insulating layer 114 forms the second insulating layer 114a after patterning. The source connection portion 108s and the drain connection portion 108d are opposite end portions of the channel layer 108, respectively, for connecting the source and the drain formed in the subsequent process (such as the source 110 and the drain 112 of FIG. 1). ).

In FIG. 2E, the thinner portion of the photoresist layer 113a is removed to form the photoresist layer 113b to expose the partially patterned second insulating layer 114a, wherein the step of removing the thinner portion of the photoresist layer 113a includes The thickness of the photoresist layer 113a is thinned, for example, by an ashing process. Since the photoresist layer 113a on the second insulating layer 114a has two thicknesses, the thinner portion of the photoresist layer 113a is removed first, and the thicker portion of the photoresist layer 113a can be retained after thinning. On the second insulating layer 114a.

Referring to FIGS. 2E to 2F, a second etching process is performed through the photoresist layer 113b (see FIG. 2E) remaining on the second insulating layer 114a to remove the partially patterned second insulating layer 114a. And exposing a portion of the channel layer 108. Next, after removing the partially patterned second insulating layer 114a, the second insulating layer 114b is formed, and the photoresist layer 113b is removed. In addition, the vertical projection of the patterned second insulating layer 114b to the channel layer 108 falls within the drain connection portion 108d. That is, the vertical projection of the patterned second insulating layer 114b to the channel layer 108 falls on the pre- The range of the drain is formed such that the second insulating layer 114b can be located between the gate 104 and the drain formed in the subsequent process. However, in other embodiments, the vertical projection of the patterned second insulating layer 114b to the channel layer 108 may fall within the source connection portion 108s, that is, fall within a range in which the source is expected to be formed, so that the second insulation Layer 114b can be between gate 104 and the source formed in subsequent processes.

In FIG. 2G, a metal layer (not shown) is formed on the first insulating layer 106, the channel layer 108, and the second insulating layer 114b, and then the metal layer is patterned into the source 110 and the drain 112. The source 110 and the drain 112 are electrically connected to the channel layer 108, wherein the source 110 is located on the source connection portion 108s, the drain 112 is located on the gate connection portion 108d, and the second insulation layer 114b is located at the gate 112 and the gate. Between poles 104.

In FIG. 2H, a first passivation protective layer 116 and a passivation layer 118 are formed over the first insulating layer 106, the channel layer 108, the second insulating layer 114b, the source 110 and the drain 112, wherein the passivation layer 118 is located first. The upper surface of the protective layer 116 is passivated and covers the first passivation protective layer 116. Next, a via hole 120 is formed in the passivation layer 118, and a portion of the first passivation protective layer 116 is exposed.

In FIG. 2I, the common electrode 122 is formed on the passivation layer 118. The material of the common electrode 122 includes a transparent metal oxide such as Indium Tin Oxide (ITO).

In FIG. 2J, a second passivation protection layer 124 is formed on the passivation layer 118, wherein the common electrode 122 is located between the second passivation protection layer 124 and the passivation layer 118. Then, a portion of the first passivation protective layer 116 and a portion of the second passivation protective layer 124 are removed, such that the via 120 extends through at least the first passivation protective layer 116 and the passivation layer. 118 to expose a portion of the drain 112.

In the second embodiment, the pixel electrode 126 is formed on the passivation layer 118, the common electrode 122 and the second passivation protection layer 124. The pixel electrode 126 is electrically connected to the drain electrode 112 through the via 120. In addition, as previously described, the vertical projections of the pixel electrode 126, the drain 112, the passivation layer 118, and the gate 104 on the substrate 102 at least partially overlap. When the pixel electrode 126 is formed, the pixel structure 100A as shown in Fig. 1 can be obtained.

In summary, by using a half-step mask process, the channel layer 108 and the second insulating layer 114b can be formed in the same mask process without increasing the number of mask processes. However, in other embodiments, the channel layer 108 and the second insulating layer 114b may also be formed through two mask processes, respectively.

In addition, the insulating layer formed may have a plurality of thicknesses due to the half-step mask process. In some embodiments, the formed first insulating layer can be patterned through a half-step mask process to have at least two thicknesses such that the vertical distance between the source and the gate and the drain and gate are The vertical distance between the poles is different.

For example, please refer to FIG. 3, wherein FIG. 3 is a cross-sectional view showing the pixel structure 100B of the second embodiment of the present invention. In order not to make the drawing too complicated, the first passivation protective layer, the passivation layer, the common electrode, the second passivation protective layer and the pixel electrode are not shown in FIG. 3 . However, the first embodiment can be configured with reference to the first embodiment. A passivation protective layer, a passivation layer, a common electrode, a second passivation protective layer, and a pixel electrode.

The difference between this embodiment and the first embodiment is that the first insulating layer 106 of the present embodiment has at least two thicknesses such that the source 110 and The vertical distance between the gates 104 is different from the vertical distance between the gates 112 and the gates 104. Specifically, the vertical distance between the source 110 and the gate 104 that is vertically projected in the channel layer 108 and the vertical distance between the drain 112 and the gate 104 that fall perpendicularly within the channel layer 108 are different.

In other words, through the half-step mask process, the thickness T1 of the first insulating layer 106 between the gate 104 and the source 110 may be smaller than the thickness T2 of the first insulating layer 106 between the gate 104 and the drain 112. Further, the maximum vertical distance between the source 110 and the gate 104 is less than the maximum vertical distance between the drain 112 and the gate 104, wherein the maximum vertical distance between the source 110 and the gate 104 is the source 110. The largest of the vertical distances between the surface of the gate 104 and the surface of the gate 104 facing the source 110, and the maximum vertical distance between the drain 112 and the gate 104 is the surface of the drain 112 facing the gate 104. The largest of the vertical distances from the surface of the gate 104 toward the drain 112. Moreover, the maximum vertical distance between source 110 and gate 104 and the maximum vertical distance between drain 112 and gate 104 are between about 300 angstroms and about 10,000 angstroms.

In this configuration, a first capacitor is formed between the source 110 and the gate 104, and a second capacitor is formed between the gate 112 and the gate 104. The first capacitor is, for example, a gate/source capacitor (CGS). The second capacitor is, for example, a gate/drain capacitance (CGD), and the second vertical capacitance can be reduced by the maximum vertical distance between the source 110 and the gate 104 being less than the maximum vertical distance between the drain 112 and the gate 104. The first capacitance can be made larger than the second capacitance. For example, the difference between the first capacitance and the second capacitance is about 10 pF to 100 pF. As described above, by reducing the second capacitance, the feedthrough voltage and the gate load can be reduced.

That is, in the pixel structure 100B of the present embodiment, the province The second insulating layer in the first embodiment is omitted, and the thin film transistor formed by the substrate 102, the gate 104, the first insulating layer 106, the channel layer 108, the source 110 and the drain 112 is permeable to have two thicknesses. The first insulating layer 106 achieves the effect of reducing the gate/drain capacitance.

In addition, the pixel structure 100B of the present embodiment is an example in which the thickness of the first insulating layer 106 between the gate 104 and the source 110 is smaller than the thickness of the first insulating layer 106 between the gate 104 and the drain 112. In other embodiments, the thickness of the first insulating layer 106 between the gate 104 and the drain 112 may be smaller than the thickness of the first insulating layer 106 between the gate 104 and the source 110, such that the source 110 and The maximum vertical distance between the gates 104 will be greater than the maximum vertical distance between the drains 112 and the gates 104.

Fig. 4 is a cross-sectional view showing a pixel structure 100C according to a third embodiment of the present invention. In order not to make the drawing too complicated, the first passivation protective layer, the passivation layer, the common electrode, the second passivation protective layer and the pixel electrode are not shown in FIG. 4 . However, the first embodiment can be configured with reference to the first embodiment. A passivation protective layer, a passivation layer, a common electrode, a second passivation protective layer, and a pixel electrode.

Referring to FIG. 4 , the difference between the present embodiment and the first embodiment is that the second insulating layer 114 b of the present embodiment is disposed on the surface of the first insulating layer 106 facing the drain 112 and the channel layer 108 , and the second insulating layer The vertical projection of layer 114b to channel layer 108, for example, falls within the vertical projection of drain 112 to channel layer 108. Specifically, the second insulating layer 114b is disposed between the channel layer 108 and the first insulating layer 106. In FIG. 4, the first distance D1 is the maximum vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114, and second Distance D2 is the source 110 faces the surface of the gate 104 and the channel layer 108 and the maximum vertical distance between the gate 104 and the surface of the channel layer 108 and the source 110, wherein the first distance D1 is greater than the second distance D2. In this configuration, since the first distance D1 is increased through the arrangement of the second insulating layer 114b, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, thereby reducing the feedthrough voltage and the gate load. The display panel to which the pixel structure 100C is applied can have better quality.

In addition, the present embodiment is exemplified by a vertical projection of the second insulating layer 114b to the channel layer 108 falling within the vertical projection of the drain 112 to the channel layer 108. However, in other embodiments, the second insulating layer 114b to the channel The vertical projection of layer 108 may also fall within the vertical projection of source 110 to channel layer 108 to reduce parasitic capacitance generated between source 110 and gate 104.

Fig. 5 is a cross-sectional view showing a pixel structure 100D according to a fourth embodiment of the present invention. In order not to make the drawing too complicated, the first passivation protective layer, the passivation layer, the common electrode, the second passivation protective layer and the pixel electrode are not shown in FIG. 5 . However, the first embodiment can be configured with reference to the first embodiment. A passivation protective layer, a passivation layer, a common electrode, a second passivation protective layer, and a pixel electrode.

Referring to FIG. 5 , the difference between the present embodiment and the first embodiment is that the second insulating layer 114 b of the present embodiment is disposed on the surface of the first insulating layer 106 facing away from the drain 112 and the channel layer 108 , and the second The vertical projection of insulating layer 114b to channel layer 108 falls within the vertical projection of drain 112 to channel layer 108. Specifically, the second insulating layer 114b is disposed between the first insulating layer 106 and the gate 104, and the first insulating layer 106 covers the second insulating layer 114b. In FIG. 5, the first distance D1 is a table in which the drain 112 faces the surface of the gate 104 and the second insulating layer 114b and the gate 104 faces the drain 112 and the second insulating layer 114b. The maximum vertical distance between the faces, the second distance D2 being the maximum vertical distance between the source 110 toward the surface of the gate 104 and the channel layer 108 and the surface of the gate 104 toward the channel layer 108 and the source 110, wherein The distance D1 is greater than the second distance D2. In this configuration, since the first distance D1 is increased through the arrangement of the second insulating layer 114b, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, thereby reducing the feedthrough voltage and the gate load. The display panel to which the pixel structure 100D is applied can have better quality.

In addition, the present embodiment is exemplified by a vertical projection of the second insulating layer 114b to the channel layer 108 falling within the vertical projection of the drain 112 to the channel layer 108. However, in other embodiments, the second insulating layer 114b to the channel The vertical projection of layer 108 may also fall within the vertical projection of source 110 to channel layer 108 to reduce parasitic capacitance generated between source 110 and gate 104.

Fig. 6 is a cross-sectional view showing a pixel structure 100E according to a fifth embodiment of the present invention. The difference between this embodiment and the first embodiment is that the pixel structure 100E of the present embodiment further includes a gate on array (GOA) unit 130. The gate driving circuit unit 130 includes a first conductive unit 132 and a second conductive unit 134. The first conductive unit 132 is disposed on the substrate 102 and electrically connected to the gate 104 . The second conductive unit 134 is disposed on the first conductive unit 132 , wherein the first insulating layer 106 , the semiconductor layer 107 , and the second insulating layer 114 c are located between the first conductive unit 132 and the second conductive unit 134 .

Since the first insulating layer 106 and the second insulating layer 114c can increase the distance between the first conductive unit 132 and the second conductive unit 134 of the gate driving circuit unit 130, the first conductive unit 132 and the second conductive unit can be lowered. Parasitic capacitance between 134.

On the other hand, through the second insulating layer 114b, the first distance D1 between the gate 104 and the drain 112 is still greater than the second distance D2 between the gate 104 and the source 110. In addition, in the pixel structure 100E of the present embodiment, the second insulating layer 114b between the drain 112 and the channel layer 108 and the second insulating layer 114c between the first conductive unit 132 and the second conductive unit 134 are permeable. The same process is completed, please see the instructions below.

7A to 7G are cross-sectional views showing the pixel structure 100E of Fig. 6 at different stages of the fabrication process. The difference between the embodiment and the manufacturing process cross-sectional views shown in FIGS. 2A to 2K is that the method of fabricating the pixel structure 100E further includes forming the gate driving circuit unit 130 (see FIG. 6).

In FIG. 7A, the gate 104 and the first conductive unit 132 are formed on the substrate 102. In this step, a metal layer (not shown) may be formed on the substrate 102, and then the metal layer is patterned into the gate 104 and the first conductive unit 132. That is, the gate 104 and the first conductive unit 132 can be formed by patterning the same metal layer through the same mask process.

In FIG. 7B, the first insulating layer 106, the semiconductor layer 107 and the second insulating layer 114 are sequentially formed, wherein the first insulating layer 106 is formed on the substrate 102, the gate 104 and the first conductive unit 132, and the semiconductor layer 107 The second insulating layer 114 is formed on the first insulating layer 106, and the second insulating layer 114 is formed on the semiconductor layer 107. After the first insulating layer 106, the semiconductor layer 107, and the second insulating layer 114 are sequentially formed, the photoresist layer 113 is further formed on the second insulating layer 114.

In FIG. 7C, as described in FIG. 2C, the patterned semiconductor layer 107 and the patterned second insulating layer 114 can be completed by a half-step mask process. In addition, since the photoresist layer 113 is exemplified as a positive photoresist, the half-step mask 115 is shielded. The light above the conductive unit 132 is such that the photoresist layer 113 above the first conductive unit 132 can remain on the second insulating layer 114 above the first conductive unit 132 after development. At this time, a photoresist layer 113a1 above the gate 104 and a photoresist layer 113a2 above the first conductive unit 132 are formed (as shown in FIG. 7D).

In FIG. 7D, a first etching process is performed to pattern the semiconductor layer 107 and the second insulating layer 114, wherein the semiconductor layer 107 forms a channel layer 108 above the gate 104 after patterning and is located above the first conductive unit 132. The auxiliary layer 109, the second insulating layer 114 forms a second insulating layer 114a1 above the gate 104 and a second insulating layer 114a2 above the first conductive unit 132 after patterning, and the auxiliary above the first conductive unit 132 Layer 109 is still between first insulating layer 106 and second insulating layer 114a2. In addition, since the exposure process performed on the photoresist layer in FIG. 7C is performed through the half-step mask 115, the photoresist layer 113a1 on the second insulating layer 114a1 above the channel layer 108 has two thicknesses, wherein One of the larger thicknesses of the photoresist layer 113a1 on the second insulating layer 114a1 and the second insulating layer 114a2 over the first conductive unit 132 have the same thickness.

In FIG. 7E, the photoresist layer 113a1 and the photoresist layer 113a2 are thinned to remove the thinner portion of the photoresist layer 113a1 to form the photoresist layer 113b1 on the second insulating layer 114a1 and the light on the auxiliary layer 109. The resist layer 113b2 is exposed to a portion of the second insulating layer 114a1. On the other hand, referring to FIGS. 7D and 7E simultaneously, the thickness of the photoresist layer 113b2 above the first conductive unit 132 is smaller than the thickness of the photoresist layer 113a2.

In FIG. 7F, a second etching process is performed through the remaining photoresist layer 113b1 (see FIG. 7E) to remove the second portion of the portion above the channel layer 108. The edge layer 114a1 exposes a portion of the channel layer 108. Next, after removing a portion of the second insulating layer 114a1 to form the second insulating layer 114b, the photoresist layer 113b1 and the photoresist layer 113b2 are removed.

In FIG. 7G, a metal layer (not shown) is formed on the first insulating layer 106, the channel layer 108, the second insulating layer 114b above the channel layer 108, and the second insulating layer 114a2 above the first conductive unit 132, and then The metal layer is patterned into a source 110, a drain 112, and a second conductive unit 134, wherein the second conductive unit 134, the source 110, and the drain 112 are formed through the same mask process.

The formed source 110 and drain 112 are connected to the channel layer 108, and the second insulating layer 114b is located between the drain 112 and the gate 104. On the other hand, in the gate driving circuit unit 130, the second conductive unit 134 is located above the first conductive unit 132, and the second insulating layer 114a2 is located at least between the first conductive unit 132 and the second conductive unit 134.

After the second conductive unit 134 is formed, the step of forming the gate driving circuit unit 130 is also completed. Then, the subsequent processes can be completed as shown in the processes of FIGS. 2H to 2K. That is, the first passivation protective layer 116, the passivation layer 118, the via 120, the common electrode 122, the second passivation protective layer 124, and the pixel electrode 126 depicted in FIG. 6 can be drawn through the 2H to 2K drawings. The flow is formed to complete the pixel structure 100E shown in FIG.

Fig. 8 is a cross-sectional view showing a pixel structure 100F according to a sixth embodiment of the present invention. The difference between this embodiment and the first embodiment is that the pixel structure 100F of the present embodiment includes a top gate thin film transistor structure, wherein the first distance D1 between the gate 104 and the drain 112 is still greater than A second distance D2 between the gate 104 and the source 110.

In the present embodiment, the channel layer 108, the source 110, the drain 112 and the second insulating layer 114b are located between the substrate 102 and the first insulating layer 106, and the gate 104 is disposed on the first insulating layer 106 facing away from the substrate 102. The surface. In other words, the channel layer 108, the source 110, the drain 112, and the second insulating layer 114b on the substrate 102 are covered by the first insulating layer 106. The second insulating layer 114b is located above the drain 112 and between the channel layer 108 and the first insulating layer 106, and the vertical projection of the second insulating layer 114b on the substrate 102 is exemplified by the vertical projection of the drain 112 on the substrate 102. in.

In Fig. 8, the first distance D1 is the maximum vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114b, and second The distance D2 is the maximum vertical distance between the source 110 toward the surface of the gate 104 and the channel layer 108 and the gate 104 toward the surface of the channel layer 108 and the source 110, wherein the first distance D1 is greater than the second distance D2. By the arrangement of the second insulating layer 114b, since the first distance D1 can be greater than the second distance D2, the parasitic capacitance generated between the drain 112 and the gate 104 is reduced, and the feedthrough voltage and the gate load are also reduced. . Therefore, the display panel to which the pixel structure 100F is applied can also have better quality.

In addition to this, the pixel structure 100F further includes a masking layer 140. The shielding layer 140 is located between the substrate 102 and the channel layer 108, wherein a vertical projection of the channel layer 108 to the shielding layer 140 falls within the shielding layer 140. In other words, the vertical projection of channel layer 108 to masking layer 140 falls within the vertical projection of masking layer 140 to substrate 102. In this configuration, since the shielding layer 140 can shield the light entering the pixel structure 100F from the side of the substrate 102 facing away from the channel layer 108, the channel layer 108 can be prevented from generating photocurrent due to the irradiation, thereby preventing leakage. Masking layer 140 The material is exemplified by a light-shielding material such as a metal or a black resin.

In addition, the pixel structure 100F depicted in FIG. 8 is such that the second insulating layer 114b is disposed between the channel layer 108 and the first insulating layer 106, and the vertical projection of the second insulating layer 114b on the substrate 102. It is an example of falling in the vertical projection of the drain 112 on the substrate 102. However, in other embodiments, the second insulating layer 114b may also be disposed between the channel layer 108 and the drain 112, and the vertical projection of the second insulating layer 114 on the substrate 102 falls on the source 110 on the substrate 102. In the vertical projection, at least the distance between the gate 104 and the source 110 is increased, thereby reducing the parasitic capacitance between the gate 104 and the source 110. In addition, in other embodiments, the two second insulating layers 114b may also be disposed between the channel layer 108 and the drain 112 and between the channel layer 108 and the first insulating layer 106, further increasing the gate 104 and The distance of the source 110.

The pixel structure 100F depicted in FIG. 8 can be completed through the manufacturing process illustrated in FIG. 9A to FIG. 9D, wherein the 9A to 9D drawings illustrate the difference in the production process of the pixel structure 100F of FIG. 8 . Sectional view of the stage. Hereinafter, each flow of the method of manufacturing the pixel structure 100F of Fig. 8 will be described.

In FIG. 9A, the shielding layer 140 is formed on the substrate 102. Then, a metal layer (not shown) is formed on the substrate 102, and the metal layer is patterned into the source 110 and the drain 112.

In FIG. 9B, a semiconductor layer (not shown) is formed on the shielding layer 140, the source 110 and the drain 112, and the semiconductor layer is patterned into a channel layer 108, wherein the formed channel layer 108 is electrically connected to the source 110. With the drain 112, the vertical projection of the channel layer 108 to the masking layer 140 falls within the masking layer 140.

In FIG. 9C, the second insulating layer 114b is formed on the channel layer 108. The vertical projection of the second insulating layer 114b to the channel layer 108 is exemplified by a vertical projection of the drain 112 to the channel layer 108. That is, a portion of the channel layer 108 will be located between the second insulating layer 114b and a portion of the drain 112.

In FIG. 9D, the first insulating layer 106 is formed and covers the source 110, the drain 112, the channel layer 108 and the second insulating layer 114b, and then the gate 104 is formed on the first insulating layer 106. Since the vertical projection of the second insulating layer 114b formed in FIG. 9C falls within the vertical projection of the drain 112 to the channel layer 108, the vertical distance between the gate 104 and the drain 112 formed is greater than the source and source. The vertical distance of the pole 110 is used to reduce the parasitic capacitance between the gate 104 and the drain 112.

In summary, the pixel structure of the present invention reduces the parasitic capacitance generated between one of the source and the drain and the gate through the arrangement of the second insulating layer, thereby reducing the feedthrough voltage and the gate load. In order to make the display panel of the pixel structure have better quality and improve the problem of uneven brightness and darkness. On the other hand, the gate of the pixel structure can be used as a mask to inject light into the pixel structure to prevent leakage of the channel layer in the pixel structure due to the generation of photocurrent.

While the invention has been described above in terms of various embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100A‧‧‧ pixel structure

102‧‧‧Substrate

104‧‧‧ gate

106‧‧‧First insulation

108‧‧‧Channel layer

110‧‧‧ source

112‧‧‧汲polar

116‧‧‧First passivation protective layer

118‧‧‧ Passivation layer

120‧‧‧through hole

122‧‧‧Common electrode

124‧‧‧Second passivation protective layer

126‧‧‧ pixel electrodes

D1‧‧‧First distance

114b‧‧‧Second insulation

D2‧‧‧Second distance

Claims (20)

A pixel structure comprising: a substrate; a gate disposed on the substrate; a channel layer disposed on the substrate; a first insulating layer disposed between the gate and the channel layer; a pole electrically connected to the channel layer; a drain electrically connected to the channel layer; and a second insulating layer disposed integrally with the source projecting vertically within the channel layer And a vertical distance between a portion of the one of the drain and the gate, wherein a vertical distance between a portion of the source and the drain of the drain and the gate is perpendicular to a first distance, and a vertical distance between the source and a portion of the other of the drains in the channel layer and the gate is a second distance, wherein the first distance is at least The thickness of the second insulating layer is included, and the first distance is greater than the second distance. The pixel structure of claim 1, wherein the vertical projection of the channel layer to the gate falls within the gate. The pixel structure of claim 1, wherein the first insulating layer covers the surface of the gate facing away from the substrate, and the second insulating layer is disposed on the source and the vertical projection falling in the channel layer One of the bungee is between the one of the channel layers. The pixel structure of claim 3, wherein the second insulating layer is disposed between a portion of the drain and a portion of the channel layer, and the opposite surfaces of the second insulating layer are partially covered by the drain and the portion, respectively. The channel layer is completely covered. The pixel structure of claim 1, wherein the channel layer, the source, the drain and the second insulating layer are located between the substrate and the first insulating layer, and the gate is disposed on the first An insulating layer faces away from the surface of the substrate. The pixel structure of claim 5, further comprising a shielding layer between the substrate and the channel layer, wherein a vertical projection of the channel layer to the shielding layer falls within the shielding layer. The pixel structure of claim 1, wherein the second insulating layer is disposed on the surface of the first insulating layer facing the source and the drain and toward the channel layer, and the second The vertical projection of the entirety of the insulating layer to the channel layer falls within a vertical projection of one of the source and the drain to the channel layer. The pixel structure of claim 1, wherein the second insulating layer is disposed on a surface of the first insulating layer facing away from the source and the drain and facing away from the channel layer, and The entirety of the second insulating layer to the The vertical projection of the channel layer falls within a vertical projection of one of the source and the drain to the channel layer. The pixel structure of claim 1, wherein the second insulating layer has a thickness of 300 nanometers (nm) to 400 nanometers (nm), and the second insulating layer does not fall perpendicular to the channel. The source within the layer is in contact with the other of the drains. The pixel structure of claim 1 further includes a gate on array (GOA) unit, including: a first conductive unit disposed on the substrate and electrically connected to the gate And a second conductive unit disposed on the first conductive unit. The pixel structure of claim 1, further comprising: a passivation layer on the first insulating layer, the channel region, the second insulating layer, the source and the drain, wherein the passivation layer Having a through hole to expose at least a portion of the drain; and a pixel electrode on the passivation layer and electrically connected to the drain through the via, wherein the pixel electrode, the drain, and the passivation layer At least partially overlapping the vertical projection of the gate to the substrate. A method for fabricating a pixel structure, comprising: forming a gate on a substrate; Forming a first insulating layer on the substrate and the gate; forming a semiconductor layer on the first insulating layer, and patterning the semiconductor layer into a channel layer, wherein the channel layer has a source connection portion and a drain a connecting portion; forming a second insulating layer, and patterning the second insulating layer such that a vertical projection of the patterned second insulating layer to the channel layer falls on the source connection portion and the drain electrode And forming a metal layer on the first insulating layer, the channel layer and the second insulating layer, and patterning the metal layer into a source and a drain, wherein the source The pole is electrically connected to the source connecting portion, the drain is electrically connected to the drain connecting portion, and the second insulating layer is entirely located between the source and the drain and the gate . The method for fabricating a pixel structure according to claim 12, wherein the patterning the semiconductor layer and patterning the second insulating layer are performed through a same half-tone mask process, and patterning The step of patterning the second insulating layer comprises: forming the second insulating layer on the semiconductor layer, and forming a photoresist layer on the second insulating layer; exposing the light through a half-step mask a resist layer, and performing a developing process on the photoresist layer; performing a first etching process to pattern the semiconductor layer and the second insulating layer, and removing a portion of the photoresist layer to expose the patterned portion Two insulating layers; A second etching process is performed to remove the partially patterned second insulating layer and expose a portion of the via layer. The method for fabricating the pixel structure of claim 12, further comprising: forming a passivation layer on the first insulating layer, the channel layer, the second insulating layer, the source and the drain; forming a via hole is formed in the passivation layer to expose at least a portion of the drain electrode; and a pixel electrode is formed on the passivation layer, and the pixel electrode is electrically connected to the drain electrode through the through hole, wherein the drawing The pixel electrode, the drain, the passivation layer and the vertical projection of the gate on the substrate at least partially overlap. The method for fabricating the pixel structure of claim 12, further comprising forming a gate on array (GOA) unit, wherein the step of forming the gate driving circuit unit comprises: forming a first conductive unit On the substrate, wherein the first conductive unit and the gate are formed through the same mask process; and a second conductive unit is formed on the second insulating layer, wherein the second conductive unit, the source and the gate It is formed through the same mask process. A method for fabricating a pixel structure includes: forming a metal layer on a substrate, and patterning the metal layer into a source and a drain; Forming a semiconductor layer on the source and the drain, and patterning the semiconductor layer into a channel layer; forming a first insulating layer, wherein a vertical projection of the first insulating layer to the channel layer and the source are Forming a second insulating layer on the source, the drain, the channel layer and the first insulating layer; and forming a gate The second insulating layer is disposed on the second insulating layer, and the entirety of the first insulating layer is located between a portion of the source and the drain and the gate. The method for fabricating the pixel structure of claim 16 further includes: forming a shielding layer on the substrate before the step of forming the metal layer on the substrate, wherein the channel layer is perpendicular to the shielding layer The projection falls within the obscuring layer. A thin film transistor comprising: a substrate; a gate disposed on the substrate; a channel layer disposed on the substrate; a first insulating layer disposed between the gate and the channel layer; and a The first electrode and the second electrode are electrically connected to the channel layer, wherein a first capacitor is formed between the first electrode and the gate, and a second capacitor is formed between the second electrode and the gate. A capacitance is greater than the second capacitance. The thin film transistor of claim 18, wherein the difference between the first capacitance and the second capacitance is about 10 pF to 100 pF. A thin film transistor comprising: a substrate; a gate disposed on the substrate; a channel layer disposed on the substrate; a first insulating layer disposed between the gate and the channel layer; and a The first electrode and the second electrode are electrically connected to the channel layer, wherein a maximum vertical distance between the first electrode and the gate and a maximum vertical distance between the second electrode and the gate are about 300 angstroms to about 10,000 angstroms.