TWI805346B - Array substrate and manufacturing method thereof - Google Patents

Abstract

An array substrate includes a substrate, a dielectric layer, an active device, fanout wiring lines and at least one dummy wiring line. The substrate has an active area and a fanout area. The dielectric layer is over the substrate. The fanout wiring lines are electrically connected with the active device. A first gap is between two adjacent fanout wiring lines, and a first lightly doped region is at the dielectric layer corresponding to a normal rejection of the first gap. The at least one dummy wiring line is at the outside of the fanout wiring lines.

Description

Array substrate and manufacturing method thereof

Some embodiments of the present disclosure relate to an array substrate and a manufacturing method thereof.

The array substrate can include a display area and a non-display area. The display area may have pixels arranged in an array to display images. The non-display area may have drive circuits to drive elements in the display area. The driving circuit can be connected to the elements in the display area through fan-out wires around the periphery of the display area. The wire spacing between fanout wires affects the number of fanout wires per unit area. When the distance between the fan-out wires is narrower, the number of fan-out wires per unit area can be increased.

Some embodiments of the present disclosure provide an array substrate, including a substrate, a dielectric layer, an active device, a plurality of fan-out wires and at least one dummy wire. The substrate has a display area and a fan-out area. The dielectric layer is on the substrate. The active element is on the display area of the substrate. A plurality of fan-out wires are electrically connected to the active element, there is a first gap between two adjacent fan-out wires, and the area of the dielectric layer corresponding to the vertical projection of the first gap includes a first lightly doped region. At least one dummy wire is located outside the fan-out wire.

In some embodiments, there is a second gap between one of the dummy wire and the fan-out wire, and a region of the dielectric layer corresponding to the vertical projection of the second gap includes a second lightly doped region.

In some embodiments, the dielectric layer further includes a heavily doped region, the heavily doped region and the second lightly doped region are located on opposite sides of the dummy wire, and the ion concentration of the heavily doped region is higher than that of the second lightly doped region. The concentration of ions in the impurity region.

In some embodiments, the dielectric layer corresponds to a region between the heavily doped region and the vertical projection of the dummy wire includes a third lightly doped region, and the ion concentration of the heavily doped region is higher than that of the third lightly doped region ion concentration.

In some embodiments, the ion concentration of the first lightly doped region is substantially equal to the ion concentration of the third lightly doped region.

In some embodiments, the array substrate further includes a plurality of semiconductor layers in the dielectric layer and under the fan-out wires.

In some embodiments, the plurality of edges of the semiconductor layer have a plurality of fourth lightly doped regions.

In some embodiments, the semiconductor layers are electrically connected to the fan-out wires respectively.

In some embodiments, the dummy wire is structurally separated from the active device.

In some embodiments, in the first lightly doped region, the concentration along the surface of the dielectric layer is substantially constant.

In some embodiments, the array substrate further includes a plurality of shielding metals between the dielectric layer and the substrate and under the fan-out wires.

In some embodiments, the shielding metals are respectively electrically connected to the fan-out wires.

In some embodiments, the width of the dummy wire is smaller than the width of the fan-out wire.

Some embodiments of the present disclosure provide a method of manufacturing an array substrate, including forming a dielectric layer on the substrate. A metal layer is formed on the dielectric layer. A photoresist layer is formed on the metal layer. Exposing the photoresist layer through a halftone mask to form a halftone photoresist layer on the metal layer, the halftone photoresist layer has a first portion with a higher height and a second portion with a lower height on the fan-out area of the substrate , and the halftone photoresist layer exposes a part of the metal layer. Performing a first wet etching to remove part of the metal layer through the half-tone photoresist layer to form a metal pattern on the fan-out area of the substrate and expose the first area of the dielectric layer. A heavily doped implant is performed to form a heavily doped region in the first region of the dielectric layer. A second portion of the halftone photoresist layer is removed to expose portions of the metal pattern. performing a second wet etch to remove portions of the metal pattern through the first portion of the halftone photoresist layer and to form a wire layer comprising a plurality of fan-out wires with exposed dielectric layers therebetween of the second area. A lightly doped implant is performed to form lightly doped regions in the first region and the second region of the dielectric layer.

In some embodiments of the present disclosure, when forming the wire layer in the display area, a half-tone mask is also used to form the fan-out wires in the fan-out area of the array substrate. When using the process of some embodiments of the present disclosure, the pitch between adjacent fan-out wires in the fan-out region can be shortened, for example, narrower than the exposure resolution.

In order to enable those who are familiar with the general skills in the technical field to which this disclosure belongs to have a better understanding of this disclosure, the preferred embodiments of this disclosure are listed below, together with the accompanying drawings, to describe in detail the composition and effects of this disclosure .

In some embodiments of the present disclosure, when forming the wire layer in the display area, a half-tone mask is also used to form the fan-out wires in the fan-out area of the array substrate. When using the process of some embodiments of the present disclosure, the pitch between adjacent fan-out wires in the fan-out region can be shortened, for example, narrower than the exposure resolution, so that the unit area can be increased. The number of fanout wires for .

FIG. 1A shows a top view of an array substrate 100 according to some embodiments of the present disclosure. FIG. 1B shows an enlarged top view of the region R1 in FIG. 1A . Figure 1C shows a cross-sectional view along the line A-B-C-D of Figure 1B. FIG. 1D shows an enlarged top view of the region R2 in FIG. 1A . Referring to FIGS. 1A to 1D , the array substrate 100 includes a substrate 110 , which is a transparent substrate such as a glass plate, and the substrate 110 has a display area AA and a fan-out area FO. The fan-out area FO may be located in the non-display area of the array substrate 100 and formed on the periphery of the display area AA, and may be used to connect wires in the display area AA to the driving circuit. The array substrate 100 can be used in any suitable electronic device, such as mobile phone, tablet, notebook computer and so on.

Referring to FIG. 1B to FIG. 1C , in the display area AA, the substrate 110 of the array substrate 100 may include a plurality of transistors TR, a plurality of scan lines SL and a plurality of data lines DL. The transistor TR includes a source SO, a drain DR, a gate GA and a channel layer CH. The source SO and the drain DR of the transistor TR are connected to the channel layer CH, and the gate GA of the transistor TR is located above the channel layer CH. The transistor TR is connected to the scan line SL and the data line DL, the scan line SL can be connected to the gate GA of the transistor TR, and the data line DL can be connected to the source SO of the transistor TR. Scanning line SL and data line DL Can be arranged in different directions. In some embodiments, the scan lines SL are arranged along the horizontal direction, while the data lines DL are arranged along the vertical direction, and vice versa. The alternately arranged scan lines SL and data lines DL can define the sub-pixel area SP of the display area AA, as shown in FIG. 1B . There may be an upper pixel electrode 186 in the sub-pixel region SP, and the upper pixel electrode 186 may be connected to the drain DR of the transistor TR.

The array substrate 100 may further include a buffer layer 120 , a shielding metal 130 , a dielectric layer 140 , an interlayer dielectric layer 160 , a lower pixel electrode 182 , and an insulating layer 184 , and the positions of the above elements will be further described later. It should be noted that, in order to simplify the drawing, FIG. 1B only shows the substrate 110 , the shielding metal 130 , the transistor TR, the scan line SL, the data line DL and the upper pixel electrode 186 . FIG. 1B and FIG. 1C show that the upper pixel electrode 186 can be connected to the drain DR of the transistor TR through the via hole V1.

Referring to FIG. 1D , the fan-out wire 154 and the dummy wire 156 are on the fan-out area FO. The fan-out wire 154 can be electrically connected to the transistor TR through a data line DL or a scan line SL, for example. The dummy wire 156 is located outside the fan-out wire 154 and is structurally separated from the transistor TR. That is, the dummy wire 156 is physically separated from the transistor TR, so the dummy wire 156 is not electrically connected to the transistor TR. In some embodiments, the fan-out wires 154 and the dummy wires 156 and the scan lines SL in the display area AA can be formed from the same conductive layer at the same time. Compared with the display area AA, there is no sub-pixel area above the fan-out area FO. In addition, compared with the adjacent scan lines SL in the display area AA, the distance between adjacent fan-out wires 154 in the fan-out area FO is narrower to accommodate more fan-out in the fan-out area FO per unit area. Wire 154. In some embodiments, the distance between adjacent fan-out wires 154 of the fan-out area FO is less than 2 microns.

2A to 15 illustrate cross-sectional views of the process of forming the array substrate 100 in some embodiments of the present disclosure. Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A and Figure 12A are along the lines of Figure 1D A cross-sectional view of the line E-E of the fan-out region FO. Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 12B, Figure 13, Figure 14 Figure 15 is a cross-sectional view along line A-B-C-D of display area AA in Figure 1B. Referring to FIG. 2A and FIG. 2B , a buffer layer 120 is formed on the substrate 110 . In the display area AA, the shielding metal 130 may be formed before the buffer layer 120 is formed. For example, a conductive layer (such as a metal layer) can be formed on the substrate 110 , and then the conductive layer can be patterned to form the shielding metal 130 . Next, a buffer layer 120 is formed to cover the shielding metal 130 . On the other hand, in the fan-out region FO, the shielding metal 130 may not be formed. Shading metal 130 can be used to block light.

Referring to FIG. 3A and FIG. 3B , a dielectric layer 140 is formed on the substrate 110 and the buffer layer 120 . In the display area AA, before the dielectric layer 140 is formed, the channel layer CH may be formed first. For example, a semiconductor layer can be formed on the buffer layer 120 first, and then the semiconductor layer can be patterned to form the channel layer CH. Next, a dielectric layer 140 is formed to cover the channel layer CH. In some embodiments, the channel layer CH may be polysilicon. On the other hand, in the fan-out area FO, the channel layer CH may not be formed. Referring to FIG. 4A and FIG. 4B , in the display area AA and the fan-out area FO, a metal layer 150 is formed on the dielectric layer 140 , and a photoresist layer PR is formed on the metal layer 150 . In some embodiments, the material of the metal layer 150 may include molybdenum or other suitable metal materials.

Referring to FIG. 5A and FIG. 5B , the photoresist layer PR in the fan-out area FO is exposed by the halftone mask HM to form the halftone photoresist layer PR1 on the metal layer 150 . The half-tone photoresist layer PR1 has a first portion P1 with a higher height and a second portion P2 with a lower height on the fan-out region FO of the substrate 110 , and the half-tone photoresist layer PR1 exposes a part of the metal layer 150 . Specifically, the halftone mask HM is made of a transparent substrate HM1 , an opaque pattern HM2 and a halftone film HM3 . When light hits the transparent substrate HM1 not covered by the opaque pattern HM2 and the halftone film HM3 , the underlying photoresist layer PR can be 100% exposed. When the light hits the transparent substrate HM1 covered by the half-tone film HM3, the exposure degree of the photoresist layer PR below is 20% to 50%. When light hits the transparent substrate HM1 covered by the opaque pattern HM2, the underlying photoresist layer PR will not be exposed. When the photoresist layer PR is 100% exposed, no photoresist layer PR will remain after developing the photoresist layer PR. When the exposure level of the photoresist layer PR is 20% to 50%, after developing the photoresist layer PR, a part of the photoresist layer PR remains and the thickness of the photoresist layer PR is reduced, such as the first part P1 of the photoresist layer PR. When the photoresist layer PR is not exposed, after the photoresist layer PR is developed, the photoresist layer PR is not removed by the developer but remains in place with the same height, such as the second portion P2 of the photoresist layer PR.

On the other hand, the photoresist layer PR in the display area AA is exposed by the binary mask BM to form the binary photoresist layer PR2 on the metal layer 150 , and the thickness of the binary photoresist layer PR2 is substantially the same. Specifically, the second portion P2 of the photoresist layer PR. The binary mask BM is made of a transparent substrate BM1 and an opaque pattern BM2. The transparent substrate BM1 and the opaque pattern BM2 are similar to the transparent substrate HM1 and the opaque pattern HM2. Therefore, the thickness of the developed binary photoresist layer PR2 is substantially consistent. It should be noted that, in FIG. 5A and FIG. 5B , the pattern sizes of the halftone mask HM and the binary mask BM are just examples and do not represent actual sizes. For example, the pattern sizes of the halftone mask HM and the binary mask BM are larger than those of the halftone photoresist layer PR1 and the binary photoresist layer PR2 respectively.

When using the halftone mask HM, the width of the formed second portion P2 of the halftone photoresist layer PR1 may be smaller than the exposure resolution. After the second portion P2 of the half-tone photoresist layer PR1 is removed in a subsequent process, the first portion P1 of the half-tone photoresist layer PR1 can be used to manufacture fan-out lines with a line width smaller than the exposure resolution.

Referring to FIG. 6A and FIG. 6B, a first wet etching is performed. In the fan-out area FO, a part of the metal layer 150 is removed by the half-tone photoresist layer PR1 to form a metal pattern on the fan-out area FO of the substrate 110 and expose the second layer of the dielectric layer 140 of the fan-out area FO. an area. Since the second portion P2 of the half-tone photoresist layer PR1 does not expose the dielectric layer 140 , the dielectric layer 140 under the second portion P2 of the half-tone photoresist layer PR1 will not be removed. On the other hand, in the display area AA, part of the metal layer 150 is removed by the binary photoresist layer PR2 to form a metal pattern on the display area AA of the substrate 110 and expose the dielectric layer 140 of the display area AA. first area. Specifically, the metal layer 150 in the display area AA can be patterned in subsequent processes to form gates (such as the gate GA in FIG. 9B ) and scan lines (such as the scan lines SL in FIG. 1B ).

Referring to FIG. 7A and FIG. 7B, a heavily doped implant is performed to form a heavily doped region P in the channel region CH. Specifically, the heavily doped region P can be implanted with different dopants according to the type of active device to be formed. For example, when an NMOS TFT is to be formed, N-type doping can be performed, and the concentration of the dopant, such as phosphorus, is about 1E19 atoms/cm3. When a PMOS TFT is to be formed, P-type doping may be performed, and the concentration of the dopant, such as boron, is about 1E19 atoms/cm3 to about 1E20 atoms/cm3.

In addition, when the heavily doped implant operation is performed, part of the dopant will also be doped into the exposed part of the dielectric layer 140 (and the buffer layer 120 ), so the heavily doped region P will also be formed in the sector. In the first area (ie, the area exposed by the metal pattern) of the dielectric layer 140 in the output area FO and the display area AA.

Referring to FIG. 8A and FIG. 8B , a part of the half-tone photoresist layer PR1 and the binary photoresist layer PR2 is removed by, for example, photoresist ashing. In the fan-out area FO, the second portion P2 of the halftone photoresist layer PR1 is removed to expose a portion of the metal pattern of the metal layer 150 . Specifically, during the ashing of the photoresist, the outermost first part P1 of the halftone photoresist layer PR1 is removed, so that the sidewall of the outermost first part P1 of the halftone photoresist layer PR1 shrinks inwardly, and The outermost peripheral portion of the metal pattern of the metal layer 150 is exposed. At the same time, the second portion P2 of the half-tone photoresist layer PR1 is also removed, so that the half-tone photoresist layer PR1 is only composed of the first portion P1. In some embodiments, the photoresist ashing also simultaneously reduces the thickness of the first portion P1 of the halftone photoresist layer PR1. On the other hand, in the display area AA, the binary photoresist layer PR2 is also partially removed from the sidewall, so that the sidewall of the binary photoresist layer PR2 shrinks inward, and part of the metal layer 150 is exposed.

Referring to FIG. 9A and FIG. 9B, a second wet etching is performed. In the fan-out area FO, a part of the metal pattern of the metal layer 150 is removed by the first part P1 of the halftone photoresist layer PR1, and a wire layer 152 is formed. The wire layer 152 includes a plurality of fan-out wires 154 and dummy wires. 156 . There is a second region of the dielectric layer 140 exposed between the fan-out wires 154 . Since the photoresist ashing can effectively remove the second part P2 of the halftone photoresist layer PR1, etching can be used to manufacture fan-out wires 154 with a pitch smaller than the exposure resolution through the remaining first part P1, and at the same time Active elements in the display area AA are formed. Since the second portion P2 of the half-tone photoresist layer PR1 is removed by wet etching, the distance between adjacent fan-out wires 154 may be smaller than the exposure resolution. Specifically, there is a first gap G1 between two adjacent fan-out wires 154 , and the area of the dielectric layer 140 corresponding to the vertical projection of the first gap G1 is the second area. The dummy wire 156 is located outside the fan-out wire 154, and there is a second gap G2 between the dummy wire 156 and one of the fan-out wires 154, and the area of the dielectric layer 140 corresponding to the vertical projection of the second gap G2 is the second gap G2. Three areas. The heavily doped implants of the second region and the third region in FIGS. 7A and 7B are covered by the half-tone photoresist layer PR1, so the second region and the third region are undoped regions. In the display area AA, a part of the metal pattern of the metal layer 150 is removed by the binary photoresist layer PR2, and a gate GA and a scan line SL are formed (see FIG. 1B ). Since the sidewall of the metal layer 150 retracts after the heavily doped implantation in FIG. 7A and FIG. Layer 140 is undoped between gate GA and the vertical projection of heavily doped region P. That is, the dielectric layer 140 around the heavily doped region P is undoped. Since the sidewalls of the outermost first part P1 of the halftone photoresist layer PR1 shrink inwardly during photoresist ashing, when forming the outermost dummy wire 156 of the wire layer 152, the width of the dummy wire 156 It is also smaller than the width of the fan-out wire 154 .

Referring to FIG. 10A and FIG. 10B, after removing the halftone photoresist layer PR1 and the binary photoresist layer PR2, perform lightly doped implantation to form lightly doped regions in the fan-out region FO and the display region AA In the first region, the second region and the third region of the dielectric layer 140 . Specifically, when the lightly doped implant is performed, the dopant is implanted into the area not covered by the fan-out wire 154 , the dummy wire 156 , the gate GA and the scan line SL (see FIG. 1B ). For example, the region of the dielectric layer 140 corresponding to the vertical projection of the first gap G1 includes the first lightly doped region N1. The region of the dielectric layer 140 corresponding to the vertical projection of the second gap G2 includes the second lightly doped region N2. The region of the dielectric layer 140 corresponding to the vertical projection of the heavily doped region P and the dummy wire 156 includes a third lightly doped region N3. That is to say, the heavily doped region P and the second lightly doped region N2 are located on opposite sides of the dummy wire 156 , and the third lightly doped region N3 is between the dummy wire 156 and the heavily doped region P. Moreover, there is no heavily doped region P on both sides of the fan-out wire 154 .

Since the first lightly doped region N1, the second lightly doped region N2 and the third lightly doped region N3 are formed simultaneously and the ions are uniformly implanted, the first lightly doped region N1, the second lightly doped region The ion concentrations of the heavily doped region N2 and the third lightly doped region N3 are substantially the same, and in the first lightly doped region N1, the second lightly doped region N2, and the third lightly doped region N3, along The concentration in the direction touching the surface of the dielectric layer 140 is substantially unchanged. The dopant dose of the lightly doped implant is smaller than that of the heavily doped implant, for example, the dopant dose of the lightly doped implant is one-tenth of that of the heavily doped implant. Therefore, the heavily doped region P has an ion concentration higher than that of the first lightly doped region N1 , the second lightly doped region N2 and the third lightly doped region N3 . Different dopants can be implanted according to the type of active device to be formed. For example, when an NMOS TFT is to be formed, N-type doping can be performed, and the concentration of the dopant, such as phosphorus, is about 1E18 atoms/cm3. When a PMOS TFT is to be formed, P-type doping may be performed, and the concentration of the dopant, such as boron, is about 1E18 atoms/cm3 to about 1E19 atoms/cm3.

Further material layers are formed on the substrate 110 with reference to FIGS. 11A to 15 . Referring to FIG. 11A and FIG. 11B, an interlayer dielectric layer 160 is formed on the substrate 110, the fan-out wire 154, the dummy wire 156, the gate electrode GA and the scanning line SL (see FIG. 1B ), and the display area AA A metal layer is formed on the interlayer dielectric layer 160 , and then the metal layer is patterned to form the source SO and the drain DR. While forming the source SO and the drain DR, it also includes forming the data line DL connected to the source SO.

Referring to FIG. 12A and FIG. 12B, a protection layer 170 is formed on the fan-out region FO and the interlayer dielectric layer 160 of the display region AA, the source electrode SO, the drain electrode DR and the data line DL, and then a via is formed in the protection layer 170. Hole V1 to expose the drain DR. Referring to FIGS. 13 to 15, an electrode layer 180 is formed on the protection layer 170 of the display area AA. Specifically, in FIG. 13 , the lower pixel electrode 182 is formed on the protective layer 170 . For example, a transparent conductive layer is first formed on the passivation layer 170 , and then the transparent conductive layer is patterned to form the lower pixel electrode 182 . The lower pixel electrode 182 has an opening, the opening is located directly above the through hole V1, and the size of the opening is larger than the size of the through hole V1. In FIG. 14, an insulating layer 184 is formed on the passivation layer 170 and the lower pixel electrode 182, and an opening is formed in the insulating layer 184 to expose the drain DR. Next, an upper pixel electrode 186 is formed on the insulating layer 184 . The upper pixel electrode 186 passes through the passivation layer 170 and the insulating layer 184 and is connected to the drain DR. For example, another transparent conductive layer is formed on the insulating layer 184 first, and then the transparent conductive layer is patterned to form the upper pixel electrode 186 . The upper pixel electrode 186 can be connected to the drain DR through the via hole V1, and a part of the upper pixel electrode 186 above the lower pixel electrode 182 has a plurality of closed openings O1, and these closed openings O1 are used to control the orientation of the LCD.

FIG. 16A to FIG. 26C illustrate cross-sectional views of the process of forming the array substrate 100' in other embodiments of the present disclosure. The top view of the fan-out region FO of the array substrate 100' formed in FIGS. 16A to 26B is shown in FIG. 26D. Figure 16A, Figure 17A, Figure 18A, Figure 19A, Figure 20A, Figure 21A, Figure 22A, Figure 23A, Figure 24A, Figure 25A and Figure 26A are along Figure 26D A cross-sectional view of the line F-F of the fan-out region FO. Figure 16B, Figure 17B, Figure 18B, Figure 19B, Figure 20B, Figure 21B, Figure 22B, Figure 23B, Figure 24B, Figure 25B and Figure 26B are along Figure 1B A cross-sectional view of line A-B-C-D of display area AA. Figure 16C, Figure 17C, Figure 18C, Figure 19C, Figure 20C, Figure 21C, Figure 22C, Figure 23C, Figure 24C, Figure 25C and Figure 26C are along Figure 26D A cross-sectional view of the line G-G of the fan-out region FO. Referring to FIGS. 16A to 16C , a buffer layer 120 is formed on the substrate 110 . In the display area AA, the shielding metal 130 may be formed before the buffer layer 120 is formed. The steps in Figures 16A to 16C are similar to the details in Figures 2A and 2B.

Referring to FIGS. 17A to 17C , a dielectric layer 140 is formed on the substrate 110 and the buffer layer 120 . In the display area AA, before the dielectric layer 140 is formed, the channel layer CH may be formed first. Next, a dielectric layer 140 is formed to cover the channel layer CH. The difference between FIG. 17A to FIG. 17C and FIG. 3A and FIG. 3B is that while the channel layer CH is formed, the semiconductor layer 190 is also formed under the dielectric layer 140 of the fan-out region FO, so the semiconductor layer 190 is formed on in the dielectric layer 140 . The semiconductor layer 190 and the channel layer CH are formed by patterning the same semiconductor layer. The semiconductor layer 190 in the fan-out area FO can be used to reduce the resistance of the subsequently formed fan-out wires.

Referring to FIGS. 18A to 18C , in the display area AA and the fan-out area FO, a metal layer 150 is formed on the dielectric layer 140 and the semiconductor layer 190 , and a photoresist layer PR is formed on the metal layer 150 . The steps in Fig. 18A to Fig. 18C are similar to the details in Fig. 4A and Fig. 4B.

Referring to FIG. 19A to FIG. 19C , the photoresist layer PR in the fan-out area FO is exposed by the halftone mask HM to form the halftone photoresist layer PR1 on the metal layer 150 . On the other hand, the photoresist layer PR in the display area AA is exposed by the binary mask BM to form the binary photoresist layer PR2 on the metal layer 150 . The semiconductor layer 190 is slightly wider than the first portion P1 of the half-tone photoresist layer PR1. The first portion P1 of the half-tone photoresist layer PR1 is on the semiconductor layer 190 and parallel to the semiconductor layer 190 . The steps in Fig. 19A to Fig. 19C are similar to the details in Fig. 5A and Fig. 5B. In some embodiments, in FIG. 19C , the metal layer 150 is also partially removed to expose a portion of the dielectric layer 140 .

Referring to FIG. 20A to FIG. 20C, a first wet etching is performed. In the fan-out area FO, a part of the metal layer 150 is removed by the half-tone photoresist layer PR1 to form a metal pattern on the fan-out area FO of the substrate 110 and expose the second layer of the dielectric layer 140 of the fan-out area FO. an area. On the other hand, in the display area AA, part of the metal layer 150 is removed by the binary photoresist layer PR2 to form a metal pattern on the display area AA of the substrate 110 and expose the dielectric layer 140 of the display area AA. first area. The steps in Fig. 20A to Fig. 20C are similar to the details in Fig. 6A and Fig. 6B.

Referring to FIGS. 21A to 21C, a heavily doped implant is performed to form a heavily doped region P in the channel region CH. The heavily doped region P is also formed in the fan-out region FO and the first region (ie the region exposed by the metal pattern) of the dielectric layer 140 in the display region AA. The steps in Fig. 21A to Fig. 21C are similar to the details in Fig. 7A and Fig. 7B. In some embodiments, heavily doped regions P are also formed in the dielectric layer 140 in FIG. 21C.

Referring to FIG. 22A to FIG. 22C , a part of the half-tone photoresist layer PR1 and the binary photoresist layer PR2 is removed by, for example, photoresist ashing. In the fan-out area FO, the second portion P2 of the halftone photoresist layer PR1 is removed to expose a portion of the metal pattern of the metal layer 150 . On the other hand, in the display area AA, the binary photoresist layer PR2 is also partially removed from the sidewall, so that the sidewall of the binary photoresist layer PR2 shrinks inward, and part of the metal layer 150 is exposed. The steps in Fig. 22A to Fig. 22C are similar to the details in Fig. 8A and Fig. 8B. In some embodiments, the sidewalls of the half-tone photoresist layer PR1 in FIG. 22C are also retracted.

Referring to FIG. 23A to FIG. 23C, a second wet etching is performed. In the fan-out area FO, a part of the metal pattern of the metal layer 150 is removed by the first part P1 of the halftone photoresist layer PR1, and a wire layer 152 is formed. The wire layer 152 includes a plurality of fan-out wires 154 and dummy wires. 156. In the display area AA, a part of the metal pattern of the metal layer 150 is removed by the binary photoresist layer PR2, and a gate GA and a scan line SL are formed (see FIG. 1B ). The steps in Fig. 23A to Fig. 23C are similar to the details in Fig. 9A and Fig. 9B. The difference between the steps of FIG. 23A to FIG. 23C and FIG. 9A and FIG. 9B is that in FIG. 23A and FIG. Wire 156 is dummy. Additionally, in Figures 23A and 23C, the fan-out wire 154 is not a continuous wire. In some embodiments, a portion of the fan-out wire 154 in Figure 23C is also removed.

Referring to FIG. 24A to FIG. 24C, after removing the halftone photoresist layer PR1 and the binary photoresist layer PR2, lightly doped implantation is performed to form lightly doped regions in the fan-out region FO and the display region AA In the first region, the second region and the third region of the dielectric layer 140 . The steps in Fig. 24A to Fig. 24C are similar to the details in Fig. 9A and Fig. 9B. The difference between Fig. 24A to Fig. 24C and Fig. 9A and Fig. 9B is that when performing light doping, ions will be implanted to the edge of semiconductor layer 190, so the edge of semiconductor layer 190 has a fourth light degree. Doped region N4. In some embodiments, after the lightly doped implantation, the lightly doped region has the highest doping concentration at or slightly above the edge of the semiconductor layer 190 in the vertical direction. In some embodiments, the dielectric layer 140 and the semiconductor layer 190 have a fifth lightly doped region N5 located on the side of the fan-out wire 154 , as shown in FIG. 24C .

Referring to FIG. 25A to FIG. 26C, the interlayer dielectric layer 160 and the metal layer 200 are formed on the substrate 110, the fan-out wire 154, the dummy wire 156, the gate electrode GA and the scanning line, and the interlayer dielectric layer on the display area AA A data line DL, a source SO or a drain DR is formed on 160 . The steps in Fig. 25A to Fig. 25C are similar to the details in Fig. 11A and Fig. 11B. The difference between FIGS. 25A to 26C and FIGS. 11A and 11B is that, in the fan-out region FO, after the interlayer dielectric layer 160 is formed, vias exposing the fan-out wire 154 are formed in the interlayer dielectric layer 160 . The hole V2 and the via hole V3 exposing the semiconductor layer 190 . Next, a metal layer 200 is formed on the interlayer dielectric layer 160 . The metal layer 200 can be electrically connected to the fan-out wire 154 through the via hole V2, and connected to the semiconductor layer 190 through the via hole V3. The metal layer 200 is made by patterning the same conductive layer as the data line DL, the source electrode SO or the drain electrode DR. The metal layer 200 in the fan-out area FO can be used to connect the fan-out wire 154 and the semiconductor layer 190 to further reduce the resistance of the fan-out wire 154 . In some embodiments, the semiconductor layer 190 may not be electrically connected to the fan-out wire 154 , so there is no other metal layer (such as the metal layer 200 ) on the fan-out wire 154 . Next, other material layers can be formed on the fan-out area FO and the display area AA, and the relevant details are the same as those in FIG. 12A to FIG. 15 , and will not be repeated here.

FIG. 27A to FIG. 35C illustrate cross-sectional views of the process of forming the array substrate 100 ″ in some embodiments of the present disclosure. The top view of the fan-out region FO of the array substrate 100'' formed in FIGS. 27A to 35C is shown in FIG. 35D. Figure 27A, Figure 28A, Figure 29A, Figure 30A, Figure 31A, Figure 32A, Figure 33A, Figure 34A and Figure 35A are along the line H-H of the fan-out area FO in Figure 35D cross-sectional view of . Figure 27B, Figure 28B, Figure 29B, Figure 30B, Figure 31B, Figure 32B, Figure 33B, Figure 34B and Figure 35B are along the line A-B-C-D of the display area AA in Figure 1B Cross-sectional view. Figure 27C, Figure 28C, Figure 29C, Figure 30C, Figure 31C, Figure 32C, Figure 33C, Figure 34C and Figure 35C are along the line I-I of the fan-out area FO in Figure 35D cross-sectional view of . Referring to FIGS. 27A to 27C , a buffer layer 120 is formed on the substrate 110 . The steps in Fig. 27A to Fig. 27C are similar to the details in Fig. 2A and Fig. 2B. The difference between the steps in FIG. 27A to FIG. 27C and FIG. 2A and FIG. 2B is that, in the fan-out area FO, before the buffer layer 120 is formed, the shielding metal 130 can also be formed first. Accordingly, the shielding metal 130 is formed between the buffer layer 120 and the substrate 110 . The fan-out area FO and the shielding metal 130 in the display area AA are made of the same metal layer at the same time. In some embodiments, the shielding metal 130 can be used to reduce the resistance of the fan-out wire 154 .

Referring to FIGS. 28A to 28C , a dielectric layer 140 is formed on the substrate 110 and the buffer layer 120 . In the display area AA, before the dielectric layer 140 is formed, the channel layer CH may be formed first. Next, a dielectric layer 140 is formed to cover the channel layer CH. The steps in Fig. 28A to Fig. 28C are the same as the details in Fig. 3A and Fig. 3B. After the dielectric layer 140 is formed, the dielectric layer 140 can be patterned to form a via hole V4 to expose the shielding metal 130 in the fan-out region FO.

Referring to FIGS. 29A to 29C , in the display area AA and the fan-out area FO, a metal layer 150 is formed on the dielectric layer 140 , and a photoresist layer PR is formed on the metal layer 150 . The steps in Fig. 29A to Fig. 29C are similar to the details in Fig. 4A and Fig. 4B. In the fan-out area FO, the metal layer 150 penetrates the dielectric layer 140 and the buffer layer 120 through the via hole V4 , and contacts the shielding metal 130 .

Referring to FIG. 30A to FIG. 30C , the photoresist layer PR in the fan-out area FO is exposed by the halftone mask HM to form the halftone photoresist layer PR1 on the metal layer 150 . On the other hand, the photoresist layer PR in the display area AA is exposed by the binary mask BM to form the binary photoresist layer PR2 on the metal layer 150 . The shielding metal 130 may be slightly wider than the first portion P1 of the half-tone photoresist layer PR1. The first portion P1 of the halftone photoresist layer PR1 is on the shielding metal 130 and parallel to the shielding metal 130 . The steps in Fig. 30A to Fig. 30C are similar to the details in Fig. 5A and Fig. 5B.

Referring to FIGS. 31A to 31C, a first wet etching is performed. In the fan-out area FO, a part of the metal layer 150 is removed by the half-tone photoresist layer PR1 to form a metal pattern on the fan-out area FO of the substrate 110 and expose the second layer of the dielectric layer 140 of the fan-out area FO. an area. On the other hand, in the display area AA, part of the metal layer 150 is removed by the binary photoresist layer PR2 to form a metal pattern on the display area AA of the substrate 110 and expose the dielectric layer 140 of the display area AA. first area. The steps in Fig. 20A to Fig. 20C are similar to the details in Fig. 6A and Fig. 6B.

Referring to FIGS. 32A to 32C , a heavily doped implant is performed to form a heavily doped region P in the channel region CH. The heavily doped region P is also formed in the fan-out region FO and the first region (ie the region exposed by the metal pattern) of the dielectric layer 140 in the display region AA. The steps in Fig. 32A to Fig. 32C are similar to the details in Fig. 7A and Fig. 7B.

Referring to FIG. 33A to FIG. 33C , a part of the half-tone photoresist layer PR1 and the binary photoresist layer PR2 is removed by, for example, photoresist ashing. In the fan-out area FO, the second portion P2 of the halftone photoresist layer PR1 is removed to expose a portion of the metal pattern of the metal layer 150 . On the other hand, in the display area AA, the binary photoresist layer PR2 is also partially removed from the sidewall, so that the sidewall of the binary photoresist layer PR2 shrinks inward, and part of the metal layer 150 is exposed. The steps in Fig. 22A to Fig. 22C are similar to the details in Fig. 8A and Fig. 8B.

Referring to FIGS. 34A to 34C, a second wet etch is performed. In the fan-out area FO, a part of the metal pattern of the metal layer 150 is removed by the first part P1 of the halftone photoresist layer PR1, and a wire layer 152 is formed. The wire layer 152 includes a plurality of fan-out wires 154 and dummy wires. 156. In the display area AA, a part of the metal pattern of the metal layer 150 is removed by the binary photoresist layer PR2, and a gate GA and a scan line SL are formed (see FIG. 1B ). The steps in Fig. 34A to Fig. 34C are similar to the details in Fig. 9A and Fig. 9B. The shielding metal 130 is on the fanout wire 154 and the dummy wire 156 and parallel to the fanout wire 154 and the dummy wire 156 . In some embodiments, the shielding metal 130 is slightly wider than the fan-out wire 154 and the dummy wire 156 . The fan-out wire 154 penetrates the dielectric layer 140 and the buffer layer 120 through the via hole V4 and contacts the shielding metal 130 , and the fan-out wire 154 is electrically connected to the shielding metal 130 .

Referring to FIG. 35A to FIG. 35C, after removing the halftone photoresist layer PR1 and the binary photoresist layer PR2, lightly doped implantation is performed to form lightly doped regions in the fan-out region FO and the display region AA In the first region, the second region and the third region of the dielectric layer 140 . The steps in Figures 35A to 35C are similar to the details in Figures 10A and 10B. Next, other material layers can be formed on the fan-out area FO and the display area AA, and the relevant details are the same as those in FIG. 11A to FIG. 15 , and will not be repeated here.

To sum up, when the halftone mask is used to form the fan-out wires in the fan-out area of the array substrate, the width of the second part of the halftone light group layer can be formed to be smaller than the exposure resolution. Therefore, the pitch between adjacent fan-out wires can be shortened to a pitch narrower than the exposure resolution. In addition, when forming the fan-out wires, only one etching is performed, so the distance between the fan-out wires does not widen. In this way, the number of fan-out wires can be increased per unit area of the fan-out area.

Although the present disclosure has been disclosed above with embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of this disclosure should be defined by the scope of the appended patent application.

100: Array substrate 100': array substrate 100'': array substrate 110: Substrate 120: buffer layer 130: shielded metal 140: dielectric layer 150: metal layer 152: wire layer 154: Fan-out wire 156: Dummy wire 160: interlayer dielectric layer 170: protective layer 182: Lower pixel electrode 184: insulating layer 186: Upper pixel electrode 190: semiconductor layer 200: metal layer AA: display area BM: binary mask BM1: transparent substrate BM2: opaque pattern DR: drain DL: data line FO: fan-out area GA: Gate HM: halftone mask HM1: transparent substrate HM2: opaque patterns HM3: halftone film N1: the first lightly doped region N2: the second lightly doped region N3: the third lightly doped region N4: The fourth lightly doped region N5: fifth lightly doped region O1: closed opening P: heavily doped region P1: part one P2: Part Two PR1: halftone photoresist layer PR2: Binary photoresist layer R1: Region R2: area

SL: scan line

SO: source

SP: sub-pixel area

TR: Transistor

FIG. 1A shows a top view of an array substrate according to some embodiments of the present disclosure. FIG. 1B shows an enlarged top view of the region R1 in FIG. 1A . Figure 1C shows a cross-sectional view along the line A-B-C-D of Figure 1B. FIG. 1D shows an enlarged top view of the region R2 in FIG. 1A . FIG. 2A to FIG. 15 illustrate cross-sectional views of a process for forming an array substrate in some embodiments of the present disclosure. FIG. 16A to FIG. 26C are cross-sectional views of the process of forming the array substrate in other embodiments of the present disclosure. FIG. 26D is a top view of the fan-out region of the array substrate in other embodiments of the present disclosure. FIG. 27A to FIG. 35C are cross-sectional views of the process of forming the array substrate in other embodiments of the present disclosure. FIG. 35D shows a top view of the fan-out region of the array substrate in other embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

110: Substrate

120: buffer layer

140: dielectric layer

152: wire layer

154: Fan-out wire

156: Dummy wire

N1: the first lightly doped region

N2: the second lightly doped region

P: heavily doped region

Claims (14)

An array substrate, comprising: A substrate having a display area and a fan-out area; a dielectric layer located on the substrate; an active device on the display area of the substrate; A plurality of fan-out wires are electrically connected to the active element, there is a first gap between two adjacent fan-out wires, and the area of the dielectric layer corresponding to the vertical projection of the first gap includes a first light weight doped regions; and At least one dummy wire is located outside the fan-out wires. The array substrate according to claim 1, wherein there is a second gap between the dummy wire and one of the fan-out wires, and the area of the dielectric layer corresponding to the vertical projection of the second gap includes a first gap Two lightly doped regions. The array substrate according to claim 2, wherein the dielectric layer further includes a heavily doped region, the heavily doped region and the second lightly doped region are located on opposite sides of the dummy wire, and the heavily doped An ion concentration of the impurity region is higher than an ion concentration of the two lightly doped regions. The array substrate according to claim 3, wherein the dielectric layer includes a third lightly doped region corresponding to the region between the heavily doped region and the vertical projection of the dummy wire, the heavily doped region of the The ion concentration is higher than an ion concentration of the third lightly doped region. The array substrate as claimed in claim 4, wherein the ion concentration of the first lightly doped region is substantially equal to the ion concentration of the third lightly doped region. The array substrate as claimed in claim 1 further includes a plurality of semiconductor layers in the dielectric layer and under the fan-out wires. The array substrate as claimed in claim 6, wherein a plurality of edges of the semiconductor layers have a plurality of fourth lightly doped regions. The array substrate as claimed in claim 6, wherein the semiconductor layers are respectively electrically connected to the fan-out wires. The array substrate as claimed in claim 1, wherein the dummy wire is structurally separated from the active device. The array substrate as claimed in claim 1, wherein in the first lightly doped region, the concentration in a direction along a surface of the dielectric layer is substantially constant. The array substrate as claimed in claim 1 further includes a plurality of shielding metals between the dielectric layer and the substrate and under the fan-out wires. The array substrate as claimed in claim 11, wherein the shielding metals are respectively electrically connected to the fan-out wires. The array substrate as claimed in claim 1, wherein the width of the dummy wire is smaller than the width of the fan-out wires. A method of manufacturing an array substrate, comprising: forming a dielectric layer on a substrate; forming a metal layer on the dielectric layer; forming a photoresist layer on the metal layer; exposing the photoresist layer through a halftone mask to form a halftone photoresist layer on the metal layer, the halftone photoresist layer having a first portion with a higher height and height on a fan-out region of the substrate a lower second portion, and the halftone photoresist layer exposes a portion of the metal layer; performing a first wet etching to remove the portion of the metal layer through the halftone photoresist layer to form a metal pattern on the fan-out region of the substrate and expose a first portion of the dielectric layer an area; performing a heavily doped implant to form a heavily doped region in the first region of the dielectric layer; removing the second portion of the halftone photoresist layer to expose a portion of the metal pattern; performing a second wet etch to remove the portion of the metal pattern through the first portion of the half-tone photoresist layer and form a wire layer including a plurality of fan-out wires, the fan-out wires having a second region of the dielectric layer exposed between the wires; and A lightly doped implant is performed to form a lightly doped region in a first region and the second region of the dielectric layer.

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