TWI589004B - Method for preparing nano-vacuum tube field effect transistor - Google Patents

Description

Vacuum nano tube field effect transistor and manufacturing method thereof

The present invention relates to the field of semiconductor manufacturing, and in particular to a vacuum nanotube field effect transistor and a method of fabricating the same.

In order to achieve faster computing speed, greater data storage and more functions, semiconductor wafers are moving toward higher integration. The size of various semiconductor components, including transistors, continues to shrink. By reducing the size of the transistor, increasing the transistor density, increasing the integration of the wafer, and reducing power consumption, the performance of the wafer is continuously improved.

However, according to the current state of the art, the transistor has not been made smaller. It can be seen that the physical size of the transistor has reached its limit, and it has been very difficult to improve the performance by reducing the physical size. To this end, the industry has designed and developed a variety of new types of transistors to meet market demand, such as nano carbon tube field effect transistors. The carbon nanotube field effect transistor can overcome the limitation of manufacturing conditions and further reduce the size of the component by replacing the channel material of the conventional MOSFET structure by using a single carbon nanotube or a carbon nanotube array. At present, the size of the Carbon Nano Tube Field Effect Transistor (CNTFET) with self-aligned gate has been reduced to 20 nm, and the uniformity of the gate surrounding the carbon nanotube channel has also been obtained. Consolidation.

However, in actual manufacturing and use, it has been found that the size and performance of the existing carbon nanotube field effect transistors cannot meet the market requirements. How to further reduce the vacuum tube The size of the field effect transistor and the improvement of the performance of the component are still technical problems to be solved by those skilled in the art.

The object of the present invention is to provide a vacuum nanotube field effect transistor and a manufacturing method thereof, so as to solve the problem that the size and performance of the vacuum nanotube field effect transistor in the prior art cannot meet the market requirements.

In order to solve the above problems, the present invention provides a method for manufacturing a vacuum nanotube field effect transistor, the method for manufacturing the vacuum nanotube field effect transistor, comprising: providing a semiconductor substrate; forming a first layer on the semiconductor substrate a dielectric layer, a source, a second dielectric layer, and an aluminum layer; anodizing the aluminum layer to form an anodized aluminum structure, the anodized aluminum structure having a plurality of uniformly arranged first via holes The bottom of the first via exposes the second dielectric layer, the anodized aluminum structure includes a gate and a gate dielectric layer surrounding the gate; etching the second dielectric layer to Forming a plurality of second through holes, the second through holes communicating with the first through holes, and a bottom of the second through holes exposing the source; and forming a drain under vacuum conditions, A drain is overlaid on the anodized aluminum structure to form a plurality of nano vacuum tubes.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, the specific process of anodizing the aluminum layer to form an anodized aluminum structure comprises: treating the aluminum layer in an acidic solution Performing a first anodizing treatment; removing the oxide generated by the first anodizing treatment; and subjecting the aluminum layer to a second anodizing treatment in an acidic solution.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, the acidic solution used in the first anodizing treatment and the second anodizing treatment is an oxalic acid solution, and the oxalic acid solution is The concentration ranges from 0.2 molar to 0.5 molar, the temperature of the first anodizing treatment and the second anodizing is between 5 ° C and 15 ° C, the first anodizing treatment The fixed voltage for the second anodization is between 35V and 45V.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, the concentration of the oxalic acid solution is 0.3 molar, the temperature of the first anodizing treatment and the second anodizing treatment. Both were 10 ° C, and the fixed voltages of the first anodizing treatment and the second anodizing treatment were both 40V.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, before the gate dielectric layer is subjected to plasma treatment, the second dielectric layer is etched to form a plurality of second via holes. The method further includes: removing the anodized aluminum in the isolation region by an etching process.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, when the drain is formed under vacuum, the method further includes: forming a source emitting end on the source.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, after forming the drain and the source emitting end under vacuum, the method further includes: removing the source in the isolation region by an etching process a transmitting end and a second dielectric layer; and processing the source emitting end by an annealing process to make the surface into a circular arc shape.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, the annealing process has a reaction temperature ranging from 400 ° C to 600 ° C, and the gas used in the annealing process is hydrogen, nitrogen or Any one of argon or any combination thereof.

Optionally, in the method for manufacturing the vacuum nanotube field effect transistor, After the source emitting end is processed by using an annealing process, the method further includes: forming a third dielectric layer in the isolation region, wherein the third dielectric layer is integrated with the second dielectric layer.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are all cerium oxide.

Optionally, in the manufacturing method of the vacuum nanotube field effect transistor, the materials of the source and the drain are low work function metals.

Correspondingly, the present invention provides a vacuum nanotube field effect transistor, the vacuum nanotube field effect transistor comprising: a semiconductor substrate; a first dielectric layer formed on the semiconductor substrate; a source on a dielectric layer; a second dielectric layer formed on the source; an anodized aluminum structure formed on the second dielectric layer; and a bungee formed on the anodized aluminum structure ; Wherein, the anodized aluminum structure comprises a gate and a gate dielectric layer surrounding the gate, and the drain covers the anodized aluminum structure to form a plurality of nano vacuum tubes.

Optionally, in the vacuum nanotube field effect transistor, the method further includes: a third dielectric layer, wherein the third dielectric layer is located in the isolation region and is integrated with the second dielectric layer.

Optionally, in the vacuum nanotube field effect transistor, the nano vacuum tube has a length ranging from 1 nm to 100 nm, and the nano vacuum tube has a diameter ranging between 1 nm and 50 nm. The vacuum in the vacuum tube of the nanometer ranges from 0.01 Torr to 50 Torr.

In summary, in the vacuum nanotube field effect transistor provided by the present invention and the manufacturing method thereof, the anode nano tube structure is formed by forming an anodized aluminum oxide structure, thereby reducing the component size and improving the size. The performance of the component.

100‧‧‧vacuum nano tube field effect transistor

110‧‧‧Semiconductor substrate

120‧‧‧First dielectric layer

130‧‧‧Source layer

140‧‧‧Second dielectric layer

140a‧‧‧second through hole

150‧‧‧Aluminum layer

150a‧‧‧first through hole

151‧‧‧ gate

152‧‧‧gate dielectric layer

160‧‧‧汲pole

162‧‧‧Source emitter

170‧‧‧ Third dielectric layer

180‧‧‧Nano vacuum tube

1 is a flow chart showing a method of fabricating a vacuum nanotube field effect transistor according to an embodiment of the present invention; and FIGS. 2 to 9 are structures of a process for fabricating a vacuum nanotube field effect transistor according to an embodiment of the present invention; Fig. 10 is a schematic view showing the energy band of a vacuum nanotube field effect transistor according to an embodiment of the present invention.

The vacuum nanotube field effect transistor and the manufacturing method thereof according to the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and all use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.

Please refer to FIG. 1 , which is a flow chart of a method for fabricating a vacuum nanotube field effect transistor according to an embodiment of the invention. As shown in FIG. 1 , the method for manufacturing the vacuum nanotube field effect transistor includes: Step 1: providing a semiconductor substrate 110; Step 2: sequentially forming a first dielectric layer 120 on the semiconductor substrate 110, a source 130, a second dielectric layer 140, and an aluminum layer 150; Step 3: anodizing the aluminum layer 150 to form an anodized aluminum (AAO) structure having a plurality of uniform arrangements a first through hole 150a, a bottom of the first through hole 150a exposing the second dielectric layer 140, and the anodized aluminum structure includes a gate 151 and a gate dielectric layer 152 surrounding the gate 151; Step 4: etching the second dielectric layer 140 to form a plurality of second via holes 140a, the second via holes 140a and the first The through hole 150a is connected, and the bottom of the second through hole 140a exposes the source 130; Step 5: forming a drain 160 under vacuum, the drain 160 covering the anodized aluminum structure, To form a plurality of nano vacuum tubes 180.

Specifically, first, a semiconductor substrate 110 is provided. The semiconductor substrate 110 may be a germanium substrate, a germanium substrate, a III-V element compound substrate, or other semiconductor material substrate well known to those skilled in the art, and is used in this embodiment. It is a germanium substrate.

Next, as shown in FIG. 2, a first dielectric layer 120, a source 130, a second dielectric layer 140, and an aluminum layer 150 are sequentially formed on the semiconductor substrate 110.

The aluminum layer 150 is then anodized to form an anodized aluminum structure. The specific process for forming an anodized aluminum oxide (AAO) structure includes: first, performing the first anodization treatment on the aluminum layer 150 in an acidic solution; then, removing the oxide generated by the first anodizing treatment; Then, the aluminum layer 150 is subjected to a second anodization treatment in an acidic solution.

In this embodiment, the process conditions of the first anodizing treatment and the second anodizing treatment are the same. The acidic solution used in the first anodizing treatment and the second anodizing treatment is an oxalic acid solution, and the concentration of the oxalic acid solution ranges from 0.2 molar to 0.5 molar, the first anode The temperature of the second anodizing treatment is between 5 ° C and 15 ° C, and the fixed voltages of the first anodizing treatment and the second anodizing treatment are both between 35 V and 45 V.

Preferably, the concentration of the oxalic acid solution is 0.3 molar, and the temperature of the anodizing treatment The degree is 10 ° C, and the anodized voltage is a fixed voltage of 40 V.

As shown in FIG. 3, after the second anodizing treatment, an anodized aluminum structure is formed on the second dielectric layer 140, and the anodized aluminum structure has a plurality of uniformly arranged first through holes 150a. The bottom of the first through hole 150a exposes the second dielectric layer 140. The anodized aluminum structure includes a gate 151 made of aluminum and a gate dielectric layer 152 made of aluminum oxide. Electrical layer 152 surrounds gate 151.

After the anodized aluminum structure is formed, the second dielectric layer 140 exposed by the first via hole 150a is etched to form a plurality of second via holes 140a. As shown in FIG. 4, the second through hole 140a communicates with the first through hole 150a, and the bottom of the second through hole 140a exposes the source 130.

Thereafter, as shown in FIG. 5, the anodized aluminum material in the isolation region is removed by an etching process.

Next, as shown in FIG. 6, the drain 160 and the source emitting end 162 are simultaneously formed under vacuum conditions, and since the drain 160 completely covers the top of the plurality of first via holes 150a, a plurality of layers are formed. The nano vacuum tube 180 has one end of a circular arc structure (ie, the surface of the drain 160), and the other end of the nano vacuum tube 180 has a spiked structure (ie, the surface of the source emitting end 162). .

In this embodiment, the length of the nano vacuum tube 180 ranges from 1 nm to 100 nm, the diameter of the nano vacuum tube 180 ranges from 1 nm to 50 nm, and the vacuum degree in the nano vacuum tube 180 ranges from 0.01 to 0.01 nm. Torr to 50 Torr. Preferably, the length of the nano vacuum tube 180 is 10 nm, 20 nm or 50 nm, the diameter of the nano vacuum tube 180 is 3 nm, 5 nm or 10 nm, and the degree of vacuum in the nano vacuum tube 180 is 0.05 Torr, 1 Torr, 10 Torr. 20 Torr, 30 Torr or 40 Torr.

In this embodiment, the source 130 and the drain 160 are made of a low work function metal, such as zirconium (Zr), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum. (Mo), tungsten (W), iron (Fe), cobalt (Co), vanadium (Pd), copper (Cu), aluminum (Al), gallium (Ga), indium (In), titanium (Ti), nitrogen Titanium (TiN), tantalum nitride (TaN), diamond, or any combination thereof.

Thereafter, as shown in FIG. 7, the source emitting end 162 and the second dielectric layer 140 in the isolation region are removed by an etching process, and etching stops at the source 130.

Thereafter, as shown in Fig. 8, annealing treatment is performed so that the other end of the nano vacuum tube 180 (i.e., the surface of the source emitting end 162) also has a circular arc structure. Through the annealing process, the reliability and service life of the component can be improved.

In this embodiment, the annealing process has a reaction temperature ranging from 400 degrees Celsius to 600 degrees Celsius. The gas used in the high temperature annealing process is any one of hydrogen (H ₂ ), nitrogen (N ₂ ), and argon (Ar), or any combination thereof.

Finally, as shown in FIG. 9, a third dielectric layer 170 is formed in the isolation region, and the third dielectric layer 170 is integrated with the second dielectric layer 140.

In this embodiment, the first dielectric layer 120, the second dielectric layer 140, and the third dielectric layer 170 are made of the same material and are all yttrium oxide.

So far, a vacuum nanotube field effect transistor 100 is formed. The gate of the vacuum nanotube field effect transistor 100 is vertically arranged between the source and the drain. This structure can not only improve the performance of the device, but also further reduce the component size.

The energy band diagram of the vacuum nanotube field effect transistor 100 during operation can be referred to Take the picture in Figure 10. As shown in Fig. 10, when the gate voltage (Vg) is greater than the threshold voltage (Vt), the transistor is turned on, and since the migration distance of the electron or hole from the source to the drain is shorter, the entire component is Better performance. Among them, the threshold voltage (Vt) is also called the turn-on voltage.

Accordingly, the present invention also provides a vacuum nanotube field effect transistor prepared by the method of manufacturing a vacuum nanotube field effect transistor as described above.

The vacuum nanotube field effect transistor 100 described in FIG. 9 further includes: a semiconductor substrate 110; a first dielectric layer 120 formed on the semiconductor substrate 110; formed on the first dielectric layer 120 a source 130; a second dielectric layer 140 formed on the source 130; an anodized aluminum structure formed on the second dielectric layer 140; a bungee formed on the anodized aluminum structure 160; wherein the anodized aluminum structure comprises a gate 151 and a gate dielectric layer 152 surrounding the gate 151, the gate 160 covering the anodized aluminum structure to form a plurality of nano vacuum tubes 180.

Specifically, the vacuum nanotube field effect transistor 100 further includes a third dielectric layer 170, and the third dielectric layer 170 is located in the isolation region and integrated with the second dielectric layer 140. The nano vacuum tube 180 has a length ranging from 1 nm to 100 nm, the nano vacuum tube 180 has a diameter ranging from 1 nm to 50 nm, and the vacuum inside the nano vacuum tube 180 has a vacuum ranging from 0.01 Torr to 50 Torr.

In summary, in the vacuum nanotube field effect transistor and the manufacturing method thereof provided by the embodiments of the present invention, the anode nano tube structure is formed by the anode alumina structure to form a vertical structure vacuum nano tube transistor, thereby further reducing the component size. And improve the performance of the components.

The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any person skilled in the art can, within the scope of the technical solution of the present invention, It is to be understood that the technical solutions and the technical contents disclosed in the disclosure are all changes in the form of equivalents, modifications, and the like, which are within the scope of the present invention.

Process steps for manufacturing a vacuum nanotube field effect transistor

Claims (15)

A method for manufacturing a vacuum nanotube field effect transistor, comprising: providing a semiconductor substrate; sequentially forming a first dielectric layer, a source, a second dielectric layer and an aluminum layer on the semiconductor substrate; The layer is anodized to form an anodized aluminum structure having a plurality of uniformly arranged first vias, the bottom of the first via exposing the second dielectric layer, The anodized aluminum structure includes a gate and a gate dielectric layer surrounding the gate; etching the second dielectric layer to form a plurality of second vias, the second via and the first via Connected, and the bottom of the second via exposes the source; and a drain is formed under vacuum, the drain covering the anodized aluminum structure to form a plurality of nano vacuum tubes. The method for producing a vacuum nanotube field effect transistor according to claim 1, wherein the step of anodizing the aluminum layer to form an anodized aluminum structure comprises: performing the aluminum layer in an acidic solution Anodizing treatment; removing the oxide generated by the first anodizing treatment; and subjecting the aluminum layer to a second anodizing treatment in an acidic solution. The method for producing a vacuum nanotube field effect transistor according to claim 2, wherein the acidic solution used in the first anodizing treatment and the second anodizing treatment is an oxalic acid solution, and the concentration of the oxalic acid solution The range is between 0.2 molar concentration and 0.5 molar concentration, and the temperatures of the first anodizing treatment and the second anodizing treatment are both between 5 ° C and 15 ° C, the first anodizing treatment and The fixed voltage for the second anodization is between 35V and 45V. A method of manufacturing a vacuum nanotube field effect transistor according to claim 3, wherein the grass The concentration of the acid solution is 0.3 mol, the temperature of the first anodizing treatment and the second anodizing treatment are both 10 ° C, and the fixed voltage of the first anodizing treatment and the second anodizing treatment Both are 40V. The method for manufacturing a vacuum nanotube field effect transistor according to claim 1, wherein after the second dielectric layer is etched to form the plurality of second via holes before forming the drain under vacuum conditions, the method further includes: The anodized aluminum in the isolated region is removed by an etching process. The method for manufacturing a vacuum nanotube field effect transistor according to claim 5, wherein, while forming the drain under vacuum, the method further comprises: forming a source emitting end on the source. The method for fabricating a vacuum nanotube field effect transistor according to claim 6, wherein after forming the drain and the source emitting end under vacuum, the method further comprises: removing the source emission in the isolation region by an etching process End and second dielectric layer. The method for fabricating a vacuum nanotube field effect transistor according to claim 7, wherein after removing the source emitting end and the second dielectric layer in the isolation region by an etching process, the method further comprises: using an annealing process pair The source emitting end is processed to have its surface become a circular arc shape. The method for manufacturing a vacuum nanotube field effect transistor according to claim 8, wherein the annealing process has a reaction temperature ranging from 400 ° C to 600 ° C, and the gas used in the annealing process is hydrogen, nitrogen or argon. Any one of the gases or any combination thereof. The method for manufacturing a vacuum nanotube field effect transistor according to claim 8, wherein after the source emitting end is processed by using an annealing process, the method further comprises: forming a third dielectric layer in the isolation region The third dielectric layer is integrated with the second dielectric layer. The method for manufacturing a vacuum nanotube field effect transistor according to claim 10, wherein the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are all cerium oxide. The method for manufacturing a vacuum nanotube field effect transistor according to claim 1, wherein the source and the drain are made of a low work function metal. A vacuum nanotube field effect transistor produced by the method for manufacturing a vacuum nanotube field effect transistor according to any one of claims 1 to 12, comprising: a semiconductor substrate; formed on the semiconductor substrate a first dielectric layer; a source formed on the first dielectric layer; a second dielectric layer formed on the source; an anodized aluminum structure formed on the second dielectric layer; a drain formed on the anodized aluminum structure; wherein the anodized aluminum structure includes a gate and a gate dielectric layer surrounding the gate, the drain covering the anodized aluminum structure Forming a plurality of nano vacuum tubes. The vacuum nanotube field effect transistor of claim 13, further comprising: a third dielectric layer, the third dielectric layer being located in the isolation region and integrated with the second dielectric layer. The vacuum nanotube field effect transistor according to claim 13, wherein the nano vacuum tube has a length ranging from 1 nm to 100 nm, and the nano vacuum tube has a diameter ranging from 1 nm to 50 nm. The vacuum in the meter vacuum tube ranges from 0.01 Torr to 50 Torr.