TWI587449B - Semiconductor package structure and method for manufacturing the same - Google Patents

Description

Semiconductor package structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.

Wire bonding is a commonly used method of providing an interconnect structure for a semiconductor package structure. However, since the wire is a relatively long conductive path, power consumption and capacitance cause problems. In addition, wires, solder balls and pads all occupy space, and the number and density of wires are therefore limited. Furthermore, the cost increases as the number of wires increases.

In recent years, through silicon vias (TSVs) have been developed, which is another method of providing interconnect structures for semiconductor package structures. The through-hole perforation is provided by an interconnect substrate having a plurality of perforations therethrough. Such a conductive path is short and the density of the conductive path can be high. However, its process is complex and costly, and production is also a problem.

This invention relates to a semiconductor structure and a method of fabricating the same that includes a new way of providing an interconnect structure.

According to some embodiments, a semiconductor package structure includes a substrate, a first chip, a first dielectric layer, a dielectric package layer, and at least one first via. The first wafer is disposed on the substrate. The first wafer has a first landing zone. The first dielectric layer is disposed on the first wafer. A dielectric encapsulation layer encapsulates the first wafer and the first dielectric layer therein. The at least one first via extends through the dielectric encapsulation layer and the first dielectric layer. The at least one first via is connected to the first landing zone of the first wafer.

According to some embodiments, a method of fabricating a semiconductor package structure includes the following steps. First, a first wafer is disposed on a substrate, and a first dielectric layer is formed on the first wafer. The first wafer has a first landing zone. Next, a dielectric encapsulation layer is formed to encapsulate the first wafer and the first dielectric layer therein. Forming at least one first perforation through the dielectric encapsulation layer. Extending the at least one first via through the first dielectric layer to the first landing region of the first wafer. Thereafter, a conductor is filled into the at least one first via to form at least one first via connected to the first landing region of the first wafer.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100, 100'‧‧‧ semiconductor package structure

102‧‧‧Substrate

104, 104'‧‧‧ first wafer

104A, 104A’‧‧‧First Landing Area

106, 106'‧‧‧ first dielectric layer

108‧‧‧First guide hole

110‧‧‧second chip

110A, 110A’‧‧‧Second landing zone

112‧‧‧Second dielectric layer

114‧‧‧Second guide hole

116‧‧‧ Third chip

116A‧‧‧ Third Landing Area

118‧‧‧ Third dielectric layer

120‧‧‧ third guide hole

122‧‧‧fourth wafer

122A‧‧‧Four Landing Area

124‧‧‧fourth dielectric layer

126‧‧‧4th guide hole

128‧‧‧ Dielectric encapsulation layer

130‧‧‧Re-layer

A1‧‧‧ sectional area

A2‧‧‧ sectional area

A3‧‧‧ sectional area

A4‧‧‧ sectional area

O1, O1’‧‧‧ first perforation

O2, O2’‧‧‧ second perforation

O3, O3’‧‧‧ third perforation

O4, O4’‧‧‧ fourth perforation

1 is a schematic view of a semiconductor package structure in accordance with an embodiment.

2 is a schematic view of a semiconductor package structure in accordance with another embodiment.

3A to 3F are schematic views of a method of fabricating a semiconductor package structure according to an embodiment.

Please refer to FIG. 1 , which illustrates a semiconductor package structure 100 in accordance with an embodiment. The semiconductor package structure 100 includes a substrate 102 , a first wafer 104 , a first dielectric layer 106 , a dielectric encapsulation layer 128 , and at least one first via hole 108 . The first wafer 104 is disposed on the substrate 102. The first wafer 104 has a first landing zone 104A. Here, the term "landing zone" means the area where the wafer can be connected to the via hole. The first dielectric layer 106 is disposed on the first wafer 104. The dielectric encapsulation layer 128 encapsulates the first wafer 104 and the first dielectric layer 106 therein. The first via hole 108 penetrates through the dielectric encapsulation layer 128 and the first dielectric layer 106 . The first via 108 is connected to the first landing zone 104A of the first wafer 104. The semiconductor package structure 100 may further include a redistribution layer 130 disposed on the dielectric encapsulation layer 128. The redistribution layer 130 is connected to the first via hole 108.

The semiconductor package structure 100 can further include a second wafer 110, a second dielectric layer 112, and at least one second via 114. The second wafer 110 is disposed between the substrate 102 and the first wafer 104. The second wafer 110 has a second landing zone 110A that is not covered by the first wafer 104. The second dielectric layer 112 is disposed between the second wafer 110 and the first wafer 104. The dielectric encapsulation layer 128 further encapsulates the second wafer 110 and the second dielectric layer 112 therein. The second via hole 114 penetrates through the dielectric encapsulation layer 128 and the second dielectric layer 112 . The second via 114 is connected to the second landing zone 110A of the second wafer 110. The redistribution layer 130 is further connected to the second via hole 114.

In one embodiment, as shown in FIG. 1, the area of the second landing zone 110A is equal to or smaller than the area of the first landing zone 104A. However, the invention is not limited thereto. As shown in Fig. 2, in the semiconductor package structure 100', the first wafer 104' having a smaller size and the first dielectric layer 106' may be disposed at the uppermost portion. At this time, the area of the second landing zone 110A' may be larger than the area of the first landing zone 104A'. In an embodiment In the first diagram, as shown in FIG. 1, the number of the second guiding holes 114 is equal to or smaller than the number of the first guiding holes 108. However, the invention is not limited thereto. As shown in FIG. 2, the number of second guiding holes 114 may be more than the number of first guiding holes 108. In one embodiment, as shown in FIG. 1, the cross-sectional area A2 of the second via hole 114 is equal to or larger than the cross-sectional area A1 of the first via hole 108. However, the invention is not limited thereto.

The semiconductor package structure 100 further includes a third wafer 116, a third dielectric layer 118, and at least one third via 120. The third wafer 116 is disposed between the substrate 102 and the second wafer 110. The third wafer 116 has a third landing zone 116A that is not covered by the second wafer 110. The third dielectric layer 118 is disposed between the third wafer 116 and the second wafer 110. The dielectric encapsulation layer 128 further encapsulates the third wafer 116 and the third dielectric layer 118 therein. The third via 120 extends through the dielectric encapsulation layer 128 and the third dielectric layer 118 . The third via 120 is connected to the third landing zone 116A of the third wafer 116. The redistribution layer 130 is further connected to the third via hole 120.

In one embodiment, as shown in FIG. 1, the area of the third landing zone 116A is equal to or smaller than the area of the second landing zone 110A. In an embodiment, as shown in FIG. 1, the number of the third via holes 120 is equal to or less than the number of the second via holes 114. In one embodiment, as shown in FIG. 1, the cross-sectional area A3 of the third via hole 120 is equal to or larger than the cross-sectional area A2 of the second via hole 114. However, the invention is not limited thereto.

The semiconductor package structure 100 further includes a fourth wafer 122, a fourth dielectric layer 124, and at least one fourth via 126. The fourth wafer 122 is disposed between the substrate 102 and the third wafer 116. The fourth wafer 122 has a fourth landing zone 122A that is not covered by the third wafer 116. The fourth dielectric layer 124 is disposed between the fourth wafer 122 and the third wafer 116. The dielectric encapsulation layer 128 further includes the fourth wafer 122 and the fourth Dielectric layer 124 is encapsulated therein. The fourth via 126 extends through the dielectric encapsulation layer 128 and the fourth dielectric layer 124. The fourth via 126 is connected to the fourth landing region 122A of the fourth wafer 122. The redistribution layer 130 is further connected to the fourth via hole 126.

In one embodiment, as shown in FIG. 1, the area of the fourth landing zone 122A is equal to or smaller than the area of the third landing zone 116A. In an embodiment, as shown in FIG. 1, the number of fourth via holes 126 is equal to or less than the number of third via holes 120. In one embodiment, as shown in FIG. 1, the cross-sectional area A4 of the fourth via hole 126 is equal to or larger than the cross-sectional area A3 of the third via hole 120. However, the invention is not limited thereto.

According to an embodiment, the redistribution layer 130 may be formed of copper (Cu) or tungsten (W). According to an embodiment, the first via hole 108, the second via hole 114, the third via hole 120, and the fourth via hole 126 may be formed of copper or tungsten. According to an embodiment, the first dielectric layer 106, the second dielectric layer 112, the third dielectric layer 118, and the fourth dielectric layer 124 are formed of a material different from the material of the dielectric encapsulation layer 128. For example, the first dielectric layer 106, the second dielectric layer 112, the third dielectric layer 118, and the fourth dielectric layer 124 may be formed of an oxide, and the dielectric encapsulation layer 128 may be formed of a photosensitive polyimide. .

Referring now to FIGS. 3A-3F, a method of fabricating a semiconductor package structure 100 in accordance with an embodiment is illustrated.

Referring to FIG. 3A, a first wafer 104 is disposed on a substrate 102, and a first dielectric layer 106 is formed on the first wafer 104. The first wafer 104 has a first landing zone 104A. In addition, a second wafer 110 may be disposed between the substrate 102 and the first wafer 104, and a second dielectric layer 112 may be formed between the second wafer 110 and the first wafer 104. The second wafer 110 has no first wafer 104 A second landing zone 110A is covered. A third wafer 116 may be disposed between the substrate 102 and the second wafer 110, and a third dielectric layer 118 may be formed between the third wafer 116 and the second wafer 110. The third wafer 116 has a third landing zone 116A that is not covered by the second wafer 110. A fourth wafer 122 may be disposed between the substrate 102 and the third wafer 116, and a fourth dielectric layer 124 may be formed between the fourth wafer 122 and the third wafer 116. The fourth wafer 122 has a fourth landing zone 122A that is not covered by the third wafer 116. In one embodiment, the first dielectric layer 106, the second dielectric layer 112, the third dielectric layer 118, and the fourth dielectric layer 124 are formed of an oxide.

According to an embodiment, the area of the first landing zone 104A may be equal to or greater than the area of the second landing zone 110A, and the area of the second landing zone 110A may be equal to or greater than the area of the third landing zone 116A, and/or the third landing zone. The area of 116A may be equal to or greater than the area of the fourth landing zone 122A. As a result, a wafer requiring more interconnect structure can be placed at the top and has a larger landing zone.

Referring to FIG. 3B, a dielectric encapsulation layer 128 is formed. The dielectric encapsulation layer 128 encapsulates the first wafer 104 and the first dielectric layer 106 therein. The dielectric encapsulation layer 128 can also encapsulate the second wafer 110, the second dielectric layer 112, the third wafer 116, the third dielectric layer 118, the fourth wafer 122, and the fourth dielectric layer 124 therein. The dielectric encapsulation layer 128 may be formed of a material different from the materials of the first dielectric layer 106, the second dielectric layer 112, the third dielectric layer 118, and the fourth dielectric layer 124. In one embodiment, the dielectric encapsulation layer 128 is formed of a photosensitive polyimide, which is easy to handle and has cost advantages. However, other materials can also be used.

Referring to FIG. 3C, at least one first via O1 is formed through the dielectric encapsulation layer 128. At least one second through hole O2, at least one third through hole O3, and at least one fourth through hole O4 may be formed through the dielectric encapsulation layer 128 at the same time. First perforation O1 The second through hole O2, the third through hole O3, and the fourth through hole O4 correspond to the first landing zone 104A, the second landing zone 110A, the third landing zone 116A, and the fourth landing zone 122A, respectively. The first through hole O1, the second through hole O2, the third through hole O3, and the fourth through hole O4 may be formed by a lithography process. The baking process can be selectively carried out (for photosensitive polyimides, this process is not required).

According to an embodiment, the number of first perforations O1 may be equal to or greater than the number of second perforations O2, the number of second perforations O2 may be equal to or greater than the number of third perforations O3, and/or the number of third perforations O3 It may be equal to or greater than the number of fourth perforations O4. In this way, more vias can be provided to the wafer at the top, requiring more interconnect structure.

According to an embodiment, the cross-sectional area of the first perforation O1 may be equal to or smaller than the cross-sectional area of the second perforation O2, the cross-sectional area of the second perforation O2 may be equal to or smaller than the cross-sectional area of the third perforation O3, and/or the third perforation O3 The cross-sectional area may be equal to or smaller than the cross-sectional area of the fourth perforation O4. Since wafers requiring more interconnect structures can be placed on top, their corresponding via depth can be shallow. As a result, the perforations can have a smaller cross-sectional area and the density of the perforations can be increased. The deeper perforations can have a larger cross-sectional area, so a larger process window can be obtained.

Referring to FIG. 3D, the first via O1 is extended through the first dielectric layer 106 to the first landing region 104A of the first wafer 104. At the same time, the second via O2 can be extended through the second dielectric layer 112 to the second landing region 110A of the second wafer 110. The third via O3 can be extended through the third dielectric layer 118 to the third landing region 116A of the third wafer 116. And extending the fourth through hole O4 through the fourth dielectric layer 124 To the fourth landing zone 122A of the fourth wafer 122. The extended first through hole O1', the second through hole O2', the third through hole O3', and the fourth through hole O4' may be formed by an etching process. The first through hole O1', the second through hole O2', the third through hole O3', and the fourth through hole O4' can be formed in an easier manner than the through hole through hole formed through the base plate, so that the yield does not constitute problem. Moreover, since only one lithography process and one etching process are performed, the cost can be reduced.

Referring to FIG. 3E, a conductor is filled into the first via O1' to form at least one first via 108 connected to the first landing region 104A of the first wafer 104. At the same time, a conductor may be filled into the second through hole O2' to form at least one second via hole 114 connected to the second landing region 110A of the second wafer 110. A conductor may be filled into the third via O3' to form at least one third via 120 connected to the third landing region 116A of the third wafer 116. Also, a conductor may be filled into the fourth via O4' to form at least one fourth via 126 connected to the fourth landing region 122A of the fourth wafer 122. The conductor can be, for example, copper or tungsten.

The number of the first via holes 108 may be equal to or greater than the number of the second via holes 114, and the number of the second via holes 114 may be equal to or greater than the number of the third via holes 120, and/or the number of the third via holes 120. It may be equal to or greater than the number of fourth via holes 126. The cross-sectional area A1 of the first guiding hole 108 may be equal to or smaller than the sectional area A2 of the second guiding hole 114, and the sectional area A2 of the second guiding hole 114 may be equal to or smaller than the sectional area A3 of the third guiding hole 120, and/or the The cross-sectional area A3 of the third via 120 may be equal to or smaller than the cross-sectional area A4 of the fourth via 126.

Since the first via hole 108, the second via hole 114, the third via hole 120, and the fourth via hole 126 can be formed by the same step, the cost is not affected by the number and size of the via holes. In addition, the first guiding hole 108, the second guiding hole 114, and the third guiding hole The cross-sectional area of the 120 and fourth vias 126 may be only about 2 micrometers by 2 micrometers, which is much smaller than the size of the pads generally used in the wire bonding (for example, 60 micrometers by 60 micrometers), so the density of the conductive paths can be greatly improved. .

Referring to FIG. 3F, a redistribution layer 130 can be formed on the dielectric encapsulation layer 128. The redistribution layer 130 is connected to the first via hole 108. The redistribution layer 130 may also be connected to the second via hole 114, the third via hole 120, and the fourth via hole 126. The redistribution layer 130 may be formed of copper or tungsten.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor package structure

102‧‧‧Substrate

104‧‧‧First chip

104A‧‧‧First Landing Area

106‧‧‧First dielectric layer

108‧‧‧First guide hole

110‧‧‧second chip

110A‧‧‧Second landing zone

112‧‧‧Second dielectric layer

114‧‧‧Second guide hole

116‧‧‧ Third chip

116A‧‧‧ Third Landing Area

118‧‧‧ Third dielectric layer

120‧‧‧ third guide hole

122‧‧‧fourth wafer

122A‧‧‧Four Landing Area

124‧‧‧fourth dielectric layer

126‧‧‧4th guide hole

128‧‧‧ Dielectric encapsulation layer

130‧‧‧Re-layer

A1‧‧‧ sectional area

A2‧‧‧ sectional area

A3‧‧‧ sectional area

A4‧‧‧ sectional area

Claims (9)

A semiconductor package structure comprising: a substrate; a first wafer disposed on the substrate, the first wafer having a first landing zone; a first dielectric layer disposed on the first wafer; a dielectric Encapsulating the first wafer and the first dielectric layer; the at least one first via hole extends through the dielectric encapsulation layer and the first dielectric layer, and the at least one first via hole is connected to the a first landing area of the first wafer; a second wafer disposed between the substrate and the first wafer, the second wafer having a second landing area not covered by the first wafer; An electrical layer disposed between the second wafer and the first wafer, the dielectric encapsulation layer encapsulating the second wafer and the second dielectric layer therein; and at least one second via hole extending through the dielectric The at least one second via is connected to the second landing region of the second wafer, and the cross-sectional area of the at least one second via is larger than the at least one first via Section area. The semiconductor package structure of claim 1, further comprising: a redistribution layer disposed on the dielectric encapsulation layer, the redistribution layer being connected to the at least one first via hole. The semiconductor package structure of claim 2, wherein the redistribution layer is further connected to the at least one second via hole. The semiconductor package structure of claim 1, wherein the area of the second landing zone is equal to or smaller than the area of the first landing zone. The semiconductor package structure of claim 1, wherein the at least one The number of the second guiding holes is equal to or less than the number of the at least one first guiding holes. The semiconductor package structure of claim 1, wherein the dielectric encapsulation layer is formed of a photosensitive polyimide. A method of fabricating a semiconductor package structure includes: disposing a second wafer on a substrate; forming a second dielectric layer on the second wafer; and disposing a first wafer on the second dielectric layer; Forming a first dielectric layer on the first wafer, wherein the first wafer has a first landing zone, and the second wafer has a second landing zone not covered by the first wafer; forming a dielectric package a first wafer, the first dielectric layer, the second wafer, and the second dielectric layer are encapsulated therein; forming at least one first via and at least one second via through the dielectric encapsulation layer Extending the at least one first through hole and the at least one second through hole, the at least one first through hole passing through the first dielectric layer to the first landing zone of the first wafer, and the at least one second through hole Passing the second dielectric layer to the second landing region of the second wafer; and filling a conductor into the at least one first via and the at least one second via to form a connection to the first wafer, respectively At least one first via hole of the first landing zone and connected to the second At least one second guide hole of the second landing zone film, wherein the cross-sectional area of the at least a second guide hole is larger than the cross-sectional area of the at least a first guide hole. The method for manufacturing a semiconductor package structure according to claim 7, further comprising: A redistribution layer is formed on the dielectric encapsulation layer, and the redistribution layer is connected to the at least one first via hole. The method of fabricating a semiconductor package structure according to claim 8, wherein the redistribution layer is further connected to the at least one second via hole.