TWI585737B - Driving circuit of active-matrix organic light-emitting diode and display panel having the same - Google Patents

Description

Driving circuit of active matrix organic light emitting diode and display panel thereof

The disclosure relates to the technical field of a liquid crystal display device, and more particularly to a driving circuit of an active matrix organic light emitting diode and a display panel thereof.

The driving matrix of the active matrix organic light emitting diode (AMOLE) pixel can be divided into P-type and N-type driving types according to the backplane process technology. 1 is a conventional 2T1C (two transistors one capacitor) N-type driving transistor pixel circuit, which is combined with an inverted (Inverted) OLED device.

The voltage corresponding to the gate-source voltage (Vgs) of the N-type driving transistor NTFT_dri is the voltage of the data potential and the low potential ELVSS. The low potential ELVSS is a fixed relatively low potential and does not change with time. For the conventional N-type drive transistor NTFt_dri, it has a phenomenon of driving the threshold voltage deviation of the transistor. That is, the threshold voltage (Vt) of the N-type driving transistor is likely to cause regional Vt variation due to the polycrystalline crystallization process. That is, for two N-type driving transistors of the same size, when the same driving voltage is input, the same current cannot be output, resulting in uneven brightness (mura) or poor uniformity. Therefore, the conventional pixel circuit still has room for improvement.

The purpose of the disclosure is mainly to provide a driving circuit of an active matrix organic light emitting diode and a display panel thereof, which use a polycrystalline germanium transistor in the light emitting electric crystal system. The polycrystalline germanium transistor provides a large current when turned on, and has a large driving capability to drive an organic light emitting diode. Simultaneously driving the transistor to use an oxide semiconductor transistor to provide a lower leakage current, thereby eliminating the voltage variation at the control terminal of the driving transistor on the driving current path, thereby enabling the driving transistor to provide a stable driving current to An organic light-emitting diode can improve the brightness unevenness (mura) or poor uniformity of the prior art. At the same time, the present disclosure proposes a stack-up structure of a transistor-shared gate, which can effectively save the area of the circuit layout.

According to one feature of the disclosure, the present disclosure provides a driving circuit for an active matrix organic light emitting diode, comprising a data writing transistor, a driving transistor, a first storage capacitor, a light emitting transistor, and a second Storage capacitors. The data writing transistor has a first control terminal connected to a first control signal, a first terminal connected to a data line, and a second terminal. The driving transistor has a second control end connected to the second end, a third end, and a fourth end. The first storage capacitor is connected to the second control end and the fourth end. The illuminating transistor has a third control terminal connected to a second control signal, a fifth terminal connected to a high potential, and a sixth end connected to the third terminal. The second storage capacitor is coupled to the fifth end and the fourth end, and is coupled to an organic light emitting diode element by the fourth end.

According to another feature of the present disclosure, the present disclosure provides a display panel, which is an organic light emitting diode display panel having a plurality of active matrix organic light emitting diode driving circuits, and the active matrix organic light emitting diodes The driving circuit of the polar body comprises a data writing transistor, a driving transistor, a first storage capacitor, a light emitting transistor, and a second storage capacitor. The data writing transistor has a first control terminal connected to a first control signal, a first terminal connected to a data line, and a first Second end. The driving transistor has a second control end connected to the second end, a third end, and a fourth end. The first storage capacitor is connected to the second control end and the fourth end. The illuminating transistor has a third control terminal connected to a second control signal, a fifth terminal connected to a high potential, and a sixth end connected to the third terminal. The second storage capacitor is coupled to the fifth end and the fourth end, and is coupled to an organic light emitting diode element by the fourth end.

NTFT_dri‧‧‧ drive transistor

ELVSS‧‧‧ low potential

100‧‧‧ display panel

Driving circuit of 200‧‧‧ active matrix organic light emitting diode

(T2) ‧‧‧data writing to the transistor

(T1)‧‧‧ drive transistor

(Cst)‧‧‧First storage capacitor

(T4)‧‧‧Lighting crystal

(C1)‧‧‧Second storage capacitor

(T3) ‧‧‧Reset the transistor

(D1)‧‧‧Organic Luminescent Diodes

(c1) ‧ ‧ first control end

(a1) ‧ ‧ first end

(b1)‧‧‧second end

(c2) ‧‧‧second control end

(a2) ‧ ‧ third end

(b2) ‧ ‧ fourth end

(c3) ‧‧‧ third console

(a3) ‧ ‧ fifth end

(b3) ‧ ‧ sixth end

(c4) ‧‧‧ fourth console

(a4) ‧ ‧ seventh end

(b4) ‧ ‧ eighth end

(ELVDD)‧‧‧High potential

(ELVSS)‧‧‧Low potential

(Sn)‧‧‧First control signal

(En)‧‧‧second control signal

(RST)‧‧‧Reset signal

(Vini) ‧ ‧ initial signal

(Data) ‧ ‧ data line

(Vrei)‧‧‧ reference potential

(Voled) ‧ ‧ anode voltage

(Vdata) ‧ ‧ data write potential

(T5)‧‧‧Compensation transistor

(c5) ‧‧‧ fifth console

(a5) ‧ ‧ ninth end

(b5) ‧ ‧ tenth end

(T4')‧‧‧Optoelectronics

(c6) ‧‧‧ sixth console

(a6) ‧ ‧ eleventh end

(b6) ‧ ‧ twelfth

(C2)‧‧‧First storage capacitor

(Sn[n])‧‧‧First control signal

(Sn[n+3])‧‧‧second control signal

(En[n])‧‧‧ third control signal

(Vref)‧‧‧ reference potential

(VSS) ‧ ‧ control low potential

(VDD)‧‧‧Control high potential

(T4)‧‧‧First illuminating transistor

(T6)‧‧‧Second light-emitting transistor

(C)‧‧‧First storage capacitor

X‧‧‧ node

Y‧‧‧ node

W‧‧‧ node

(tft6)‧‧‧data writing to the transistor

(tft1)‧‧‧ drive transistor

(Cst)‧‧‧First storage capacitor

(tft4)‧‧‧First illuminating transistor

(tft5)‧‧‧Compensated transistor

(tft2)‧‧‧Reset the transistor

(tft3)‧‧‧second illuminating transistor

(PVDD) ‧ ‧ high potential

(G2)‧‧‧First control signal

(EMIT) ‧ ‧ second control signal

(VI) ‧ ‧ third control signal

(G1)‧‧‧fourth control signal

(XEMIT)‧‧‧First Control Signal

(PVDD) ‧ ‧ high potential

(EMIT) ‧ ‧ second control signal

(VREF)‧‧‧ reference potential

(G1)‧‧‧ Third control signal

(PVEE)‧‧‧ Low potential

FIG. 1 is a schematic diagram of a pixel circuit of a conventional 2T1C P-type driving transistor.

2 is a schematic view of a display panel of the present disclosure.

3 is a circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

4a to 4d are timing diagrams of the driving circuit of the active matrix organic light emitting diode of the present disclosure.

Figure 5 is a schematic illustration of currents of polycrystalline germanium transistors, oxide semiconductor transistors, and amorphous germanium transistors during turn-on and turn-off.

FIG. 6 is a schematic diagram showing the simulation of the driving circuit of the active matrix organic light emitting diode.

FIG. 7 is a schematic diagram showing simulation results of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 8 is a schematic diagram showing simulation results of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 9 is a schematic diagram of an application of the driving circuit of the active matrix organic light emitting diode of FIG. 3 .

FIG. 10 is another schematic diagram of the application of the driving circuit of the active matrix organic light emitting diode of FIG. 3 .

FIG. 11 is a schematic diagram of still another application of the driving circuit of the active matrix organic light emitting diode of FIG.

FIG. 12 is another circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 13 is a schematic diagram of an application of the driving circuit of the active matrix organic light emitting diode of FIG. 12 .

FIG. 14 is another schematic diagram of the application of the driving circuit of the active matrix organic light emitting diode of FIG.

FIG. 15 is a schematic diagram of still another application of the driving circuit of the active matrix organic light emitting diode of FIG.

FIG. 16 is still another circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 17 is a schematic diagram of an application of the driving circuit of the active matrix organic light emitting diode of FIG. 16 .

FIG. 18 is another schematic diagram of the application of the driving circuit of the active matrix organic light emitting diode of FIG. 16 .

FIG. 19 is a schematic diagram of still another application of the driving circuit of the active matrix organic light emitting diode of FIG. 16 .

20a to 20d are timing diagrams of driving circuits of the active matrix organic light emitting diode of the present disclosure.

FIG. 21 is a schematic diagram of the compensation of the current of the organic light emitting diode element by the compensation transistor.

FIG. 22 is still another circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 23 is a schematic diagram showing one application of the driving circuit of the active matrix organic light emitting diode of FIG. 22 .

FIG. 24 is another schematic diagram of the application of the driving circuit of the active matrix organic light emitting diode of FIG. 22.

FIG. 25 is a schematic diagram of still another application of the driving circuit of the active matrix organic light emitting diode of FIG. 22.

FIG. 26 is a further circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 27 is a schematic diagram of an application of the driving circuit of the active matrix organic light emitting diode of FIG. 26 .

FIG. 28 is another schematic diagram of the application of the driving circuit of the active matrix organic light emitting diode of FIG. 26.

FIG. 29 is still another schematic diagram of the application of the driving circuit of the active matrix organic light emitting diode of FIG. 26 .

FIG. 30 is a further circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 31 is a timing diagram of a driving circuit of the active matrix organic light emitting diode of FIG. 30.

32 is a further circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 33 is still another circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 34 is a further circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

FIG. 35 is a timing diagram of a driving circuit of the active matrix organic light emitting diode of FIG. 34.

FIG. 36 is a further circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

37a to 37c are timing diagrams showing the driving circuit of the active matrix organic light emitting diode of FIG. 36.

38 is a further circuit diagram of a driving circuit of an active matrix organic light emitting diode according to the present disclosure.

39a to 39c are timing diagrams showing the driving circuit of the active matrix organic light emitting diode of FIG. 38.

2 is a schematic view of a display panel of the present disclosure. The display panel 100 is an organic light emitting diode display panel having a plurality of driving circuits 200 of active matrix organic light emitting diodes. The driving circuit 200 of the active matrix organic light emitting diodes is used to drive one of the organic layers. The LED component is shown for display, as shown in FIG. 3 is a circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode. 3 is a circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. As shown in FIG. 3, the driving circuit 200 includes a data writing transistor (T2) and a driving transistor (T1). a first storage capacitor (Cst), a light-emitting transistor (T4), a second storage capacitor (C1), and a reset transistor (T3) for driving an organic light-emitting diode (D1) .

The data writing transistor (T2) has a first control terminal (c1) connected to a first control signal (Sn), a first terminal (a1) connected to a data line (Data), and a second terminal (b1) ). The driving transistor (T1) has a second control terminal (c2) connected to the second terminal (b1), a third terminal (a2), and a fourth terminal (b2). The first storage capacitor (Cst) is connected to the second control terminal (c2) and the fourth terminal (b2).

The light-emitting transistor (T4) has a third control terminal (c3) connected to a second control signal (En), a fifth terminal (a3) connected to a high potential (ELVDD), and a sixth terminal (b3) Connected to the third end (a2). The second storage capacitor (C1) is coupled to the fifth end (a3) and the fourth end (b2), and is coupled to an organic light emitting diode element (D1) by the fourth end (b2). The reset transistor (T3) has a fourth control terminal (c4) connected to a reset signal (RST), a seventh terminal (a4) connected to an initial signal (Vini), and an eighth terminal (b4) connection. To the fourth end (b2). An anode terminal of the organic light emitting diode element (D1) is coupled to the fourth terminal (b2), and a cathode terminal thereof is connected to a low potential (ELVSS).

4a to 4d are timing diagrams of the driving circuit 200 of the active matrix organic light emitting diode of the present disclosure. During a pre-charge period, the reset signal (RST), the first control signal (Sn), and the second control signal (En) are a control high potential (VDD), a data line ( The voltage of Data) is a reference potential (Vref). The voltage level of the control high potential (VDD) may be the same as the voltage level of the high potential (ELVDD), or may be different from the voltage level of the high potential (ELVDD). The voltage level of the reference potential (Vref) may be the same as the voltage level of the high potential (ELVDD), or may be different from the voltage level of the high potential (ELVDD).

As shown in FIG. 4a, during the pre-charge period, the data is written into the transistor (T2), the driving transistor (T1), the illuminating transistor (T4), and the reset transistor. (T3) is turned on, and the data line (Data) is a reference potential (Vref), so the voltage on the node G is Vref, and the voltage on the node S is Vini.

During a compensation period, the first control signal (Sn) and the second control signal (En) are control high potential (VDD), and the reset signal (RST) is a control low potential (VSS), data line The voltage of (Data) is the reference potential (Vref). The voltage level of the control low potential (VSS) may be the same as the voltage level of the low potential ELVSS, or may be different from the voltage level of the low potential ELVSS.

As shown in FIG. 4b, during the compensation period, the data writing transistor (T2), the driving transistor (T1), and the illuminating transistor (T4) are turned on, and the reset transistor (T3) is Closed, the data line (Data) is a reference potential (Vref), so the voltage on node G is Vref, and the voltage on node S is Vref-Vt, where Vt is the threshold voltage of the driving transistor (T1) ( Threshold voltage, Vt).

During a data writing cycle, the first control signal (Sn) is the control high potential (VDD), the second control signal (En) and the reset signal (RST) are the control low potential (VSS), data. The voltage of the line is a data write potential (Vdata).

As shown in FIG. 4c, during the data writing period, the data is written into the transistor (T2), the driving transistor (T1) is turned on, and the light-emitting transistor (T4) and the reset transistor (T3) are turned on. The system is turned off, the data line (Data) is the data write potential (Vdata), so the voltage on node G is Vdata, and the voltage on node S is Vref-Vt+f(Vdata-Vref), where f is Cst/ (Cst+C1), Cst is the capacitance value of the first storage capacitor (Cst), and C1 is the capacitance value of the second storage capacitor (C1).

During an Emitting cycle, the second control signal (En) is a control high potential (VDD), and the first control signal (Sn) and the reset signal (RST) are control low (VSS).

As shown in FIG. 4d, during the illumination period, the driving transistor (T1) and the illuminating transistor (T4) are turned on, and the data writing transistor (T2) and the reset transistor (T3) are turned off. Therefore, the voltage on the node G is Vdata+Voled-[Vref-Vt+f(Vdata-Vref)], and the voltage on the node S is Voled, where Voled is the anode voltage of the organic light emitting diode element (D1) . Since the voltage on the node G has a threshold voltage (Vt), it is possible to compensate for the Vt variation of the region caused by the polycrystalline crystallization process and compensate for the voltage of the organic light-emitting diode during the light-emitting period. The organic light-emitting diode element (D1) has uniform brightness and solves the problem of conventional brightness mura.

Fig. 5 is a schematic view showing currents of a polycrystalline germanium transistor, an oxide semiconductor transistor, and an amorphous germanium (a-Si) transistor when turned on and off. As shown in FIG. 5, the polycrystalline germanium transistor has a large current when it is turned on, and the leakage current of the oxide semiconductor transistor when it is turned off is much smaller than that of the polycrystalline germanium transistor and the amorphous germanium (a-Si) transistor. Therefore, in an embodiment, the threshold voltage (Vt) of the driving transistor (T1) needs to have better uniformity, and the data writing transistor (T2) requires less leakage current, thus driving the transistor. (T1), and the data writing transistor (T2) may be an oxide semiconductor transistor. The oxide semiconductor transistor may be an indium gallium zinc oxide (IGZO) transistor. The illuminating transistor (T4) needs to have better electron mobility (Electron Mobility) and stability, so the illuminating transistor (T4) can be a polycrystalline germanium transistor. The polycrystalline germanium transistor can be a low temperature polycrystalline germanium (LTPS) transistor. The reset transistor (T3) can be a polysilicon transistor to reduce the area of the circuit layout.

FIG. 6 is a schematic diagram showing the driving circuit 200 of the active matrix organic light emitting diode according to the present disclosure. The analog driving circuit 200 drives the currents of the transistor (T1) and the light emitting transistor (T4) during the light emitting period. The upper half of FIG. 6 is a current when the driving transistor (T1) and the light-emitting transistor (T4) are both oxide semiconductor transistors, and the lower half of FIG. 6 is a driving semiconductor (T1) which is an oxide semiconductor transistor. The current when the light-emitting transistor (T4) is a polycrystalline germanium transistor.

During the illumination period, the current driving the transistor (T1) controls the current on the organic light-emitting diode element (D1), and the light-emitting transistor (T4) controls the light-emitting time of the organic light-emitting diode element (D1). Therefore, it is necessary to ensure that the current of the light-emitting transistor (T4) is larger than the current of the driving transistor (T1). As can be seen from Fig. 6, when the polycrystalline germanium transistor is used for the light-emitting transistor (T4), the driving current is 80 nA, and when the light-emitting transistor (T4) is an oxide semiconductor transistor, the driving current is 43 nA. Therefore, the illuminating transistor (T4) needs to have better electron mobility (Electron Mobility) and stability, so the illuminating transistor (T4) can be a polycrystalline germanium transistor. The threshold voltage (Vt) of the driving transistor (T1) needs to have a good uniformity, so the driving transistor (T1) is preferably an oxide semiconductor transistor.

FIG. 7 is a schematic diagram showing simulation results of the driving circuit 200 of the active matrix organic light emitting diode. It is a schematic diagram of the simulation results of data writing into the transistor (T2) and resetting the transistor (T3) as the basis for selecting the data to be written into the transistor (T2) and resetting the transistor (T3). As shown in FIG. 7, VGS represents the gate and source voltages of the driving transistor (T1), and VGS peak to peak represents the VGS voltage difference of each frame. As shown in FIG. 7, when Vdata is 0.3 volt (V) and the write transistor (T2) is a polycrystalline germanium transistor, VGS peak to peak is 108.78 mV, and when the write transistor (T2) is an oxide semiconductor transistor, , VGS peak to peak is 16.123mV. When Vdata is 2 volts (V) and the write transistor (T2) is a polycrystalline germanium transistor, VGS peak to peak is 87.84 mV, and when the write transistor (T2) is an oxide semiconductor transistor, VGS peak to peak is 8.1521mV. Therefore, it is understood that when the write transistor (T2) is an oxide semiconductor transistor, it has a good VGS peak to peak stability.

As shown in FIG. 7, the reset transistor (T3) is a polycrystalline germanium transistor or an oxide semiconductor transistor, and there is no significant difference for VGS peak to peak.

FIG. 8 is a schematic diagram showing simulation results of the driving circuit 200 of the active matrix organic light emitting diode. It is a schematic diagram of the simulation results of data writing into the transistor (T2), which is used as the basis for selecting the data to be written into the transistor (T2). As shown in FIG. 8, when Vdata is 0.3 volt (V) and the write transistor (T2) is a polysilicon transistor, the pre-charge time is 5.0129 microseconds (μs), and the transistor is written ( When T2) is an oxide semiconductor transistor, the precharge time is 12.9464 microseconds (μs). Therefore, in another embodiment, the driving transistor (T1) may be an oxide semiconductor transistor. The illuminating transistor (T4) needs to have better electron mobility (Electron Mobility) and stability, so the illuminating transistor (T4) can be a polycrystalline germanium transistor. The reset transistor (T3) can be a polysilicon transistor to reduce the area of the circuit layout. The data write transistor (T2) is a polysilicon transistor to reduce the precharge time.

FIG. 9 is a schematic diagram of an application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 3, wherein the reset transistor (T3) of the driving circuit 200 is shared with another driving circuit, and the two driving The circuit has the same architecture, and the reset transistor (T3) is an oxide semiconductor transistor. As shown in FIG. 9, the reset transistor (T3) is shared by the driving circuit of the sub-pixel A and the driving circuit of the sub-pixel B, and the number of transistors can be greatly reduced. For example, when applied to a high-resolution panel, the FHD panel is taken as an example, which has 1080×1920×3=6220800 sub-pixels, so 6,220,800 drive circuits are required. According to the technique disclosed in the present invention, since two driving circuits can save one transistor, it can save 3,110,400 transistors.

FIG. 10 is a schematic diagram of another application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 3, wherein the reset transistor (T3) of the driving circuit 200 is shared with another driving circuit, and the second The drive circuit has the same architecture. As shown in FIG. 10, the material writing transistor (T2) of the sub-pixel A driving circuit is a P-type polycrystalline germanium transistor, and the data writing transistor (T2) of the sub-pixel B driving circuit is an N-type oxide. Semiconductor transistor. The data of the driving circuit of the sub-pixel A is written into the transistor (T2) and the sub-pixel B. The data write transistor (T2) of the drive circuit is controlled by the same first control signal (Sn). The light-emitting transistor (T4) of the driving circuit of the sub-pixel A and the driving circuit of the sub-pixel B may be a P-type polycrystalline germanium transistor or an N-type polycrystalline germanium transistor, wherein the driving circuit of the sub-pixel A and the sub-pixel B The light-emitting transistor (T4) of the driving circuit may be a P-type polycrystalline germanium transistor.

FIG. 11 is a schematic diagram of still another application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 3, wherein the reset transistor (T3) of the driving circuit 200 is shared with another driving circuit, and the second The drive circuit has the same architecture. The light-emitting transistor (T4) of the two driving circuit is a P-type polycrystalline silicon transistor, and the driving transistor (T1) of the two driving circuits is an N-type oxide semiconductor transistor.

As shown in FIG. 11, the driving circuit of the sub-pixel A and the light-emitting transistor (T4) of the driving circuit of the sub-pixel B are P-type polycrystalline germanium transistors, the driving circuit of the sub-pixel A and the driving circuit of the sub-pixel B. The illuminating transistor (T4) is a driving transistor (T1) which is an N-type oxide semiconductor transistor. The data writing transistor (T2) of the driving circuit of the sub-pixel A is a P-type polycrystalline germanium transistor, and the data writing transistor (T2) of the driving circuit of the sub-pixel B is an N-type oxide semiconductor transistor. The data writing circuit (T2) of the data of the driving circuit of the sub-picture A is written by the same first control signal (Sn).

As shown in FIG. 11, the data of the driving circuit of the sub-pixel A is written into the transistor (T2) as a bottom gate structure, and the data of the driving circuit of the sub-pixel B is written into the transistor (T2). ) is a top gate structure. The data of the driving circuit of the sub-pixel A is written into the data-transisting transistor (T2) common-shared gate of the driving circuit of the transistor (T2) and the sub-pixel B, as shown in FIG. Since the data of the driving circuit of the sub-pixel A is written to the transistor (T2) and the data of the driving circuit of the sub-pixel B is written to the transistor (T2) sharing gate (GE), when the circuit layout is performed, The data of the driving circuit of the sub-pixel A is written into the driving circuit of the transistor (T2) and the sub-pixel B. The data writing transistor (T2) has a stack-up structure, which can effectively save the circuit layout. The area of (layout).

FIG. 12 is another circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. The main difference from FIG. 3 is the addition of a compensation transistor (T5). The compensation transistor (T5) has a fifth control terminal (c5) connected to a sensed compensation signal (compensated/sensing), a ninth terminal (a5) connected to a compensated/sensing line, and A tenth end (b5) is connected to the fourth end (b2). For the connection of the remaining components, refer to the connection mode of the components in FIG. 3, and details are not described herein again.

As shown in FIG. 12, the light-emitting transistor (T4) may be a polycrystalline germanium transistor. The driving transistor (T1) may be an oxide semiconductor transistor. The data writing transistor (T2), the resetting transistor (T3), and the compensation transistor (T5) may be an oxide semiconductor transistor or a polycrystalline germanium transistor.

FIG. 13 is a schematic diagram of an application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. It is similar to FIG. 12, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is a P-type transistor, and the compensation transistor (T5) is an N-type transistor.

FIG. 14 is another schematic diagram of the application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. It is similar to FIG. 12, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is an N-type transistor, and the compensation transistor (T5) is a P-type transistor.

FIG. 15 is a schematic diagram of still another application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. It is similar to FIG. 12 but removes the compensation/sensing and connects the fifth control terminal (c5) of the compensation transistor (T5) to the first control signal (Sn).

FIG. 16 is still another circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. The main difference from FIG. 12 is that the compensation transistor (T5) has a fifth control terminal (c5) connected to a sensed compensation signal (compensated/sensing), and a ninth terminal (a5) connected to the fourth terminal (b2). And a tenth end (b5) is connected to the data line (Data). For the connection of the remaining components, refer to the connection mode of the components in FIG. 12, and details are not described herein again.

FIG. 17 is a schematic diagram of an application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 16 . It is similar to FIG. 16, but the compensation/sensing signal is removed and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is a P-type transistor, and the compensation transistor (T5) is an N-type transistor.

FIG. 18 is another schematic diagram of the application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 16 . It is similar to FIG. 16, but the compensation/sensing signal is removed and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is an N-type transistor, and the compensation transistor (T5) is a P-type transistor.

FIG. 19 is a schematic diagram of still another application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 16 . It is similar to Figure 16, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the first control signal (Sn).

20a to 20d are timing diagrams of the driving circuit 200 of the active matrix organic light emitting diode of the present disclosure. It is a timing diagram corresponding to the operation of the circuit of FIG. The working principle and the voltage of each node are similar to those of FIG. 4a to FIG. 4d, and are not described herein again.

The compensation transistor (T5) mainly compensates the current of the organic light emitting diode element (D1). The compensation time is not in any of the pre-charge period, the compensation period, the data writing period, and the emitting period in FIG. The current of the organic light emitting diode element (D1) is sensed/compensated when a panel is turned on. Figure 21 is a schematic diagram of the compensation of the current of the organic light-emitting diode element (D1) by the compensation transistor (T5). The circuit in FIGS. 12 and 15 is taken as an example. First, the driving transistor (T1), the data writing transistor (T2), the resetting transistor (T3), and the light-emitting transistor (T4) are turned off, and the compensation transistor (T5) is turned on, at this time an external A sensing device (not shown) senses a current flowing through the organic light emitting diode element (D1) to determine a magnitude of the compensation current and calculates a corresponding voltage Vgs5. At the time of compensation, the voltage Vgs5 is applied via a sensing compensation signal (compensated/sensing) to the fifth control terminal (c5) of the compensation transistor (T5) to compensate the organic light emitting diode element. (D1) current. 21 is an example of the circuit of FIG. 12 and FIG. 15, and the current compensation principle of the organic light-emitting diode element (D1) of other circuits is similar, and will not be described again.

FIG. 22 is still another circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. The main difference from FIG. 3 is the addition of a compensation transistor (T5) and a transistor (T4'). The compensation transistor (T5) has a fifth control terminal (c5) connected to a sensed compensation signal (compensated/sensing), a ninth terminal (a5) connected to a compensated/sensing line, and A tenth end (b5) is connected to the organic light emitting diode element (D1). The transistor (T4') has a sixth control terminal (c6) connected to the second control signal (En), and a tenth end (a6) connected to the fourth terminal (b2), a twelfth end (b6) is connected to the tenth end (b5) and the organic light emitting diode element (D1). For the connection of the remaining components, refer to the connection mode of the components in FIG. 3, and details are not described herein again.

As shown in Fig. 22, the light-emitting transistor (T4) and the transistor (T4') may be polycrystalline germanium transistors. The driving transistor (T1) may be an oxide semiconductor transistor. The data writing transistor (T2), the resetting transistor (T3), and the compensation transistor (T5) may be an oxide semiconductor transistor or a polycrystalline germanium transistor.

FIG. 23 is a schematic diagram of an application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 22 . It is similar to FIG. 22 except that the sensing/sensing signal is removed and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is a P-type transistor, and the compensation transistor (T5) is an N-type transistor.

FIG. 24 is another schematic diagram of the application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 22 . It is similar to FIG. 22 except that the sensing/sensing signal is removed and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is an N-type transistor, and the compensation transistor (T5) is a P-type transistor.

FIG. 25 is a schematic diagram of still another application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 22 . It is similar to FIG. 22, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the first control signal (Sn).

FIG. 26 is a further circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. The main difference from FIG. 3 is the addition of a compensation transistor (T5) and a transistor (T4'). The compensation transistor (T5) has a fifth control terminal (c5) connected to a sensed compensation signal (compensated/sensing), a ninth terminal (a5), and a tenth terminal (b5) connected to the data line (Data). ). The transistor (T4') has a sixth control terminal (c6) connected to the second control signal (En), and a tenth end (a6) connected to the fourth terminal (b2) and a twelfth end ( B6) is connected to the ninth terminal (a5) and the organic light emitting diode element (D1). For the connection of the remaining components, refer to the connection mode of the components in FIG. 3, and details are not described herein again.

As shown in Fig. 26, the light-emitting transistor (T4) and the transistor (T4') may be polycrystalline germanium transistors. The driving transistor (T1) may be an oxide semiconductor transistor. The data writing transistor (T2), the resetting transistor (T3), and the compensation transistor (T5) may be an oxide semiconductor transistor or a polycrystalline germanium transistor.

FIG. 27 is a schematic diagram of an application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 26 . It is similar to FIG. 26, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is a P-type transistor, and the compensation transistor (T5) is an N-type transistor.

FIG. 28 is another schematic diagram of the application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. It is similar to FIG. 26, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the second control signal (En). At this time, the light-emitting transistor (T4) is an N-type transistor, and the compensation transistor (T5) is a P-type transistor.

FIG. 29 is still another schematic diagram of the application of the driving circuit 200 of the active matrix organic light emitting diode of FIG. It is similar to FIG. 26, but with the compensation/sensing removed, and the fifth control terminal (c5) of the compensation transistor (T5) is connected to the first control signal (Sn).

FIG. 30 is a further circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. As shown in FIG. 30, the driving circuit 200 includes a data writing transistor (T2) and a driving transistor (T1). ), a first storage capacitor (C2), a light-emitting transistor (T4), a compensation transistor (T5), A second storage capacitor (C1) and a reset transistor (T3) are used to drive an organic light emitting diode (D1).

The data writing transistor (T2) has a first control terminal (c1) connected to a first control signal (Sn[n]), a first terminal (a1) connected to a data line (Data), and a second End (b1). The driving transistor (T1) has a second control terminal (c2) connected to the second terminal (b1), a third terminal (a2) connected to a high potential (ELVDD), and a fourth terminal (b2) . One end of the second storage capacitor (C1) is connected to the second control end (c2) and the second end (b1).

The light-emitting transistor (T4) has a third control terminal (c3) connected to a second control signal (Sn[n+3]), and a fifth terminal (a3) connected to the second control terminal (c2) and The second end (b1) and a sixth end (b3) are connected to the other end of the second storage capacitor (C1). The compensation transistor (T5) has a fifth control terminal (c5) connected to a third control signal (En[n]), a ninth terminal (a5) connected to a reference potential (Vref), and a tenth The terminal (b5) is connected to the sixth end (b3) and one end of the first storage capacitor (C2). The other end of the first storage capacitor (C2) is connected to the fourth end (b2) and the organic light emitting diode (D1).

The reset transistor (T3) has a fourth control terminal (c4) connected to the first control signal (Sn[n]), a seventh terminal (a4) connected to an initial signal (Vini), and a first An eight end (b4) is connected to the fourth end (b2). An anode terminal of the organic light emitting diode element (D1) is coupled to the fourth terminal (b2), and a cathode terminal thereof is connected to a low potential (ELVSS).

FIG. 31 is a timing diagram of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 30. As shown in FIG. 31, during the pre-charge period, the first control signal (Sn[n]) and the third control signal (En[n]) are control high potentials (VDD), and the second control The signal (Sn[n+3]) is a control low potential (VSS), and therefore, the data is written into the transistor (T2), the driving transistor (T1), the compensation transistor (T5), and the resetting power. The crystal (T3) is turned on, the light-emitting transistor (T4) is turned off, and the data line (Data) is a data write potential (Vdata), so the voltage on the node G is Vdata, and the voltage on the node S is Vini. The voltage on node W is the reference potential (Vref).

During a compensation period, the first control signal (Sn[n]) and the second control signal (Sn[n+3]) are control low (VSS), and the third control signal (En[n]) In order to control the high potential (VDD), the driving transistor (T1) and the compensation transistor (T5) are turned on, and the data is written into the transistor (T2), the reset transistor (T3), and the light-emitting device. The crystal (T4) is off, so the voltage on node G is Vdata, the voltage on node S is Vdata-Vt, and the voltage on node W is the reference potential (Vref).

During an Emitting cycle, the first control signal (Sn[n]) and the third control signal (En[n]) are control low (VSS), and the second control signal (Sn[n+3]) In order to control the high potential (VDD), the driving transistor (T1) and the light-emitting transistor (T4) are turned on, and the data is written into the transistor (T2), the reset transistor (T3), and the compensation power. The crystal (T5) is turned off, so the voltage on node G is Vref+[Voled-(Vdata-Vt)], the voltage on node S is Voled, and the voltage on node W is the reference potential (Vref). As shown in FIG. 4, during the illumination period, since the voltage on the node G has a threshold voltage (Vt), the Vt variation due to the regionality caused by the polycrystalline crystallization process can be compensated during the illumination period. The organic light-emitting diode element (D1) has uniform brightness, which solves the problem of conventional brightness mura.

In one embodiment, the driving transistor (T1) of FIG. 30 may be an oxide semiconductor transistor to have a better uniformity of the threshold voltage (Vt) of the driving transistor (T1). The luminescent transistor (T4) is a polycrystalline germanium transistor, which has better electron mobility and stability. The reset transistor (T3) is a polysilicon transistor to reduce the area of the circuit layout. The data writing transistor (T2) and the compensation transistor (T5) may be polycrystalline germanium transistors or oxide semiconductor transistors.

In another embodiment, the driving transistor (T1) of FIG. 30 may be an oxide semiconductor transistor to have a better uniformity of the threshold voltage (Vt) of the driving transistor (T1). The luminescent transistor (T4) is a polycrystalline germanium transistor, which has better electron mobility and stability. The reset transistor (T3) is a polysilicon transistor to reduce the area of the circuit layout. data The write transistor (T2) is a polysilicon transistor to reduce the precharge time. The compensation transistor (T5) may be a polycrystalline germanium transistor or an oxide semiconductor transistor.

32 is a further circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. As shown in FIG. 32, the driving circuit 200 includes a switching transistor (PTFT_sw), a driving transistor (PTFT_dri), a first storage capacitor (Cst), and a compensation transistor (NTFT_comp) for driving. An organic light emitting diode (D1).

With the driving circuit 200 of FIG. 32, first, in a step (A), the scanning line (Scan/Scan2) is controlled to be low (VSS), the switching transistor (PTFT_sw) is turned on, the driving transistor (PTFT_dri) and a compensation are performed. The transistor (NTFT_comp) is turned off, and the voltage on the data line charges the first storage capacitor (Cst).

In a step (B), the scan line (Scan/Scan2) is controlled to a high potential (VDD), the switching transistor (PTFT_sw) is turned off, the driving transistor (PTFT_dri) and a compensation transistor (NTFT_comp) are turned on, and a high potential (ELVDD) drives an organic light emitting diode (D1) via a driving transistor (PTFT_dri). At this time, the compensation transistor (NTFT_comp) is turned on, and the compensation line (Compensate) can compensate the current of the organic light-emitting diode element (D1) via the compensation transistor (NTFT_comp).

The operation principle of the compensation transistor (NTFT_comp) is similar to that of FIG. 21. It senses/compensates the current of the organic light emitting diode element (D1) when a panel is turned on. First, the switching transistor (PTFT_sw) is turned off and the driving transistor (PTFT_dri) is turned off, and the compensation transistor (NTFT_comp) is turned on. At this time, an external sensing device (not shown) senses the flow through the organic light emitting diode. The current of the component (D1) determines the magnitude of the compensation current and calculates the corresponding voltage Vgs. At the time of compensation, a voltage Vgs is applied via a scan line (Scan/Scan 2) to a control terminal (c) of the compensation transistor (NTFT_comp), and the current of the compensation line (Compensate) can be compensated for by the compensation transistor (NTFT_comp). Current of the diode element (D1).

In FIG. 32, the switching transistor (PTFT_sw) may be a P-type polysilicon transistor, the compensation transistor (NTFT_comp) may be an N-type oxide semiconductor transistor, and the driving transistor (PTFT_dri) may be more A germanium transistor or an oxide semiconductor transistor. As shown in FIG. 32, the compensation transistor (NTFT_comp) is a bottom gate structure, and the switching transistor (PTFT_sw) is a top gate structure. And the compensation transistor (NTFT_comp) and the switching transistor (PTFT_sw) share a common-shared gate, that is, the compensation transistor (NTFT_comp) and the switching transistor (PTFT_sw) share a gate (GE). Therefore, in the circuit layout, the compensation transistor (NTFT_comp) and the switching transistor (PTFT_sw) have a stack-up structure, which can effectively save the area of the circuit layout.

FIG. 33 is still another circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. The difference from FIG. 32 is that the switching transistor (NTFT_sw) is an N-type oxide semiconductor transistor, and the compensation transistor (PTFT_comp) is a P-type polycrystalline silicon transistor.

FIG. 34 is a further circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. As shown in FIG. 34, the driving circuit 200 includes a data writing transistor (T2) and a driving transistor (T1). a first storage capacitor (C), a first illuminating transistor (T4), a compensating transistor (T5), a reset transistor (T3), and a second illuminating transistor (T6), It is used to drive an organic light-emitting diode (D1).

The data writing transistor (T2) has a first control terminal (c1) connected to a first control signal (SCAN1), a first terminal (a1) connected to a data line (Data), and a second terminal (b1) ). The driving transistor (T1) has a second control terminal (c2) connected to one end of the first storage capacitor (C), a third end (a2), and a fourth end (b2) connected to the second end (b1).

The first light-emitting transistor (T4) has a third control terminal (c3) connected to a second control signal (EM1), a fifth terminal (a3) connected to a high potential (ELVDD), and a sixth terminal ( B3) is connected to the third end (a2). The compensation transistor (T5) has a fifth control terminal (c5) connected to a third control signal (SCAN2), a ninth terminal (a5) connected to the sixth terminal (b3), and a tenth terminal ( B5) connected to the second control terminal (c2) and one end of the first storage capacitor (C).

The reset transistor (T3) has a fourth control terminal (c4) connected to the third control signal (SCAN2), a seventh terminal (a4) connected to an initial signal (Vini), and an eighth terminal (b4). The other end of the first storage capacitor (C) and the organic light emitting diode element (D1) are connected. The second light-emitting transistor (T6) has a sixth control terminal (c3) connected to a fourth control signal (EM2), and a tenth end (a6) connected to the fourth terminal (b2) and the second end ( B1), and a twelfth end (b6) are connected to the eighth end (b4) and the organic light emitting diode element (D1).

FIG. 35 is a timing diagram of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 34. As shown in FIG. 35, during a reset period, the first control signal (SCAN1) and the fourth control signal (EM2) are control low potential (VSS), second control signal (EM1), and third control. The signal (SCAN2) is controlled to a high potential (VDD). Therefore, the data is written to the transistor (T2) and the second light-emitting transistor (T6) is turned off. The driving transistor (T1), the compensation transistor (T5) The first light-emitting transistor (T4) and the reset transistor (T3) are turned on.

During the data input and compensation (Data Input + Vt Compensation) cycle, the second control signal (EM1) and the fourth control signal (EM2) are control low potential (VSS), first control signal (SCAN1) and third The control signal (SCAN2) is controlled to a high potential (VDD). Therefore, the first light-emitting transistor (T4) and the second light-emitting transistor (T6) are turned off, and the data is written into the transistor (T2), the driving transistor. (T1), the compensation transistor (T5) and the reset transistor (T3) are turned on.

During an Emitting cycle, the second control signal (EM1) and the fourth control signal (EM2) are controlled high (VDD), and the first control signal (SCAN1) and the third control signal (SCAN2) are low control. a potential (VSS), therefore, the data is written into the transistor (T2), the compensation transistor (T5), and the reset transistor (T3) is turned off, the driving transistor (T1), the first light-emitting transistor (T4) and the second illuminating transistor (T6) are turned on. The principle of the threshold voltage (Vt) compensation is similar to that of FIG. 4 and is known to those skilled in the art based on the disclosure of the present disclosure. Therefore, the region caused by the polycrystalline crystallization process can be compensated during the illuminating period The Vt variation of the property makes the brightness of the organic light-emitting diode element (D1) uniform, solving the problem of conventional brightness mura.

In one embodiment, the first illuminating transistor (T4) and the second illuminating transistor (T6) of FIG. 34 may be polycrystalline germanium transistors, data writing transistor (T2), driving transistor (T1), and compensation power. The crystal (T5) and the reset transistor (T3) may be a polycrystalline germanium transistor or an oxide semiconductor transistor.

In another embodiment, the first illuminating transistor (T4) and the second illuminating transistor (T6) of FIG. 34 are polycrystalline germanium transistors, which have better electron mobility and stability. The driving transistor (T1) may be an oxide semiconductor transistor to have a better uniformity of the threshold voltage (Vt) of the driving transistor (T1). The reset transistor (T3) is a polysilicon transistor to reduce the area of the circuit layout. The data write transistor (T2) is a polysilicon transistor to reduce the precharge time. The compensation transistor (T5) may be a polycrystalline germanium transistor or an oxide semiconductor transistor.

36 is a further circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. As shown in FIG. 36, the driving circuit 200 includes a data writing transistor (tft6) and a driving transistor (tft1). a first storage capacitor (Cst), a first light-emitting transistor (tft4), a compensation transistor (tft5), a reset transistor (tft2), and a second light-emitting transistor (tft3), It is used to drive an organic light-emitting diode (D1).

The data writing transistor (tft6) has a first control terminal (c1) connected to a first control signal (G2), a first terminal (a1) connected to a data line (Data), and a second terminal (b1). ). The driving transistor (tft1) has a second control terminal (c2), a third terminal (a2) connected to a high potential (PVDD), and a fourth terminal (b2) connected to the first storage capacitor (Cst) One end.

The first light-emitting transistor (tft4) has a third control terminal (c3) connected to a second control signal (EMIT), and a fifth terminal (a3) connected to the second control terminal of the driving transistor (tft1) ( C2), and a sixth end (b3) is connected to the other end of the first storage capacitor (Cst). The compensation transistor (tft5) has a fifth control The terminal (c5) is connected to the first control signal (G2), the ninth terminal (a5) is connected to a third control signal (VI), and the tenth terminal (b5) is connected to the driving transistor (tft1). Second control terminal (c2).

The reset transistor (tft2) has a fourth control terminal (c4) connected to a fourth control signal (G1), and a seventh terminal (a4) connected to the fourth terminal (b2) of the driving transistor (tft1) And one end of the first storage capacitor (Cst) and an eighth end (b4) are connected to the cathode end of the organic light emitting diode element (D1). The second light-emitting transistor (tft3) has a sixth control terminal (c6) connected to the second control signal (EMIT), and a tenth end (a6) connected to the fourth end of the driving transistor (tft1) ( B2), and a twelfth end (b6) are connected to the anode end of the organic light emitting diode element (D1).

37a to 37c are timing diagrams of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 36. As shown in FIG. 37a, during a reset period, the first control signal (G2) and the fourth control signal (G1) are control high potential (VDD), second control signal (EMIT), and third control. The signal (VI) is a control low potential (VSS), and therefore, the first light-emitting transistor (tft4), the driving transistor (tft1), and the second light-emitting transistor (tft3) are turned off, and the data is written into the transistor ( Tft6), the compensation transistor (tft5) and the reset transistor (tft2) are turned on. Therefore, the voltage on node X is Vdata, and the voltage on node Y is PVEE, where Vdata is the voltage of the data line and PVEE is a low potential. It should be noted that, at this time, the voltage of the third control signal (VI) is a low potential VI_L, and the low potential VI_L turns off the driving transistor (tft1) to prevent the organic light emitting diode (D1) from emitting light. .

As shown in FIG. 37b, during a Vt Compensation period, the first control signal (G2) and the third control signal (VI) are control high potential (VDD), second control signal (EMIT), and The four control signals (G1) are controlled to be low (VSS), and therefore, the first light-emitting transistor (tft4), the reset transistor (tft2), and the second light-emitting transistor (tft3) are turned off, and the data is written. The transistor (tft6), the driving transistor (tft1), and the compensation transistor (tft5) are turned on. Therefore, the voltage on node X is Vdata, and the voltage on node Y is VI_H-Vt1, where VI_H is a high voltage of the third control signal (VI), and Vt1 is the threshold voltage of the driving transistor (tft1). , Vt).

As shown in FIG. 37c, during an Emitting cycle, the first control signal (G2) and the fourth control signal (G1) are control low (VSS), second control signal (EMIT), and third. The control signal (VI) is controlled to a high potential (VDD), and therefore, the reset transistor (tft2), the compensation transistor (tft5), and the data write transistor (tft6) are turned off, and the drive transistor (tft1) The second illuminating transistor (tft3) and the first illuminating transistor (tft4) are turned on. Therefore, the voltage on node X is Vdata+Voled-VI_H+Vt1, and the voltage on node Y is Voled, where Voled is the voltage at the anode end of the organic light-emitting diode (D1). Since the first light-emitting transistor (tft4) is turned on, the voltage on the node W is about the voltage on the node X, that is, the voltage on the node W is Vdata+Voled-VI_H+Vt1. Therefore, the voltage Vgs of the gate and source of the driving transistor (tft1) is Vdata-VI_H+Vt1. Since the voltage on the node W has a threshold voltage (Vt1), the luminance of the organic light-emitting diode element (D1) can be compensated for by compensating for the Vt variation of the region caused by the polycrystalline crystallization process during the light-emitting period. To solve the problem of conventional brightness mura.

In one embodiment, the first illuminating transistor (tft4) and the second illuminating transistor (tft3) of FIG. 36 may be polycrystalline germanium transistors, and the driving transistor (tft1) may be an oxide semiconductor transistor, resetting the transistor. (tft2), the driving transistor (T1), the compensation transistor (tft5), and the data writing transistor (tft6) may be polycrystalline germanium transistors or oxide semiconductor transistors.

38 is a further circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode according to the present disclosure. As shown in FIG. 38, the driving circuit 200 includes a data writing transistor (tft6) and a driving transistor (tft1). a first storage capacitor (Cst), a first light-emitting transistor (tft4), a compensation transistor (tft5), a reset transistor (tft2), and a second light-emitting transistor (tft3), It is used to drive an organic light-emitting diode (D1).

The data writing transistor (tft6) has a first control terminal (c1) connected to a first control signal (XEMIT), a first terminal (a1) connected to a data line (Data), and a second terminal (b1). ). The driving transistor (tft1) has a second control terminal (c2) connected to the second terminal (b1), a third terminal (a2) connected to a high potential (PVDD), and a fourth terminal (b2) connected. To one end of the first storage capacitor (Cst).

The first light-emitting transistor (tft4) has a third control terminal (c3) connected to a second control signal (EMIT), a fifth terminal (a3) connected to the second control terminal (c2), and a sixth The terminal (b3) is connected to the other end of the first storage capacitor (Cst). The compensation transistor (tft5) has a fifth control terminal (c5) connected to the first control signal (XEMIT), a ninth terminal (a5) connected to the second control signal (EMIT), and a tenth end ( B5) Connect to a reference potential (VREF).

The reset transistor (tft2) has a fourth control terminal (c4) connected to a third control signal (G1), a seventh terminal (a4) connected to the fourth terminal (b2), and the first storage capacitor ( One end of Cst) and an eighth end (b4) are connected to the cathode end of the organic light emitting diode element (D1). The second light-emitting transistor (tft3) has a sixth control terminal (c6) connected to the second control signal (EMIT), a tenth end (a6) connected to the fourth terminal (b2), and a tenth The two ends (b6) are connected to the anode terminal of the organic light emitting diode element (D1).

39a to 39c are timing diagrams of the driving circuit 200 of the active matrix organic light emitting diode of FIG. 38. As shown in FIG. 39a, during a reset period, the first control signal (XEMIT) and the third control signal (G1) are control high potential (VDD), second control signal (EMIT), and data line ( Data) is to control the low potential (VSS), therefore, the driving transistor (tft1), the second illuminating transistor (tft3), and the first illuminating transistor (tft4) are turned off, and the data is written into the transistor (tft6) The compensation transistor (tft5) and the reset transistor (tft2) are turned on. Therefore, the voltage on node X is VREF, the voltage on node Y is PVEE, and the voltage on node W is Vdata_L, where Vdata_L is the voltage of the data line, which is a low potential, PVEE is a low potential, VREF Is the reference potential (VREF). It should be noted that at this time, the voltage on the node W is a low potential Vdata_L, and the low potential Vdata_L turns off the driving transistor (tft1) to prevent the organic light emitting diode (D1) from emitting light.

As shown in FIG. 39b, during a Vt Compensation period, the first control signal (XEMIT) and the data line (Data) are the control high potential (VDD), the second control signal (EMIT), and the third control signal ( G1) is to control the low potential (VSS), therefore, the first light-emitting transistor (tft4), the reset transistor (tft2), and the second light-emitting transistor (tft3) are turned off, and the data is written into the transistor (tft6). ), the drive transistor (tft1), And the compensation transistor (tft5) is turned on. Therefore, the voltage on node X is VREF, the voltage on node Y is Vdata_H-Vt1, and the voltage on node W is Vdata_H, where Vdata_H is a high voltage of data line (Data) and Vt1 is the driving transistor (tft1) Threshold voltage (Vt).

As shown in FIG. 39c, during an Emitting cycle, the first control signal (XEMIT), the data line (Data), and the third control signal (G1) are control low (VSS), and the second control signal ( EMIT) is to control the high potential (VDD), therefore, the reset transistor (tft2), the compensation transistor (tft5), and the data write transistor (tft6) are turned off, and the drive transistor (tft1), The two light-emitting transistors (tft3) and the first light-emitting transistor (tft4) are turned on. Since the first light-emitting transistor (tft4) is turned on, the voltage on the node W is the voltage on the node X, the voltage on the node X is VREF+Voled-Vdata_H+Vt1, and the voltage on the node Y is Voled, wherein Voled is the voltage at the anode end of the organic light-emitting diode (D1). That is, the voltage on the node W is VREF+Voled-Vdata_H+Vt1. Therefore, the voltage Vgs of the gate and source of the driving transistor (tft1) is VREF-Vdata__H+Vt1. That is, the current flowing through the driving transistor (tft1) is Kn '( VREF-Vdata _ H ) ² , where kn' is a metal oxide semiconductor field effect transistor transconductance parameter. In the current formula, since there is no Vt1 term, it means that Vt compensation has been performed. That is, since the voltage on the node W has a threshold voltage (Vt1), the organic light-emitting diode element (D1) can be compensated for during the light-emitting period by compensating for the Vt variation of the region caused by the polycrystalline crystallization process. The brightness is uniform, solving the problem of conventional brightness mura.

In one embodiment, the first illuminating transistor (tft4) and the second illuminating transistor (tft3) of FIG. 38 may be polycrystalline germanium transistors, and the driving transistor (tft1) may be an oxide semiconductor transistor, resetting the transistor. (tft2), the driving transistor (T1), the compensation transistor (tft5), and the data writing transistor (tft6) may be polycrystalline germanium transistors or oxide semiconductor transistors.

In this specification, some symbols represent both a signal name and the voltage of the signal. For example, Vini represents the initial signal and also represents the voltage of the initial signal. The same is true for other signals, so I won't go into details.

As can be seen from the above description, the illuminating transistor (T4) needs to have better electron mobility and stability, and thus the illuminating transistor (T4) is a polycrystalline germanium transistor. The LTPS transistor provides a large current when turned on, and has a large driving capability to drive the organic light emitting diode (D1). The threshold voltage (Vt) of the driving transistor (T1) needs to have better uniformity, so it is changed to an oxide semiconductor transistor, so that the control terminal (g) of the driving transistor (T1) can be eliminated. The voltage variation causes the first transistor (T1) to provide a stable driving current to the organic light emitting diode (D1), thereby improving the problem of poor brightness or uniformity of the prior art. In addition, the present disclosure has a stack-up structure with a transistor-shared gate, which can effectively save the area of the circuit layout.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

Driving circuit of 200‧‧‧ active matrix organic light emitting diode

(T2) ‧‧‧data writing to the transistor

(T1)‧‧‧ drive transistor

(Cst)‧‧‧First storage capacitor

(T4)‧‧‧Lighting crystal

(C1)‧‧‧Second storage capacitor

(T3) ‧‧‧Reset the transistor

(D1)‧‧‧Organic Luminescent Diodes

(c1) ‧ ‧ first control end

(a1) ‧ ‧ first end

(b1)‧‧‧second end

(c2) ‧‧‧second control end

(a2) ‧ ‧ third end

(b2) ‧ ‧ fourth end

(c3) ‧‧‧ third console

(a3) ‧ ‧ fifth end

(b3) ‧ ‧ sixth end

(c4) ‧‧‧ fourth console

(a4) ‧ ‧ seventh end

(b4) ‧ ‧ eighth end

(Data) ‧ ‧ data line

(ELVDD)‧‧‧High potential

(ELVSS)‧‧‧Low potential

(Sn)‧‧‧First control signal

(En)‧‧‧second control signal

(RST)‧‧‧Reset signal

(Vini) ‧ ‧ initial signal

Claims (10)

The driving circuit of the active matrix organic light emitting diode comprises: a data writing transistor having a first control end connected to a first control signal, a first end connected to a data line, and a second end; a driving transistor having a second control end connected to the second end, a third end, and a fourth end; a first storage capacitor connecting the second control end and the fourth end; The transistor has a third control terminal connected to a second control signal, a fifth terminal connected to a high potential, and a sixth terminal connected to the third terminal; and a second storage capacitor connected to the third The fifth end and the fourth end are coupled to an organic light emitting diode element by the fourth end. The driving circuit of claim 1, further comprising a reset transistor having a fourth control terminal connected to a reset signal, a seventh terminal connected to an initial signal, and an eighth terminal connection To the fourth end, wherein the driving transistor is an oxide semiconductor transistor, and the illuminating transistor and the reset transistor are polycrystalline germanium transistors. The driving circuit of claim 2, wherein the other driving circuit shares the reset transistor with the driving circuit, and the other driving circuit has the same structure as the driving circuit, and the reset transistor is oxidized. Semiconductor transistor. The driving circuit of claim 3, wherein the data writing transistor of the driving circuit is a P-type polysilicon transistor, and the data writing transistor of the other driving circuit is an N-type oxide semiconductor device. Crystal. The driving circuit of claim 3, wherein the driving circuit and the light emitting transistor of the other driving circuit are P-type polycrystalline silicon transistors, and the driving circuit of the driving circuit and the other driving circuit is N Type oxide semiconductor transistor. The driving circuit of claim 2, further comprising: a compensation transistor having a fifth control terminal connected to a sensing compensation signal, a ninth terminal connected to a sensing compensation signal line, and A tenth end is connected to the fourth end. The driving circuit of claim 2, further comprising: a compensation transistor having a fifth control terminal connected to a sensing compensation signal, a ninth terminal connected to the fourth terminal, and a first The ten end is connected to the data line. The driving circuit of claim 2, further comprising: a compensation transistor having a fifth control terminal connected to a sensing compensation signal, a ninth terminal connected to a sensing compensation signal line, and a tenth end; and a transistor having a sixth control terminal connected to the second control signal, a tenth end connected to the fourth end, and a twelfth end connected to the tenth end. The driving circuit of claim 2, further comprising: a compensation transistor having a fifth control terminal connected to a sensing compensation signal, a ninth terminal, and a tenth terminal connected to the data And a transistor having a sixth control end connected to the third control end, a tenth end connected to the fourth end, and a twelfth end connected to the ninth end. A display panel is an organic light emitting diode display panel having a plurality of driving circuits of active matrix organic light emitting diodes. The driving circuit of the active matrix organic light emitting diodes comprises: a data writing The transistor has a first control end connected to a first control signal, a first end connected to a data line, and a second end; a driving transistor having a second control end connected to the second end, a third end, and a fourth end; a first storage capacitor connecting the second control end and the fourth end; The transistor has a third control terminal connected to a second control signal, a fifth terminal connected to a high potential, and a sixth terminal connected to the third terminal; and a second storage capacitor connected to the third The fifth end and the fourth end are coupled to an organic light emitting diode element by the fourth end.