TWI581430B - Metal oxide semiconductor device - Google Patents

Description

Metal oxide semiconductor device structure

This invention relates to a semiconductor component, and more particularly to a high voltage MOS device.

Liquid crystal display (LCD) has gradually become the mainstream of display devices. Due to its light weight, small size, suitable for different size applications and low radiation, liquid crystal display devices are particularly suitable as notebook computers. Display screens for portable electronic devices such as mobile phones and global positioning systems (GPS).

When a large number of liquid crystal display devices are used in portable electronic devices, with the limitation of the battery capacity of the portable application, it is an indispensable requirement to have low power consumption. However, as the size of the LCD panel continues to increase, the power consumption of the LCD panel will also increase.

In general, the high voltage components used in the driver IC of a liquid crystal display device are mainly manufactured by a high voltage complementary metal oxide semiconductor (CMOS) process, mainly by forming an isolation layer to increase the source. The distance between the drain region and the gate is used to reduce the lateral electric field in the channel; or the light ion doping is performed in the drift region below the isolation layer and the grade region below the source/drain region. Reducing hot electron effects; thus increasing the junction breakdown voltage of the source/drain regions, which in turn enables the high voltage components of the driver circuit to function properly and provide a sufficiently high voltage.

In practical applications, it is quite urgent to save the power consumption of the LCD driver circuit and the LCD panel to avoid excessive power consumption.

In view of the above, it is an object of the present invention to provide a MOS device suitable for use in a driver integrated circuit of a liquid crystal display. The MOS device having a lower operating voltage provided by the present invention is particularly suitable for being disposed in a driver IC high voltage MOS device region or in combination with a high voltage MOS device.

The invention provides a MOS device, comprising a substrate having an N-type deep well region and at least one isolation structure, a P-type well region disposed in the N-type deep well region, disposed on the substrate and located in the P-type well region a gate, at least one N-type extension region, an N-type drain region and an N-type source region, and a P-type doped region. The N-type extension region is disposed in the P-type well region and is respectively located in the substrate on both sides of the gate electrode, and the N-type drain region and the N-type source region are respectively located in the substrate on both sides of the gate and are disposed on the N In the type of extension. In addition, the P-type doped region is disposed in the P-type well region and separated from the N-type source region by an isolation structure.

According to a preferred embodiment of the present invention, in the above MOS device, the N-type extension region further includes a double doped region.

In accordance with a preferred embodiment of the present invention, in the MOS device, one side of the N-type extension is aligned with the gate, and the other side of the N-type extension is located below the isolation structure. Alternatively, one side of the N-type extension extends to the underside of the gate, and the other side of the N-type extension is located below the isolation structure.

According to a preferred embodiment of the present invention, the MOS device further includes a spacer disposed on the sidewalls of the gate, and the N-type drain region and the N-type source region Side adjacent to the spacer and another One side abuts the isolation structure.

According to a preferred embodiment of the present invention, in the MOS device, the doping concentration of the N-type extension region is smaller than the doping concentration of the N-type drain region or the N-type source region.

According to a preferred embodiment of the present invention, in the above MOS device, the depth of the N-type extension region is greater than the depth of the N-type drain region or the N-type source region.

According to a preferred embodiment of the present invention, in the above MOS device, at least one N-type doping region is further disposed in the substrate in the N-type deep well region.

Since the MOS device of the present invention has a P-type well region providing a higher potential between the N-type source and the drain region and the substrate, the potential difference between the gate and the source and the drain and the source are reduced. The potential difference between the poles can achieve the purpose of reducing the voltage range and saving power consumption.

On the other hand, since the voltage range is lowered, the specification of the MOS device proposed by the present invention can be loosened, and the pitch between the elements can be reduced or reduced. In the MOS device proposed by the present invention, an N-type deep well region is further provided to ensure galvanic semiconductor devices and other high-voltage semiconductor devices which are electrically separated from the lower voltage range of the present invention.

In addition, the method for fabricating the MOS device of the present invention can be easily integrated into the current complementary CMOS process or the DMOS process without adding a mask. The MOS device structure of the present invention can be completed, so that no additional cost is added.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A to 1D are cross-sectional views showing a manufacturing process of a MOS transistor device according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is first provided. The substrate 100 is, for example, a P-type germanium substrate. Next, an N-type deep well region 102 is formed in the substrate 100. The formation method of the N-type deep well region 102 is formed, for example, by performing an ion implantation process using phosphorus as a dopant. Thereafter, a P-type well region 104 is formed in the N-type deep well region 102, and the P-type well region 104 is surrounded by the N-type deep well region 102. The formation method of the P-type well region 104 is formed, for example, by performing an ion implantation process using boron as a dopant.

Also, isolation structures 101 and 103 are formed in the N-type deep well region 102 and the P-type well region 104. It is readily known to those skilled in the art that any structure and material that can be used for isolation can be applied to the isolation structure 101 of the present invention. For example, the isolation structure 101/103 is formed, for example, by thermal oxidation. The field oxide layer or the shallow trench isolation structure, and the material of the isolation structure 101/103 is, for example, yttrium oxide.

Then, referring to FIG. 1B, a gate structure 110 is formed on the substrate 100. The gate structure 110 is a stacked structure including a gate dielectric layer 111 and a polysilicon gate 112. The gate electrode 110 is formed by, for example, forming a hafnium oxide layer (not shown) by thermal oxidation, and forming a doped polysilicon layer (not shown) by a field-doped chemical vapor deposition process, and then performing lithography and Formed by an etching process. Subsequently, the gate structure 110 can be used as a mask, and the gate junction An N-type extension 106 is formed between each side of the structure 110 and the isolation structure 101. The N-type extension 106 is located in the P-type well region 104. The formation method of the N-type extension region 106 is formed by, for example, doping with N-type ions such as phosphorus or arsenic by a double doping process. Since the gate structure 110 is used as a mask, the formed N-type extensions 106 are generally aligned on both sides of the gate structure 110. However, the N-type extensions 106 may also be designed to meet the needs of, for example, tempering. In a manner, it extends slightly to the sides so that it is partially below the gate structure 110 and/or the isolation structure 101.

Next, referring to 1C, a spacer 120 is formed on the sidewall of the gate 110. The material of the spacer 120 is, for example, tantalum nitride. The method for forming the spacers 120 is formed, for example, by forming a layer of spacer material (not shown) on the substrate 100 and performing an etch back process. Then, the gate structure 110 and the spacer 120 can be used together as a mask, and an N-type drain region 108 and an N-type source are formed between the two sides of the spacer 120 on the gate structure 110 and the isolation structure 101. The pole region 109, and the N-type drain region 108 and the N-type source region 109 are located in the N-type extension region 106 and are surrounded by the N-type extension region 106.

The N-type drain region 108 and the N-type source region 109 are adjacent to the isolation structures 101 on both sides, but may also extend slightly laterally to a point below the isolation structure 101 as needed for electrical design. Basically, the depth and range of the N-type extension region 106 are larger than the N-type drain region 108 and the N-type source region 109, but the doping concentration of the N-type extension region 106 is smaller than the doping concentration of the N-type source/drain region. . For example, the doping concentration of the N-type drain region 108 or the N-type source region 109 is, for example, about 10 ¹⁴ -10 ¹⁷ cm ^-3 .

Optionally, two of the N-type deep well regions 102 are remote from the gate 110 The side can simultaneously form the N-type doping region 122 using the same mask step. The formation method of the N-type doping region 122 is formed, for example, by an ion implantation process using phosphorus as a dopant, and the depth is approximately equal to the depth of the N-type drain/source region 108/109. The N-doped region 122 can serve, for example, as an external termination through which VDD (here, system supply voltage) can be applied to the N-type deep well region 102 to aid in electrical isolation.

Furthermore, referring to FIG. 1D, a P-type doping region 124 is formed in the P-type well region 104 between the gate 110 and the isolation structures 101 and 103. The formation method of the P-type doping region 124 is formed, for example, by boron as a dopant for an ion implantation process, and the depth is approximately equal to the depth of the N-type drain/source region 108/109. The P-type doping region 124 can serve, for example, as a substrate contact.

The steps of forming the above-mentioned various types of well regions or doped regions are merely examples, but those skilled in the art can easily infer that the formation sequences and steps may be changed depending on the component design or process. The above-described method for fabricating the MOS device can be integrated with the current CMOS process, and the MOS device of the present invention can be fabricated without adding a photomask. In the embodiment of the present invention, an NMOS device is taken as an example, but the manufacturing method of the present invention is not limited thereto.

2A is a cross-sectional view showing a MOS device according to an embodiment of the present invention. 2B is a partial top view of a MOS device according to an embodiment of the invention.

Referring to FIGS. 2A & 2B, the MOS device 10 of the present invention includes, for example, an NMOS including a substrate 100, an N-type deep well region 102, a P-type well region 104, isolation structures 101 and 103, a gate 110 and a spacer 120, and an N-type. Extension region 106, N-type drain region 108, N-type source region 109, and P-type Doped region 124.

2B, the relationship between the gate 110, the N-type extension 106, the N-type drain region 108 and the N-type source region 109 in FIG. 2A is mainly shown, and the active structures defined by the isolation structures 101 and 103 are defined. Area 20 is indicated by a solid line. The gate structure 110 is disposed on the substrate 100, and the N-type drain region 108 and the N-type source region 109 are disposed in the substrate on both sides of the gate structure 110 adjacent to the isolation structure 101, and the N-type extension region 106 is located at the gate. The substrate on both sides of the structure 110 is located below the N-type drain region 108 and the N-type source region 109 and surrounds the N-type drain region 108 and the N-type source region 109. The N-type drain region 108 and the N-type source region 109 are provided with a contact 130.

As shown in FIG. 2A, a P-type doped region 124 is provided in the P-type well region 104 between the gate 110 and the isolation structures 101 and 103, and the P-type well region 104 in the substrate 100 surrounds the N-type extension region. 106, N-type drain region 108, N-type source region 109 and P-type doped region 124. In addition, the N-type deep well region 102 in the substrate 100 completely surrounds the P-type well region 104, while electrically separating the P-type well region 104 from other components in the substrate 100.

Compared with the general high-voltage NMOS device electrical operation mode, the source and the base are grounded to GND and the gate and drain potentials are VDD (here, the system power supply voltage), and the MOS device of the present invention has a P-type light. Doping the well region 104 to increase the potential of the substrate (the P-type well region 104 can be regarded as the bulk of the NMOS and the potential is, for example, about 1/2 VDD), and the potentials of the N-type source region 109 and the P-type doping region 124 are both It is about 1/2 VDD, and the potential difference between the N-type source region 109 and the gate 110 is reduced to 1/2 VDD, and the potential difference between the N-type drain region 108 and the N-type source region 109 is reduced to The potential difference between 1/2 VDD and N-type drain region 108 and P-type well region 104 is also reduced to 1/2 VDD.

Therefore, the structure of the MOS structure of the embodiment of the invention can reduce the working voltage (about from the high voltage working range to the medium voltage working range), and further achieve the purpose of saving power consumption. In addition, because the voltage range is reduced and the component design specifications are looser, the pitch between the components is also reduced, thereby helping to reduce the component layout area.

The MOS device of the present invention can replace the general high voltage component partially disposed in the LCD driver integrated circuit of the liquid crystal display, thereby achieving the purpose of reducing power consumption and saving energy.

The material and formation method of each film layer in the MOS device of the present invention, and the method of forming each doped region have been described in detail in the above-described method for manufacturing a MOS device, and will not be described herein.

Since the method for fabricating the MOS device proposed by the present invention can be integrated with the current CMOS process, the MOS device of the present invention can be fabricated without adding a photomask, and thus no additional cost is added. Therefore, the MOS element of the present invention can be fabricated together with other general high-voltage elements in the high-voltage element region; however, in the MOS device structure of the present invention, since the P-type well region having a higher potential is used, the work can be effectively reduced. The voltage range and the power consumption are reduced, and the MOS device of the present invention can be electrically isolated from other high voltage components of different potentials by using the N-type deep well region.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧Gold-oxide semiconductor components

20‧‧‧active area

100‧‧‧Base

101, 103‧‧‧ isolation structure

102‧‧‧N type deep well area

104‧‧‧P type well area

106‧‧‧N type extension

108‧‧‧N type bungee area

109‧‧‧N-type source region

110‧‧‧ gate

111‧‧‧gate dielectric layer

112‧‧‧Polysilicon gate

120‧‧‧ spacer

122‧‧‧N-doped area

124‧‧‧P-doped area

130‧‧‧Contacts

1A to 1D are cross-sectional views showing a manufacturing process of a MOS transistor device according to an embodiment of the present invention.

2A is a cross-sectional view showing a MOS device according to an embodiment of the present invention.

2B is a partial top view of a MOS device according to an embodiment of the invention.

100‧‧‧Base

101, 103‧‧‧ isolation structure

102‧‧‧N type deep well area

104‧‧‧P type well area

106‧‧‧N type extension

108‧‧‧N type bungee area

109‧‧‧N-type source region

110‧‧‧ gate

111‧‧‧gate dielectric layer

112‧‧‧Polysilicon gate

120‧‧‧ spacer

122‧‧‧N-doped area

124‧‧‧P-doped area

Claims (8)

A MOS device for use in a display driving integrated circuit, the device comprising: a substrate having an N-type deep well region and at least one isolation structure; and a P-type well region disposed in the N-type deep well region, wherein The P-type well region has a potential of 1/2 power supply voltage (1/2 VDD); a gate is disposed on the substrate and located in the P-type well region, wherein a power supply voltage (VDD) is applied to the gate At least one N-type extension region is disposed in the P-type well region and respectively located in the substrate on both sides of the gate; an N-type drain region and an N-type source region are respectively located in the substrate on both sides of the gate And disposed in the N-type extension region; an N-type doped region disposed in the N-type deep well region and directly contacting the N-type deep well region; and a P-type doped region disposed in the P-type well region Applying VDD to the N-type drain region, the N-type source region and the P-type doping region are electrically connected to the P-type well region to have a potential of 1/2 VDD, so that the N-type source region The potential difference from the gate is about 1/2 VDD, the potential difference between the N-type drain region and the N-type source region is about 1/2 VDD, and the potential difference between the N-type drain region and the P-type well region It is about 1/2 VDD. The MOS device of claim 1, wherein the N-type extension further comprises a double doped region. The MOS device of claim 1, wherein one side of the N-type extension is aligned with the gate, and the other side of the N-type extension is located below the isolation structure. The MOS device of claim 1, wherein one side of the N-type extension extends below the gate and the other side of the N-type extension is below the isolation structure. The MOS device of claim 1, further comprising a spacer disposed on the sidewalls of the gate, wherein the N-type drain region and a side of the N-type source region abut the spacer The other side is adjacent to the isolation structure. The MOS device according to claim 1, wherein a doping concentration of the N-type extension region is smaller than a doping concentration of the N-type drain region or the N-type source region. The MOS device of claim 1, wherein the N-type extension has a depth greater than a depth of the N-type drain region or the N-type source region. The MOS device of claim 1, further comprising applying a power supply voltage (VDD) to the N-type doping region.