TWI581233B - Low power source drive circuit - Google Patents

Description

Low power source driver circuit

The invention relates to a source driving circuit, in particular to a low power source driving circuit.

In recent years, with the rise of the information product market, liquid crystal displays are widely used in computer systems and mobile devices due to their advantages of thinness, low power consumption, no radiation pollution, and compatibility with semiconductor process technology. The liquid crystal display uses a source driving chip and a gate driving chip to drive pixels on the panel to display images. Generally, the source driving chip consumes more power, and as the resolution of the liquid crystal display continues to increase, it means that More and more sources drive the chip, and this need conflicts with the system design engineer's goal of saving system power.

Referring to FIG. 1, FIG. 2 and FIG. 3, the conventional source driving chip utilizes a class AB CMOS amplifier as a circuit structure of an output stage, and FIG. 1 shows an operation of charging a load capacitor 100 by an amplifier of a source driving chip output stage. When the control signal = 1 (inverting control signal = 0), the switch is turned on and the inverting switch is not turned on. The pull-up current of the amplifier is as shown in FIG. 3, which is 4I plus the flow to the load capacitor 100. Charge Electric current. In addition, FIG. 2 shows the operation when the amplifier of the output stage discharges the load capacitor 100. When the control signal=1 (inverted control signal=0), the pull-down current of the amplifier is as shown in FIG. 4I plus the discharge current from the load capacitor 100. In the charging and discharging operations shown in FIGS. 1 and 2, when the control signal = 0 (inverting control signal = 1), the switch is not turned on and the inverting switch is turned on, and the pull-up and pull-down currents of the amplifier are both 0 to achieve the effect of reducing power consumption. At present, the low-power consumption of the output stage circuit of the source driver chip shown in FIG. 1 has reached the design bottleneck. Therefore, how to effectively reduce the power consumption of the single source-level driver chip has become a problem to be solved by related companies. .

Accordingly, it is an object of the present invention to provide a low power source driver circuit.

Therefore, the low-power source driving circuit of the present invention is electrically connected to a load and includes a first output stage and a second output stage.

The first output stage is controlled to determine whether a first pull-up current is generated.

The second output stage is controlled to determine whether a second pull-up current is generated.

When a first charging period, the first output stage generates the first pull-up current and the second output stage generates the second pull-up current, and a portion of the first and second pull-up currents A charging current charges the load.

When in a second charging period, the second output stage does not generate the second pull-up current, and the first output stage generates the first pull-up current, and a portion of the first pull-up current serves as the The charging current charges the load.

The effect of the present invention is that the low-power source driving circuit is designed by a two-stage output stage, and the first and second output stages jointly charge the load during the first charging period, and During the second charging period, the load is only charged by the first output stage, which can effectively reduce the charging current and achieve the effect of power saving.

100‧‧‧ load capacitance

200‧‧‧ load capacitance

1‧‧‧First output stage

11‧‧‧First switch unit

111‧‧‧First switch

112‧‧‧Second switch

113‧‧‧First Inverting Switch

114‧‧‧Secondary inverter switch

12‧‧‧First buffer unit

121‧‧‧First transistor

122‧‧‧Second transistor

2‧‧‧second output stage

21‧‧‧Second switch unit

211‧‧‧ third switch

212‧‧‧fourth switch

213‧‧‧ Third Inverting Switch

214‧‧‧fourth inverter switch

22‧‧‧Second buffer unit

221‧‧‧ Third transistor

222‧‧‧ Fourth transistor

3‧‧‧Operating circuit

Vo‧‧‧ output voltage

Vo’‧‧‧ output voltage

Other features and effects of the present invention will be apparent from the following description of the drawings. FIG. 1 is a block diagram illustrating an operation of a conventional source driving circuit for charging a load capacitor; A block diagram illustrating an operation of a conventional source driver circuit for discharging the load capacitor; and FIG. 3 is a waveform diagram illustrating operation of the source driver circuit illustrated in FIGS. 1 and 2; 4 is a block diagram showing an embodiment of charging a load capacitor by the low power source driving circuit of the present invention; and FIG. 5 is a block diagram showing an implementation of discharging the load capacitor by the low power source driving circuit of the present invention. And FIG. 6 is a waveform diagram illustrating the operation of the embodiment shown in FIGS. 4 and 5.

Referring to FIG. 4, the low-power source driving circuit of the present invention is electrically connected to a load, and includes a first output stage 1, a second output stage 2, an arithmetic circuit 3, and a control circuit (not shown). In this embodiment, the load is a load capacitor 200.

The control circuit (not shown) generates a first control signal, a first inverted control signal, a second control signal, and a second inverted control signal, and the phase of the first control signal is inverted from the first An inversion control signal has a phase, the phase of the second control signal being inverted to a phase of the second inverted control signal.

The operation circuit 3 receives a first working bias voltage and a second operating bias voltage, and generates a first enable voltage and a second enable voltage. The second operating bias is a ground voltage. The level of the first working bias is greater than the threshold of the first enabling voltage by at least one threshold voltage, the level of the first enabling voltage is greater than the second enabling voltage, and the second enabling The voltage level is greater than the second operating bias voltage by at least one threshold voltage. The arithmetic circuit 3 can be further according to a liquid crystal display every predetermined time a new screen, and updating the first and the second enable voltages once, so that the low-power source driving circuit drives the load capacitor 200 to be in a charging operation according to the received first and second enable voltages One of the operations with a discharge. For example, the frame rate of the liquid crystal display is 60 frames per second, that is, when one screen is displayed every sixtieth of a second, the operation circuit 3 is separated by one-sixtieth. The first and the second enable voltage are updated once, and the low-power source driving circuit drives the load capacitor 200 to make the load capacitor 200 be black, white, or a checkerboard, etc. One of charging operation and the discharging operation.

The first output stage 1 is controlled to determine whether a first pull-up current is generated to charge the load capacitor 200, and the voltage level of the load capacitor 200 is pulled up, and includes a first switching unit 11, And a first buffer unit 12.

The first switching unit 11 is controlled to output a first charging control signal indicating enable or disable. In this example, the first switch unit 11 includes a first switch 111, a second switch 112, a first reverse switch 113, and a second reverse switch 114. The description of the first charging control signal will be described later.

The first switch 111 has a first end, a second end for receiving the first enable voltage of the operation circuit 3, and a control end for receiving the first control signal, and the first switch 111 switching between conducting and non-conducting according to the first control signal between. For example, when the first control signal is logic 1, the first switch 111 is turned on; when the first control signal is logic 0, the first switch 111 is not turned on.

The second switch 112 has a first end, a second end for receiving the second enable voltage of the operation circuit 3, and a control end for receiving the first control signal, and the second switch 112 switches between the conducting and the non-conducting according to the first control signal. For example, when the first control signal is logic 1, the second switch 112 is turned on; when the first control signal is logic 0, the second switch 112 is not turned on.

The first inverting switch 113 has a first end for receiving the first working bias, a second end electrically connected to the second end of the first switch 111, and a receiving the first inverting control The control terminal of the signal, and the first inverting switch 113 is switched between the conducting and the non-conducting according to the first inverting control signal. It should be noted that when the first control signal is logic 1, the first inversion control signal is logic 0, the first inversion switch 113 is non-conducting; when the first control signal is logic 0, the An inverting control signal is logic 1, and the first inverting switch 113 is turned on.

The second inverting switch 114 has a first end for receiving the second working bias, a second end electrically connected to the second end of the second switch 112, and a second receiving end for receiving the first inverting control The control terminal of the signal, and the second inverting switch 114 is switched between the conducting and the non-conducting according to the first inverting control signal. For example, when the first reverse phase control The signal is logic 0, the second inverter switch 114 is non-conducting; when the first inversion control signal is logic 1, the second inverter switch 114 is turned on.

Therefore, when the first switch 111 and the second switch 112 are turned on, the first inverting switch 113 and the second inverting switch 114 are not turned on. At this time, the second end of the first switch 111 outputs the a first uniform energy voltage, and the second enable voltage is output by the second end of the second switch 112 to form the first charge control signal indicating the enable. When the first inverting switch 113 and the second inverting switch 114 are turned on, the first switch 111 and the second switch 112 are not turned on. At this time, the second end of the first inverting switch 113 is output. The first working bias voltage is outputted by the second end of the second inverting switch 114 to form the first charging control signal indicating the de-energization.

The first buffer unit 12 is electrically connected between the load capacitor 200 and the first switch unit 11. The first buffer unit 12 correspondingly generates or does not generate the first according to the first charging control signal indicating enable or disable. Pull up current. In this example, the first buffer unit 12 includes a first transistor 121 and a second transistor 122. The detailed components of the first buffer unit 12 will be described one by one below.

The first transistor 121 has a control end electrically connected to the second end of the first switch 111 and the second end of the first inverting switch 113, a first end for receiving the first working bias, and A second end of the load capacitor 200 is electrically connected. In this embodiment, the first transistor 121 is a P-type metal oxide semiconductor field effect transistor. (hereinafter referred to as PMOS), and the control terminal is its gate, the first terminal is its source, and the second terminal is its drain.

The second transistor 122 has a control end electrically connected to the second end of the second switch 112 and the second end of the second inverting switch 114, a first end for receiving the second working bias, and A second end of the load capacitor 200 is electrically connected. In this embodiment, the second transistor 122 is an N-type metal oxide semiconductor field effect transistor (hereinafter referred to as NMOS), and the control terminal is its gate, the first terminal is its source, and the first The second end is its bungee.

When the control terminal of the first transistor 121 receives the first enable voltage from the first switch 111, and when the control terminal of the second transistor 122 receives the second enable voltage from the second switch 112, The first pull-up current is output from the second end of the first transistor 121. And when the control end of the first transistor 121 receives the first operating bias from the first switch 111, and when the control terminal of the second transistor 122 receives the second operating bias from the second switch 112 The second end of the first transistor 121 does not output the first pull-up current.

The second output stage 2 is controlled to determine whether a second pull-up current is generated to charge the load capacitor 200, and includes a second switching unit 21 and a second buffer unit 22.

The second switching unit 21 is controlled to output a second charging control signal indicating enable or disable. In this example, the second switch unit 21 includes a third switch 211, a fourth switch 212, a third reverse switch 213, and a fourth reverse switch 214. The detailed components of the second switching unit 21 will be described one by one below. The description of the second charging control signal will be described later.

The third switch 211 has a first end electrically connected to the second end of the first switch 111 to receive the first enable voltage, a second end, and a control end for receiving the second control signal. And the third switch 211 is switched between the conduction and the non-conduction according to the second control signal. For example, when the second control signal is logic 1, the third switch 211 is turned on; when the second control signal is logic 0, the third switch 211 is not turned on.

The fourth switch 212 has a first end electrically connected to the second end of the second switch 112 to receive the second enable voltage, a second end, and a control end for receiving the second control signal. And the fourth switch 212 switches between the conduction and the non-conduction according to the second control signal. For example, when the second control signal is logic 1, the fourth switch 212 is turned on; when the second control signal is logic 0, the fourth switch 212 is not turned on.

The third inverting switch 213 has a first end for receiving the first working bias, a second end electrically connected to the second end of the third switch 212, and a second end Receiving a control end of the second inversion control signal, and the third inversion switch 213 is switched between conducting and non-conducting according to the second inverting control signal. It should be noted that when the second control signal is logic 1, the second inversion control signal is logic 0, the third inversion switch 213 is non-conducting; when the second control signal is logic 0, the The second inverting control signal is logic 1, and the third inverting switch 213 is turned on.

The fourth inverting switch 214 has a first end for receiving the second working bias, a second end electrically connected to the second end of the fourth switch 212, and a second end control for receiving the second inverting control The control terminal of the signal, and the fourth inverting switch 214 is switched between the conducting and the non-conducting according to the second inverting control signal. For example, when the second inverted control signal is logic 0, the fourth inverting switch 214 is non-conducting; when the second inverting control signal is logic 1, the fourth inverting switch 214 is turned on.

Therefore, when the third switch 211 and the fourth switch 212 are turned on, the third inverting switch 213 and the fourth inverting switch 214 are not turned on. At this time, the second end of the third switch 211 outputs the The first uniform energy voltage is outputted by the second end of the fourth switch 212 to form the second charging control signal indicating the enable. When the third inverting switch 213 and the fourth inverting switch 214 are turned on, the third switch 211 and the fourth switch 212 are not turned on. At this time, the second end of the third inverting switch 213 outputs the The first working bias voltage is outputted by the second end of the fourth inverting switch 214 to form the second charging control signal indicating the de-energization.

The second buffer unit 22 is electrically connected between the load capacitor 200 and the second switch unit 21, and the second buffer unit 22 correspondingly generates or does not generate the second according to the second charging control signal indicating enabling or disabling. Pull up current. In this example, the second buffer unit 22 includes a third transistor 221 and a fourth transistor 222. The detailed components of the second buffer unit 22 will be described below one by one.

The third transistor 221 has a control end electrically connected to the second end of the third switch 211 and the second end of the third inverting switch 213, a first end for receiving the first working bias, and a first end The second end of the load capacitor 200 is electrically connected.

The fourth transistor 222 has a control end electrically connected to the second end of the fourth switch 212 and the second end of the fourth inverting switch 214, a first end for receiving the second working bias, and A second end of the load capacitor 200 is electrically connected.

When the control terminal of the third transistor 221 receives the first enable voltage from the third switch 211, and when the control terminal of the fourth transistor 222 receives the second enable voltage from the fourth switch 212, The second pull-up current is outputted from the second end of the third transistor 221 . When the control terminal of the third transistor 221 receives the first operating bias from the third switch 211, and when the control terminal of the fourth transistor 222 receives the second operating bias from the fourth switch 212, The second terminal of the third transistor 221 does not output the second pull-up current.

Referring to FIG. 4 and in conjunction with FIG. 6, in the embodiment, the first switching unit 11 and the second switching unit 21 are in a first charging period related to the charging operation of the load capacitor 200. Controlling the output of the second charging control signal that is enabled, such that the first output stage 1 generates the first pull-up current and the second output stage 2 generates the second pull-up current, wherein the first pull-up current a portion of the current flows to the load capacitor 200, a portion of which flows to the second transistor 122, a portion of the second pull-up current flows to the load capacitor 200, and a portion flows to the fourth transistor 222, and the first and second pull-ups The portion of the current that flows collectively to the load capacitor 200 charges the load capacitor 200 as a charging current (as shown by the hatched portion in FIG. 6). And when a second charging period in which the load capacitance 200 is in the steady state charging operation, the second switching unit 21 is controlled to output the second charging control signal indicating the deactivation, so that the second output Stage 2 does not generate the second pull-up current, and the first output stage 1 generates the first pull-up current, and a portion of the first pull-up current charges the load capacitor 200 as the charging current, one part The portion flows to the second transistor 122.

The specific implementation and related component operations are further described as follows: when the first charging period is, the first control signal is logic 1 (the first inversion control signal is logic 0), and the second control signal is logic 1 The second inverting control signal is logic 0. At this time, the first switch 111 and the second switch 112 of the first switching unit 11 are both turned on (the first inverting switch 113 and the second inverting switch) Switch 114 is not guided And the third switch 211 and the fourth switch 212 of the second switch unit 21 are both turned on (the third inverting switch 213 and the fourth inverting switch 214 are not turned on), at this time, the first The control terminal of the transistor 121 receives the first enable voltage, and the control terminal of the second transistor 122 receives the second enable voltage. The control terminal of the third transistor 221 receives the first enable voltage. The voltage is consistent, and the control terminal of the fourth transistor 222 receives the second enable voltage.

As such, in the first charging period, the first transistor 121, the second transistor 122, the third transistor 221, and the fourth transistor 222 are all enabled, wherein the first transistor 121 is The first end correspondingly generates the first pull-up current, and is outputted through the second end of the first transistor 121, a portion flows as the charging current to the load capacitor 200, and another portion flows to the second transistor 122. Second end. The first end of the third transistor 221 correspondingly generates the second pull-up current and outputs through the second end of the third transistor 221, and a portion flows as the charging current to the load capacitor 200, and the other portion As a second pull-down current flows to the second end of the fourth transistor 222. Therefore, as shown in FIG. 6, in the first charging period in which the charging capacitor 200 has a steep charging slope and requires an emergency current, the first output stage 1 and the second output stage 2 respectively output the first pull-up current and the A portion of the second pull-up current charges the load capacitor 200 as the charging current, and 4I is the first and second output stages 1, 2 The current value of the PMOS flowing to the NMOS is summed, and I is the current value of only the first output stage 1 flowing from the PMOS to the NMOS.

When in the second charging period, the first control signal is logic 1 (the first inversion control signal is logic 0), and the second control signal is logic 0 (the second inversion control signal is logic 1) At this time, the first switch 111 and the second switch 112 of the first switch unit 11 are both turned on (the first inverting switch 113 and the second inverting switch 114 are not turned on), and the second switch The third inverting switch 213 and the fourth inverting switch 214 of the unit 21 are both turned on (the third switch 211 and the fourth switch 212 are not turned on), and at this time, the control end of the first transistor 121 Receiving the first enable voltage, the control terminal of the second transistor 122 receives the second enable voltage, the control terminal of the third transistor 221 receives the first operational bias, and the first The second operational bias is received by the control terminal of the quad transistor 222. As such, in the second charging period, only the first transistor 121 and the second transistor 122 are enabled, and the third transistor 221 and the fourth transistor 222 are both disabled, and therefore, at the load. The charging slope of the capacitor 200 is moderated to reach the second charging period of steady state charging, and the second output stage 2 is turned off, and only the first output stage 1 charges the load capacitor 200, thereby achieving power saving effect.

Further, the low-power source driving circuit of the present invention can be smaller than the second output stage by controlling a first parallel number ratio of the first transistor 121 of the first output stage 1 with respect to the second transistor 122. The third transistor 221 of 2 is opposite to the first a second parallel number ratio of the fourth transistor 222 is further controlled. During the second charging period, the first pull-up current and the second pull-up current respectively occupy the first output stage 1 and the second output stage The ratio of the total output current of 2. For example, by designing the first parallel number ratio to be 2:1, and the second parallel number ratio is 6:3, the first pull-up current can be made to occupy the first output stage 1 and The second output stage 2 has a total output current of about one quarter, and the second pull-up current accounts for about three quarters. Therefore, as shown in FIG. 6, only the first output stage is in the second charging period. 11 generates the first pull-up current, so only about one quarter of the current consumption is left, that is, the driving force of the source driving circuit is only 25%, so that the source driving circuit can be effectively reduced. The current exceeds 50%.

Referring to FIG. 5 and in conjunction with FIG. 6, it is additionally noted that the first output stage 1 generates the first pulldown when a first discharge period associated with the load capacitance 200 is in the transient discharge operation ( Pulling down the current and the second output stage 2 generates the second pull-down current, wherein the first pull-down current is partially from the first transistor 121, and the other part is from the load capacitor 200, and the second pull-down current One portion is from the third transistor 221, and the other portion is from the load capacitor 200, and a portion of the first and second pull-down currents from the load capacitor 200 is a discharge current of the load capacitor 200 (eg, Figure 6 is a diagonal line). And when a second discharge period in which the load capacitance 200 is in the steady state discharge operation, the second output stage 2 does not generate the second pull-down current, and the first output stage 1 generates the first lower stage Pulling current, And a part of the first pull-down current is from the first transistor 121, and the other part is a discharge current from the load capacitor 200. Therefore, when the first discharge period is, the logic value of the first control signal is 1, and the logic value of the second control signal is 0, the first switching unit 11 and the second of the first output stage 1 The second switching unit 21 of the output stage 2 is enabled, and the first pull-down current of the first output stage 1 and the second pull-down current of the second output stage 2 respectively have a portion as the discharge current. The load capacitor 200 is discharged, and 4I is a sum of current values of the first and second output stages 1, 2 flowing from the PMOS to the NMOS. When in the second discharging period, the second switching unit 21 of the second output stage 2 is deenergized without generating the second pull-down current, and the first output stage 1 generates the first pull-down current, and I means that only the current value of the first output stage 1 flowing from the PMOS to the NMOS. Therefore, as shown in FIG. 6, during the second discharge period, only about one quarter of the total output current of the first output stage 1 and the second output stage 2 is consumed, that is, the source The driving force of the driving circuit is also only 25%, so that the current of the source driving circuit can be effectively reduced by more than 50%.

In summary, the low-power source driving circuit of the present invention has a two-stage output stage design, and the first output stage 1 and the second output stage 2 are common during the first charging (discharging) period The load capacitor 200 is charged (discharged), and during the second charging (discharging) period, the load capacitor 200 is charged (discharged) only by the first output stage 1. The driving force of the first output stage 1 and the second output stage 2 is effectively reduced to achieve the effect of power saving, so that the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

200‧‧‧ load capacitance

1‧‧‧First output stage

11‧‧‧First switch unit

111‧‧‧First switch

112‧‧‧Second switch

113‧‧‧First Inverting Switch

114‧‧‧Secondary inverter switch

12‧‧‧First buffer unit

121‧‧‧First transistor

122‧‧‧Second transistor

2‧‧‧second output stage

21‧‧‧Second switch unit

211‧‧‧ third switch

212‧‧‧fourth switch

213‧‧‧ Third Inverting Switch

214‧‧‧fourth inverter switch

22‧‧‧Second buffer unit

221‧‧‧ Third transistor

222‧‧‧ Fourth transistor

3‧‧‧Operating circuit

Vo’‧‧‧ output voltage

Claims (7)

A low power source driving circuit electrically connected to a load and comprising: a first output stage controlled to determine whether to generate a first pull-up current; and a second output stage controlled to determine whether to generate a first Two pull-up currents; when a first charging period, the first output stage generates the first pull-up current and the second output stage generates the second pull-up current, and the first and second pull-up currents Portion of the load as a charging current; when in a second charging period, the second output stage does not generate the second pull-up current, and the first output stage generates the first pull-up current, And charging a portion of the first pull-up current as the charging current; the first output stage includes a first switching unit and a first buffer unit, the first switching unit is controlled to output an indication a first charging control signal capable of or capable of being electrically connected between the load and the first switching unit, the first buffering unit correspondingly generating according to the first charging control signal indicating enabling or deactivating Or does not produce the first The first switching unit of the first output stage includes: a first switch having a first end for receiving a first enable voltage, a second end, and a first receiving a control end of the control signal, and switching between the conduction and the non-conduction according to the first control signal; a second switch having a first end, a second end for receiving a second enable voltage, and a Receiving the control end of the first control signal, and switching between the conducting and non-conducting according to the first control signal; a first inverting switch having a first end for receiving a first operating bias, a second end electrically connected to the second end of the first switch, and a receiving a first inverted control signal And a second inverting switch having a first end for receiving a second operating bias and an electrical connection a second end of the second end of the second switch, and a control end for receiving the first inverted control signal, and switching between conducting and non-conducting according to the first inverted control signal; when the first and second The switch is turned on, the second enable terminal of the first switch outputs the first enable voltage, and the second end of the second switch outputs the second enable voltage to form the first charge control signal indicating the enablement; When the first and second inverting switches are turned on, and the second working end of the first inverting switch outputs the first working bias, and the second end of the second inverting switch outputs the second working bias Pressing to form the first charge control signal indicating the deactivation; wherein the first inversion Inverting the phase of the signal produced in the first phase of the control signal. The low-power source driving circuit of claim 1, wherein the first buffer unit of the first output stage comprises a first transistor having a second end electrically connected to the first switch and the first a control end of the second end of the inverting switch, a first end for receiving the first working bias, and a second end electrically connected to the load, and a second transistor having a control end electrically connected to the second end of the second switch and the second end of the second inverting switch, a first end for receiving the second working bias, and an electric Connecting the second end of the load; when the control end of the first transistor receives the first enable voltage from the first switch, and when the control end of the second transistor receives the second from the second switch When the voltage is capable, the first pull-up current is outputted by the second end of the first transistor; when the control end of the first transistor receives the first operating bias from the first switch, and when the second When the control terminal of the crystal receives the second operating bias from the second switch, the second terminal of the first transistor does not output the first pull-up current. The low-power source driving circuit of claim 1, wherein the second output stage comprises a second switching unit controlled to output a second charging control signal indicating enable or disable, and a second a buffer unit electrically connecting the load and the second switching unit, the second buffer unit correspondingly generating or not generating the second pull-up current according to the second charging control signal indicating enabling or disabling; During the first charging period, the second switching unit is controlled to output the second charging control signal indicating the enabling; when in the second charging period, the second switching unit is controlled to output the indication to enable the second charging control signal. The low power source driving circuit of claim 3, wherein the second switching unit of the second output stage comprises a third switch having a first end for receiving a first enable voltage, a second end, and a control end for receiving a second control signal, and switching to be turned on according to the second control signal And a non-conducting, and a fourth switch having a first end for receiving a second enable voltage, a second end, and a control end for receiving the second control signal, and according to the The second control signal is switched between conducting and non-conducting; when in the first charging period, the third and fourth switches are turned on, and the second enabling end of the third switch outputs the first enabling voltage, and the first The second end of the four switches outputs the second enable voltage to form the second charge control signal indicating the enable. The low-power source driving circuit of claim 4, wherein the second switching unit of the second output stage further comprises a third inverting switch having a first receiving a first operating bias a second end of the second end of the third switch, and a control end for receiving a second inverted control signal, and switching between the conducting and the non-conducting according to the second inverting control signal, And a fourth inverting switch having a first end for receiving a second operating bias, a second end electrically connected to the second end of the fourth switch, and a second inverting control for receiving a control end of the signal, and switching between the conducting and the non-conducting according to the second inverting control signal; when in the second charging period, the third and fourth inverting switches are turned on, by the third inverting switch The second end outputs the first working bias, and the second end of the fourth inverting switch outputs the second working bias to form the second charging control signal indicating the de-energization; The phase of the second inverted control signal is opposite to the phase of the second control signal. The low-power source driving circuit of claim 5, wherein the second buffer unit of the second output stage comprises a third transistor having a second end electrically connected to the third switch and the third a control end of the second end of the inverting switch, a first end for receiving the first working bias, and a second end electrically connected to the load, and a fourth transistor having an electrical connection a second end of the switch and a control end of the second end of the fourth inverting switch, a first end for receiving the second working bias, and a second end electrically connected to the load; During the charging period, the control end of the third transistor receives a first enable voltage from the third switch, and the control end of the fourth transistor receives a second enable voltage from the fourth switch, and The second terminal of the triode outputs the second pull-up current; when in the second charging period, the control terminal of the third transistor receives the first operating bias from the third switch, the fourth transistor The control terminal receives a second operating bias from the fourth switch, and the third transistor The second terminal of the body does not output the second pull-up current. The low power source driving circuit of claim 1, wherein the first output stage is further controlled to determine whether to generate a first pull-down current, the second output stage is further controlled to determine whether a second pulldown a current; when a first discharge period, the first output stage generates the first pull-down current and the second output stage generates the second pull-down current, and a portion of the first and second pull-down currents a discharge current discharges the load; When a second discharge period, the second output stage does not generate the second pull-down current, and the first output stage generates the first pull-down current, and a portion of the first pull-down current serves as the discharge The current discharges the load.