201029325 六、發明說明： 【發明所屬之技術領域】 [0001丨在此所描述之實施例係有關於一種顯示器裝置，尤其是有 關於一種驅動器裝置之輸出緩衝電路、一種放大器裝置，以及一 種使用該輸出緩衝電路之顯示器裝置。 【先前技術】 Φ 丨0002】-般而言，在精密、輕巧、低功率以及高品質的顯示器裝 置的開發下，對於低功率耗損、高速率、高解析度，以及大輪出 範圍的液晶顯示器(Liquid Crystal Display; LCD)裝置的需求乃與日 漸增。LCD驅動器普遍上由源極驅動器、閘極驅動器、控制器， 以及參考電源構成。為達上述需求，這些源極驅動器扮演著尤其 重要的角色，而這些源極驅動器包含暫存器、資料鎖存器、數位 至類比轉換器(Digital-to_Analog Converter ; DAC)，以及輸出緩衝 魯器虽中，這些輸出緩衝器決定了源極驅動器的速率、解析度、 電壓範圍，以及功率耗損。由於單—的晶片喊有大量(典型上違 數百個)的輸出緩衝器，因此每一個輸出緩衝器必須僅佔據較小的 晶片面積’同時其功率消耗也必須夠低。 I麵31第i圖係一傳統源極驅動器裝置之示意圖。於第i圖中， 一傳統源極驅動器裝置觸係包含一輪出緩衝電路1〇2以及一切 換電路104。 "〇DMA\PCD〇CS\TPEDMS\41528\1 4 201029325 【0004]輪出緩衝電路1〇2係包含第一放大器電路n〇與第二放大 器電路120。第一放大器電路丨10係接收從一 D/A轉換器(未顯示) 所輸入的第一輸入訊號SI1，並且提供第一輸出訊號s〇1以驅動 一顯示器面板之一源極線。類似地，第二放大器電路120係接收 從上述D/A轉換器所輸入的第二輸入訊號SI2，並且提供第二輸 出訊號S02以驅動該顯示器面板之另一源極線。 [❶005】s亥第一放大器電路110係搞合於一較高電源VDDA與一較 低電源VSSA之間。典型上，該第一放大器電路11〇係包含一輸 入級(未顯示），譬如是一差動對，用以接收該第一輸入訊號SI1與 *亥第一輸出訊號SOI ’以及還包含一輸出級(未顯示），用以提供該 第一輸出訊號SOI ’其中該輸入級及輸出級係皆耦合於該較高電 源VDDA與該較低電源VSSA之間。類似地，該第二放大器電路 120係耦合於該較高電源vdda與該較低電源vssa之間。該第 一放大器電路120典型上係包含一輸入級(未顯示），譬如是一差動 對，用以接收該第二輸入訊號SI2與該第二輸出訊號s〇2，以及 還包含一輸出級(未顯示），用以提供該第二輸出訊號s〇2，其中該 輸入級及輸出級係皆耦合於該較高電源VDDA與該較低電源 VSSA之間。因此’該第一及第二放大器電路11〇及12〇兩者皆可 於介於VSSA與vdda之間的輸出驅動範圍上來驅動該顯示器面 板。 ::ODMA\PCDOCS\TPEDMS\41528\l 5 201029325 【0006】假設在長時間下， ^ch arge\ 〉-〈^fecAargd〉* 其中〈 ^ch arg el 〉與〈^cAargei〉刀 別代表平均充電電流與平均放電電流’則第一放大器電路u〇之 輸出級的平均功率消耗可以表示為： (m—HvDDA-VA、 ^disch arg el 〉x (L=〈 W丨〉♦應-隠） 其中L代表第一輸出訊號s〇1之電壓。 [0007] ^ge2)=^e2), ^t 別代表平均充電電流與平均放電電流，則第二放大器電路120之 輸出級的平均功率消耗可以表示為： (P) = (^/, arge2) X (VDDA ~V02) + ) x (F〇2 _ VSSA) = ^ χ {ν〇ϋΑ _ VSSA^ 其中匕2代表第二輸出訊號S〇2之電塵。 [0008】切換電路104係包含第一開關哪與第二開關撕，兩者 接文-控制峨SCTRL之控制。該第-關SW1係控制第一放 大盗電路110與顯示器面板上的源極線之間的搞合。類似地，該 第-開關SW2係控制第二放大n電路m與顯示器面板上的源極 線之間的耦合。藉由將該控制訊號SCTRL切換於不同位準之間， 該第-及第二放大H電路11G及12G可以輪流驅動該顯示器面板 上之不同源極線。 _9]-般而言，設計源極驅動器裝置刚時所考慮之限制條件 可包含：雜驅動輯於顯示器面板上龐大負載的驅動能力、源 ::ODMA\PCDOCS\TPEDMS\41528\1 6 201029325 極驅動器裝置100之動態與穩態功率消耗、源極驅動器1⑻設計 與製造之複雜度，以及/或緩衝電路之結構/操作的其他特徵。然 而，上述的源極驅動器裝置100無法理想地滿足以上所有的設計 限制條件，尤其是功率消耗。 【發明内容】 【0010】在此係描述一種具有低功率消耗之驅動器裝置之緩衝器電 鲁路、一種放大器裝置，以及一種應用該緩衝器電路之顯示器裝置。 【0011】根據一方面，一種驅動器裝置之輸出緩衝電路，其用於一 顯示器，包括第一放大器電路，其包含一第一輸入級，其耦合於 一較高電源與一較低電源之間，以及包含一第一輸出級，其耦合 於該較咼電源與一第一中間電源之間，其中該第一中間電源係高 於該較低電源’以及包括第二放大器電路，其包含一第二輸入級， 其耦合於該較高電源與該較低電源之間，以及包含一第二輸出 © 級，其耦合於一第二中間電源與該較低電源之間，其中該第二中 間電源係低於該較高電源。 [0012】根據另一方面，一種放大器裝置包括一輸入級，其耦合於 第一及第二電源之間，以及一輸出級，其耦合於第三及第四電源 之間，其中該第三及第四電源當中至少之一係不同於該第一及第 一電源當中任一電源。 ：：〇DMA\PCDOCS\TPEDMS\41528\l 7 201029325 [0013】上述及其他特徵、方面，以及實施例係於以下實施方式中 描述。 【實施方式】 [0014】第2圖是依據一實施例之一範例源極驅動器裝置之一示意 圖。於第2圖中，—源極驅動器裝置200可以配置來驅動一顯示 器面板(未顯示）’並且可包含一輸出緩衝電路202以及一切換電路 204。 [0015】輸出緩衝電路2〇2可包含第一放大器裝置21〇與第二放大 器裝置220。此第一放大器裝置210可以配置來接收由一 D/A轉 換器(未顯示)所輸出之第一輸入訊號sn，並且於一第一輸出節點 〇1提供第一輸出訊號s〇1，方以在第一輸出驅動範圍(即第一輸出 訊號SOI之電壓範圍)上驅動該顯示器面板。類似地此第二放大 器裝置22〇可以配置來接收倾騰轉換器所輪出之第二輸入訊 ®號SI2，並且於一第二輸出節點02提供第二輸出訊號S〇2，方以 在第二輸出驅動範圍(即第二輸出訊號S02之電壓範圍)上驅動該 顯示器面板。於較佳的情況下，該第—輸出驅動範圍係佔據一整 體輸出驅動範圍之較上方之部分，而該第二輸出驅練圍係佔ς 該整體輸出驅動範圍之較下方之部份。於更佳之情況下，該第一 及第二輸出驅動範圍係分別佔據—整體輸出驅動範圍之上:部與 ：：〇DMA\PCD〇CS\TPEDMS\41528\1 8 201029325 [0016丨於第2圖中，切換電路204可耦合於第一及第二放大器電 路210及220以及該顯示器面板之間，並且可配置來控制該第一 及第二放大器電路210及220以及該顯示器面板上的源極線之間 的耦合。舉例而言，該切換電路204可以實踐成為一多工器，該 多工器包含第一開關SW1與第二開關SW2,該第一及第二開關 SW1及SW2受一控制訊號SCTRL之控制。當控制訊號SCTRL 對應於第一位準時，該第一開關SW1可以耦合至該顯示器面板上 ❹ 之第一源極線輸入FIRST一IN，而當控制訊號SCTRL對應於第二 位準時’該第一開關SW1可以柄合至該顯示器面板上之第二源極 線輸入SECOND_IN。反之，當控制訊號SCTRL對應於第一位準 時’該第二開關SW2可以輕合至該顯示器面板上之第二源極線輸 入SECONDJN，而當控制訊號SCTRL對應於第二位準時，該第 二開關SW2可以耦合至該顯示器面板上之第一源極線輸入 FIRSTJN。由於控制訊號SCTRL於第一及第二位準之間切換， ❿第一及第二放大器電路21〇及220可輪流耦合至該第一及第二源 極線輸入FIRST一IN及SECOND_IN之間不同的源極線輪入，以驅 動不同之源極線。 [0017】第一放大器210可包含第一輸入級212與第一輸出級214。 該第一輸入級212可包含一較高電源節點pil，其可耦合至一較高 電源VDDA，以及包含一較低電源節點P12，其可耦合至一較低 電源VSSA。 ：：ODMA\PCDOCS\TPEDMS\41528\l 9 201029325 【❶❶18】5亥第一輸出級214可包含-較高電源節點P13，其可柄合至 該較冋電源VDDA ’以及包含一中間電源節點ρΐ4，其可耦合至 一第一中間電源VCA1。該第一中間電源VCA1之位準可高於該 較低電源之位準。舉例而言，該第一中間電源VCA1可介於vssa 與VDDA之間，並且較佳的情況是等於(VDDA+VSSA)/2。 [〇〇19】此外’第一輸入級212可包含-非反相輸入節點IN1(+)， ❹其可耦合至該第一輸入訊號sn，以及包含一反相輸入節點 !N1(-)，其可耦合至該第一輸出節點〇卜在此，舉例而言，該第 一放大器電路210可以配置成具有單位增益(Unity Gain)。 【〇〇2〇】第-輸入級212可配置來依據該非反相輸入節點啊+)與 反相輸入節點INl(-)之電壓位準來操作。此外，第一輸入級212， 其耦合於該較高電源VDDA與該較低電源VSSA之間，可以配置 為操作於一操作範圍，而該操作範圍可由該較高電源VDDA與該 鲁較低電源VSSA來侷限。舉例而言，該第一輸入級212可包含一 放大電路，譬如是一種包含差動對之差動放大器。對於第一放大 器電路210建構成單位增益之放大器的情況而言，可將第一輸入 級212之輸入電晶體最佳化來操作於上述之第一輸出驅動範圍。 舉例而言，該差動對可包含N型之差動輸入電晶體，而這些]^型 差動輸入電晶體可於一個佔據整體驅動範圍之較上方部分的第一 輸出驅動範圍上來操作。 ：：〇DMA\PCDOCS\TPEDMS\41528\l 10 201029325 [0021]第-輸出級214 ’其可直接或間絲合至該第一輸入級 212 ’可以配置來提供第一輸出訊號SOI以驅動顯示器面板。舉例 而吕，第一輸出級214可包含一驅動電路，其根據第一輸入級212 之一輸出訊號來驅動該顯示器面板。該第一輸出級214可包含一 介於該較高電源節點Ρ13與該第一輸出節點01之間的充電路徑， 以及一介於該第一輸出節點01與該中間電源節點Ρ14之間的放電 路徑。因此’上述第一輸出級214用來驅動顯示器裝置的第一輸 豢出驅動範圍，即第一輸出訊號SOI之驅動範圍，可以藉由第一中 間電源VCA1與較高電源vdDA來侷限。 【0022】該充電路徑可以實踐為一電流源，該電流源可提供一從較 咼電源節點P13流至第一輸出節點〇ι之電流，以對該第一輸出節 點οι進行充電。而該放電路徑可以實踐為一電流 Sink) ’該電流槽可令電流從該第·—.輸出節點〇1流入該中間電源 節點P14，以對該第一輸出節點〇1進行放電。 ❹ [0023】舉例而言’當位於非反相輸入節點取1(+)之第一輸入訊號 SI1之位準南於编合至反相輸入卸點IN1㈠之第一輸出訊梦· 時’第一輸出級214之充電路徑會導通，而對顯示器面板上之輸 出負載進行充電，藉以拉高第一輸出訊號SOI之位準。反之，當 位於非反相輸入節點IN1(+)之第一輸入訊號SI1之位準低於輛合 至反相輸入節點INl(-)之第一輸出訊號S01時，第一輪出級214 ：：〇DMA\PCDOCS\TPEDMS\41528\ 1 11 201029325 之放電路徑會導通，而對顯示器面板上之輸出負載進行放電，藉 以拉低第一輪出訊號SOI之位準。 【0024】第一放大器220可包含第二輸入級222與第二輸出級224。 該第二輸入級222可包含一較高電源節點P21，其可耦合至上述之 較咼電源VDDA，以及包含一較低電源節點P22，其可耦合至上 述之較低電源VSSA。 ❹ 丨0025】該第二輸出級224可包含一較高電源節點P23,其可耦合至 一第二中間電源VCA2，以及包含一中間電源節點p24，其可耦合 至該較低電源VSSA。該第二中間電源VCA2之位準可低於該較 高電源之位準。舉例而言，該第二中間電源VCA2可介於VSSA 與VDDA之間，並且較佳的情況是等於(VDDA+VSSA)/2。在此， 舉例而言，該輸出級212與224可共享一個與該較高及較低電源 等距之通用電源。 β【0026】第二輸入級222可包含一非反相輸入節點ΙΝ2(+)，其可耦 合至該第二輸入訊號SI2，以及包含一反相輸入節點ΙΝ2(_)，其可 柄合至該第一輸出節點〇2。在此，舉例而言，該第二放大器電路 220可以配置成具有單位增益。 [0027]第二輸入級222可配置來依據該非反相輸入節點ΙΝ2(+)與 反相輸入節點ΙΝ2(-)之電壓位準來操作。此外，第二輸入級222， 其耦合於該較高電源VDDA與該較低電源VSSA之間，可以配置 ::ODMA\PCDOCS\TPEDMS\41528\1 12 201029325 成操作於—操作範圍，碰猶_可由雜高魏VDDA與該 較低電源顺來揭限。舉例而言，該第二輸入級222可包含- 放大電路，#如是—種包含差動對之差械大ϋ。對於第二放大 器電路220建構成單位增益之放大器的情況而言可將第二輸入 級222之輸入電晶體最佳化來操作於上述之第二輸出驅動細。 舉例而言’該差動對可包含ρ型之差動輸人電晶體，而這些ρ型 差動輸入電晶體可於一個佔據整體驅動範圍之較下部份的第二輸 ❹ 出驅動把圍之上來操作。 ❹ 【0028】第二輪出級224 ’其可直接或間接耗合至該第二輸入級 222 ’可以配置來提供第二輪出訊號s〇2以驅動顯示器面板。舉例 而言，第二輸出級224可包含一驅動電路，方以根據第二輸入級 222之-輸出訊號來驅動該顯示器面板。該第二輸出級似可包含 -介於該第二中間電源節點p23與該第二輸出節點〇2之間的充電 路徑，以及-介於該第二輸出節點〇2與該較低電源節點似之間 的放電路仏目此，邊第二輪出級224用來驅動顯示器裝置的第 二輸出驅動祕，即第二輪出訊號迎之驅動卿，可以藉由上 述第二中間電源篇2與較低電源VSSA來侷限。 【繼該充電雜可以實賤為1親，該賴源可提供一從中 間電源即點P23 至第一輪出節點〇2之電流，以對該第二輸出節 點〇2進行充電。_玫電路柯以實踐為-電流槽(Current ：：〇DMA\PCDOCS\TPEDMS\41528\l 13 201029325201029325 VI. Description of the Invention: [Technical Field of the Invention] [0001] The embodiments described herein relate to a display device, and more particularly to an output buffer circuit of an actuator device, an amplifier device, and a use of the same A display device that outputs a buffer circuit. [Prior Art] Φ 丨 0002] In general, under the development of precision, lightweight, low-power and high-quality display devices, low-power consumption, high-speed, high-resolution, and large-volume liquid crystal displays ( The demand for Liquid Crystal Display; LCD) devices is increasing. LCD drivers are commonly composed of a source driver, a gate driver, a controller, and a reference power supply. These source drivers play a particularly important role in meeting these needs, and these source drivers include scratchpads, data latches, digital-to-analog converters (DACs), and output buffers. These output buffers determine the source driver's rate, resolution, voltage range, and power dissipation. Since a single-chip has a large number of output buffers (typically hundreds of), each output buffer must occupy only a small area of the wafer while its power consumption must be low enough. I-face 31 is a schematic diagram of a conventional source driver device. In Fig. i, a conventional source driver device system includes a round-out buffer circuit 1〇2 and an all-in circuit 104. "〇DMA\PCD〇CS\TPEDMS\41528\1 4 201029325 [0004] The wheel snubber circuit 1〇2 includes a first amplifier circuit n〇 and a second amplifier circuit 120. The first amplifier circuit 10 receives the first input signal SI1 input from a D/A converter (not shown) and provides a first output signal s〇1 to drive a source line of a display panel. Similarly, the second amplifier circuit 120 receives the second input signal SI2 input from the D/A converter and provides a second output signal S02 to drive the other source line of the display panel. [❶005] The first amplifier circuit 110 of the shai is engaged between a higher power supply VDDA and a lower power supply VSSA. Typically, the first amplifier circuit 11 includes an input stage (not shown), such as a differential pair, for receiving the first input signal SI1 and the first output signal SOI ' and also includes an output. a stage (not shown) for providing the first output signal SOI 'where the input stage and the output stage are both coupled between the higher power supply VDDA and the lower power supply VSSA. Similarly, the second amplifier circuit 120 is coupled between the higher power supply vdda and the lower power supply vssa. The first amplifier circuit 120 typically includes an input stage (not shown), such as a differential pair, for receiving the second input signal SI2 and the second output signal s〇2, and an output stage (not shown) for providing the second output signal s〇2, wherein the input stage and the output stage are both coupled between the higher power supply VDDA and the lower power supply VSSA. Thus, both the first and second amplifier circuits 11A and 12A can drive the display panel over an output drive range between VSSA and vdda. ::ODMA\PCDOCS\TPEDMS\41528\l 5 201029325 [0006] Assume that for a long time, ^ch arge\ 〉-<^fecAargd>* where < ^ch arg el > and <^cAargei> represent the average charge The current and the average discharge current' then the average power consumption of the output stage of the first amplifier circuit u〇 can be expressed as: (m−HvDDA-VA, ^disch arg el 〉x (L=<W丨>♦ should-隠) L represents the voltage of the first output signal s 〇 1. [0007] ^ge2) = ^e2), ^t represents the average charging current and the average discharging current, and the average power consumption of the output stage of the second amplifier circuit 120 can be expressed. It is: (P) = (^/, arge2) X (VDDA ~V02) + ) x (F〇2 _ VSSA) = ^ χ {ν〇ϋΑ _ VSSA^ where 匕2 represents the second output signal S〇2 Electric dust. [0008] The switching circuit 104 includes the first switch which is torn from the second switch, and the two are controlled by the control-SCTRL. The first-off SW1 controls the engagement between the first thief circuit 110 and the source line on the display panel. Similarly, the first switch SW2 controls the coupling between the second amplification n-circuit m and the source line on the display panel. By switching the control signal SCTRL between different levels, the first and second amplification H circuits 11G and 12G can alternately drive different source lines on the display panel. _9] In general, the constraints considered when designing the source driver device can include: the drive capability of the hybrid driver on the large load on the display panel, source: ODMA\PCDOCS\TPEDMS\41528\1 6 201029325 The dynamic and steady state power consumption of the driver device 100, the complexity of the design and manufacture of the source driver 1 (8), and/or other features of the structure/operation of the buffer circuit. However, the source driver device 100 described above does not ideally meet all of the above design constraints, particularly power consumption. SUMMARY OF THE INVENTION [0010] Here, a buffer circuit of a driver device having low power consumption, an amplifier device, and a display device to which the buffer circuit is applied are described. [0011] According to one aspect, an output buffer circuit of a driver device for a display includes a first amplifier circuit including a first input stage coupled between a higher power source and a lower power source, And including a first output stage coupled between the second power supply and a first intermediate power supply, wherein the first intermediate power supply is higher than the lower power supply and includes a second amplifier circuit including a second An input stage coupled between the higher power source and the lower power source and including a second output© stage coupled between a second intermediate power source and the lower power source, wherein the second intermediate power source is Below this higher power supply. [0012] According to another aspect, an amplifier apparatus includes an input stage coupled between a first and a second power source, and an output stage coupled between the third and fourth power sources, wherein the third At least one of the fourth power sources is different from any of the first and first power sources. ::〇DMA\PCDOCS\TPEDMS\41528\l 7 201029325 [0013] The above and other features, aspects, and embodiments are described in the following embodiments. [Embodiment] FIG. 2 is a schematic view showing an example of a source driver device according to an embodiment of the present invention. In Fig. 2, the source driver device 200 can be configured to drive a display panel (not shown) and can include an output buffer circuit 202 and a switching circuit 204. The output buffer circuit 2〇2 may include a first amplifier device 21〇 and a second amplifier device 220. The first amplifier device 210 can be configured to receive the first input signal sn output by a D/A converter (not shown), and provide the first output signal s〇1 at a first output node ,1. The display panel is driven over a first output drive range (ie, a voltage range of the first output signal SOI). Similarly, the second amplifier device 22A can be configured to receive the second input signal SI2 rotated by the tilt converter, and provide the second output signal S〇2 at a second output node 02. The display panel is driven on the output drive range (ie, the voltage range of the second output signal S02). Preferably, the first output drive range occupies an upper portion of an overall output drive range, and the second output drive wrap occupies a lower portion of the overall output drive range. In a better case, the first and second output driving ranges respectively occupy the above-mentioned overall output driving range: part::〇DMA\PCD〇CS\TPEDMS\41528\1 8 201029325 [0016丨第第2 In the figure, the switching circuit 204 can be coupled between the first and second amplifier circuits 210 and 220 and the display panel, and can be configured to control the first and second amplifier circuits 210 and 220 and the source on the display panel. Coupling between lines. For example, the switching circuit 204 can be implemented as a multiplexer including a first switch SW1 and a second switch SW2, and the first and second switches SW1 and SW2 are controlled by a control signal SCTRL. When the control signal SCTRL corresponds to the first level, the first switch SW1 can be coupled to the first source line input FIRST-IN on the display panel, and when the control signal SCTRL corresponds to the second level, the first The switch SW1 can be shank to the second source line input SECOND_IN on the display panel. Conversely, when the control signal SCTRL corresponds to the first level, the second switch SW2 can be lightly coupled to the second source line input SECONDJN on the display panel, and when the control signal SCTRL corresponds to the second level, the second Switch SW2 can be coupled to a first source line input FIRSTJN on the display panel. Since the control signal SCTRL is switched between the first and second levels, the first and second amplifier circuits 21 and 220 can be alternately coupled to the first and second source line inputs FIRST-IN and SECOND_IN. The source line is wheeled in to drive different source lines. The first amplifier 210 can include a first input stage 212 and a first output stage 214. The first input stage 212 can include a higher power supply node pil that can be coupled to a higher power supply VDDA and a lower power supply node P12 that can be coupled to a lower power supply VSSA. ::ODMA\PCDOCS\TPEDMS\41528\l 9 201029325 [❶❶18] The 5th first output stage 214 can include a higher power supply node P13 that can be coupled to the lower power supply VDDA 'and includes an intermediate power supply node ρΐ4 It can be coupled to a first intermediate power source VCA1. The level of the first intermediate power source VCA1 can be higher than the level of the lower power source. For example, the first intermediate power source VCA1 can be between vssa and VDDA, and is preferably equal to (VDDA + VSSA)/2. [19] Further, the first input stage 212 can include a non-inverting input node IN1(+) that can be coupled to the first input signal sn and includes an inverting input node !N1(-), It can be coupled to the first output node. Here, for example, the first amplifier circuit 210 can be configured to have a unity gain (Unity Gain). [第2〇] The first input stage 212 is configurable to operate in accordance with the voltage level of the non-inverting input node +) and the inverting input node IN1 (-). In addition, the first input stage 212, coupled between the higher power supply VDDA and the lower power supply VSSA, can be configured to operate in an operating range, and the operating range can be from the higher power supply VDDA and the lower power supply VSSA is limited. For example, the first input stage 212 can include an amplifying circuit, such as a differential amplifier including a differential pair. In the case where the first amplifier circuit 210 is constructed as an amplifier constituting unity gain, the input transistor of the first input stage 212 can be optimized to operate in the first output drive range described above. For example, the differential pair can include an N-type differential input transistor, and the differential input transistors can operate over a first output drive range that occupies an upper portion of the overall drive range. ::〇DMA\PCDOCS\TPEDMS\41528\l 10 201029325 [0021] The first output stage 214 'which may be directly or indirectly wired to the first input stage 212' may be configured to provide a first output signal SOI to drive the display panel. For example, the first output stage 214 can include a driving circuit that drives the display panel according to one of the output signals of the first input stage 212. The first output stage 214 can include a charging path between the higher power node Ρ13 and the first output node 01, and a discharge path between the first output node 01 and the intermediate power node Ρ14. Therefore, the first output stage 214 used to drive the first output driving range of the display device, that is, the driving range of the first output signal SOI, can be limited by the first intermediate power source VCA1 and the higher power source vdDA. [0022] The charging path can be practiced as a current source that provides a current flow from the higher power supply node P13 to the first output node 以 to charge the first output node οι. The discharge path can be practiced as a current sink. The current slot allows current to flow from the first output node 〇1 to the intermediate power supply node P14 to discharge the first output node 〇1. ❹ [0023] For example, 'When the non-inverting input node takes 1 (+), the first input signal SI1 is located south of the first output of the inverting input unloading point IN1 (1). The charging path of an output stage 214 is turned on, and the output load on the display panel is charged to raise the level of the first output signal SOI. Conversely, when the level of the first input signal SI1 at the non-inverting input node IN1(+) is lower than the first output signal S01 of the inverting input node IN1(-), the first round is output 214: :〇DMA\PCDOCS\TPEDMS\41528\ 1 11 201029325 The discharge path will be turned on, and the output load on the display panel will be discharged to lower the level of the first round of signal SOI. The first amplifier 220 can include a second input stage 222 and a second output stage 224. The second input stage 222 can include a higher power supply node P21 that can be coupled to the higher power supply VDDA and a lower power supply node P22 that can be coupled to the lower power supply VSSA. The second output stage 224 can include a higher power supply node P23 that can be coupled to a second intermediate power supply VCA2 and that includes an intermediate power supply node p24 that can be coupled to the lower power supply VSSA. The level of the second intermediate power source VCA2 can be lower than the level of the higher power source. For example, the second intermediate power source VCA2 can be between VSSA and VDDA, and is preferably equal to (VDDA + VSSA)/2. Here, for example, the output stages 212 and 224 can share a common power source that is equidistant from the higher and lower power supplies. [0026] The second input stage 222 can include a non-inverting input node ΙΝ2(+) coupled to the second input signal SI2 and including an inverting input node ΙΝ2(_) stalkable to The first output node 〇2. Here, for example, the second amplifier circuit 220 can be configured to have a unity gain. The second input stage 222 is configurable to operate in accordance with the voltage level of the non-inverting input node ΙΝ2(+) and the inverting input node ΙΝ2(-). In addition, the second input stage 222 is coupled between the higher power supply VDDA and the lower power supply VSSA, and can be configured with: ODMA\PCDOCS\TPEDMS\41528\1 12 201029325 into operation-operating range, It can be limited by the high wei VDDA and the lower power supply. For example, the second input stage 222 can include an amplifying circuit, such as a differential that includes a differential pair. In the case where the second amplifier circuit 220 is constructed as an amplifier constituting unity gain, the input transistor of the second input stage 222 can be optimized to operate in the second output drive fine. For example, the differential pair may comprise a p-type differential input transistor, and the p-type differential input transistor may be driven by a second output drive that occupies a lower portion of the overall drive range. Operate on top. [0028] The second round of the stage 224' can be directly or indirectly consuming to the second input stage 222' can be configured to provide a second round of signal s〇2 to drive the display panel. For example, the second output stage 224 can include a driver circuit for driving the display panel based on the output signal of the second input stage 222. The second output stage may comprise - a charging path between the second intermediate power supply node p23 and the second output node 〇 2, and - between the second output node 〇 2 and the lower power supply node Between the two circuits, the second output stage 224 is used to drive the second output driver of the display device, that is, the second round of the signal is driven by the driver, which can be performed by the second intermediate power supply 2 The lower power VSSA is limited. [The charge can be implemented as a parent, and the source can provide a current from the intermediate power source, point P23, to the first round node 〇2 to charge the second output node 〇2. _ 玫 circuit Ke to practice as - current slot (Current ::〇 DMA\PCDOCS\TPEDMS\41528\l 13 201029325
Smk) ’該電麟可令賴帛二糾祕〇2叙雜低電源 節點P24 ’以對該第二輸出節點〇2進行放電。 [0030】舉例而言，當位於非反相輸入節點m2(+)之第二輸入訊號 SI2之位準高於轉合至反相輸入節點脱㈠之第二輸出訊號s〇2 時’第二輸出級224之充電路徑會導通，而對顯示器面板上之輸 出負載進行充電’藉以拉高第二輸出訊號s〇2之位準。反之，當 ❹位於非反相輸入節點IN2㈩之第二輸入訊號SI2之位準低於耗合 至反相輸入節點IN2㈠之第二輸出峨微日寺，第二輸出級 之放電路徑會導通’而對顯示器面板上之輸出負載進行放電，藉 以拉低第二輸出訊號S〇2之位準。 【003較益於上述對於該第一輸出級214所作之電源安排，該筹 -放大器電路21G可因其輸出驅動範圍(紐於VCA1與 之間)較第—放Α||電路丨⑽i圖)之輸出驅動酬偈限於 VCCA與VDDA之間)還小，而於動態功率消耗上有所縮減。更明 確言之’第-放大器電路110與·兩者之輸人級，皆操作於一 偈限於VDDA與職之間的操作範圍上，因而可具有相同之功 率消耗。另-方面，第-放大器電路21〇之第一輸出級214對於 充電過程可具有_之_功率雜，但雜放電過糊具有較 低之功率耗損。整體而言，第—放大器電路別可彻較小之總 功率消耗來操作。 ::ODMA\PCD〇CS\TPEDMS\41528\l 14 201029325 [0032】於第2圖中，第一輸入級212在第一放大器電路21〇之總 功率耗損中佔了較次要之角色，原因在於第一輸出級212乃以一 穩態電流來操作，而相較對於該顯示器面板必須具備足夠驅動能 力的第一輸出級214之操作電流而言，該穩態電流可低得多。由 於在動態功率消耗降低上有所貢獻的第一輸出級214是佔了第一 放大器電路210之總功率耗損的主要地位，因此第一放大器電路 210總功率耗知可以有相當大的比例被節省下來。 【0033]舉例而言’以vca1=(v〇da+vssa)/2的情況來說，並假設在長 寺間下〉= Ο——〉，其中〈/rf,argd〉與㈣〉分別代表平均充電 電流與平均放電電流’則第一放大器電路21〇内之第一輸出級 之平均功率消耗為： (ρ) = (1〇,^) X {VDDA -Vol)+ (idischugei^ χ {ν〇λ _ VCAl) = ^ x ^fdda _ VCA^ =(^arg.i) x {VDDA - VSSA)/2. . ❹結果’相較於第一放大器電路110的輸出級(第i圖内)而言，第一 輸出級214可具有僅僅一半的功率消耗。 【0034】類似地，受益於上述對於該第二輸出級224所作之電源安 排’該第二放大器電路220可因其輪出驅動範圍(侷限於辦A與 VCA2之間)較第二放大器電路12〇(第i圖)之輸出驅動範圍(偈限 於VCCA與彻A之間)還小，而於動態功率消耗上有所縮減。 更明碟言之，第二放大器電路120與22〇兩者之輸入級，皆操作 ::ODMA\PCDOCS\TPEDMS\41528\1 15 201029325 於-偈限於VDDA與VSSA之間的操作範圍上，因而可具有相同 之功率消耗。另-方面，第二放大器電路22〇之第二輸出級似 對於放電過程可具有相同之動態功率消耗，但對於充電過糊具 有較低之轉_。整體而言，第二放大^電路⑽可利用較小 之總功率消耗來操作。 【5]於第2圖中’第二輸入級222在第二放大器電路咖之總 籲力率耗損中佔了較次要之角色，原因在於第二輸入級Μ2乃以一 穩態電流來操作’ _較騎該齡器面板必須具備足夠驅動能 力的第二輸出級224之操作電流而言該穩態電流可低得多。由 於在動態功率消耗降低上有所貢獻的第二輸出級224是佔了第二 放大器電路220之總功率耗損的主要地位，因此第二放大器電路 220總功率耗損可以有相當大的比例被節省下來。 [0036】舉例而言，以 VCA2=(vdda+vssa_ ❹時間下，〈W2卜2〉，其中〈‘〉與“㈣〉分別代表平均充電 電流與平均放電電流’則第二放大器電路22〇内之第二輸出級224 之平均功率消耗為： (){ Ch^e2) x {VCA2 ν〇2) + {idischatse2 ^ x (y〇2 _ VSSA) = (i'cAarge2) x {VDDA - VCAl) ◊•c/iarge2〉X {VDDA-VSSA)/2. 尨果’相較於第二放大器電路12〇的輸出級(第i圖内）而言，第二 輸出級224可具有僅僅一半的功率消耗。 ；：〇DMAVPCDOCS\TPEDMS\41528\1 16 201029325 [0037J總結來說，由於第一輸出級214具有上述輕合至第一中間 電源VCA1而_合至較低電源VSSA之放電路徑，因此第一放 大器電路210放電過程之動態功率耗損可以有效地節省下來。此 外’由於第二輸出級224具有上述輕合至第二中間電源VCA2而 非耦合至較高電源VDDA之充電路徑，因此第二放大器電路22〇 充電過程之動態功率耗損可以有效地節省下來。整體而言，源極 驅動器裝置200之總功率消耗相較於傳統源極驅動器裝置1〇〇可 # 以有效地降低。 【0038]雖然上述第一及第二放大器電路21〇及22〇係顯示為單位 增益放大器電路，然而其他種配置是可能的。唯一的要求可以是 其中一個放大器電路包含一個耦合於VSSA與Vj^DA的輸入級以 及一個麵合於VCA1(大於VSSA)與VDDA之間的輸出級，以及另 外一個放大器包含一個耦合於VSSA與VDDA的輸入級以及一個 麵合於VSSA與VCA2(低於VDDA)之間的輸出級。因此，種種不 同的放大器電路’譬如是反相放大器電路，均可以使用。 [0039]第3圖係依據另一實施例的另一範例源極驅動器裝置。於 第3圖中’一源極驅動器裝置300可以配置為包含一輸出缓衝電 路302，其包含第一放大器電路310與第二放大器電路320，以及 一切換電路204。在此’源極驅動器裝置3〇〇可以與源極驅動器裝 置200(第2圖内)實質上相似，差別僅在於第一及第二放大器電路 310及320可配置成反相放大器電路而非單位增益放大器電路210 ::ODMA\PCDOCS\TPEDMS\41528\l 17 201029325 及220(第2圖内）。第2及3圖内類似元件與節點乃利用相同的參 照數字和符號來加以標示。 [0040】與第一及第二放大器電路210及22〇(第2圖内)實質上類 似，第-放大器電路3H)可以配置來提供第一輸出訊號咖，以 於一由VCA1及VDDA來侷限的第一輸出驅動範圍之上，來驅動 一顯示器面板’以及第一放大器電路320可以配置來提供第一輸 • A訊號S02，以於-由VSSA及VCA2來侷限的第二輸出驅動範 圍之上，來驅動該顯示器面板。 【0041]第一放大器電路310可包含兩個電阻rii及，以及一 放大器電路210。電阻R11可耦合於一第一輸入訊號SI1與該第一 放大器電路210之"-反相輸入卽點INl(-)之間。電阻R12可轉人 於該反相輸入節點INl(-)與該第一放大器電路21〇之一輸出節點 ΟΙ之間。因此’第一放大器電路310可以具有一取決於電阻R11 ❹ 及R12之增益。 [0042】第二放大器電路320可包含兩個電阻R2i及R22，以及一 放大器電路220。電阻R21可耦合於一第二輸入訊號SI2與該第一 放大器電路220之一反相輸入節點IN2(-)之間。電阻R22可麵合 於該反相輸入節點IN2(-)與該第二放大器電路220之一輸出節點 02之間。因此’第二放大器電路320可以具有一取決於電阻R21 及R22之增益。 ::ODMA\PCD〇CS\TPEDMS\41528\1 18 201029325 [00431由於第一及第二放大器電路32〇及33〇分別保持第一及第 '一放大器電路21〇及220(第2圖内），因此源極驅動器裝置3〇〇(第 3圖内)之功率消耗可因類似的理由而降低。 [0044】第4圖係顯示依據一實施例之一範例顯示器裝置之示意性 方塊圖。於第4圖中，一顯示器裝置400可採用上述之源極驅動 器裝置200或300’並且可包含一源極驅動器410與一顯示器面板 420。顯示器面板420可包含複數條源極線，當中包含源極線SL1 及SL2，以及複數條閘極線，即gli至GLn，其中n為一非零整 數。此源極驅動器410可配置來驅動該顯示器面板420上之該等 源極線，並且可利用上述之源極驅動器裝置2〇〇(第2圖内）或該源 極驅動器裝置300(於第3圖内)來加以實踐。明確言之，源極驅動 器410可包含一輸出緩衝器電路420’其可實踐成為上述之輸出緩 衝電路202(第2圖内）或輸出緩衝電路302，以及包含上述之切換 電路204(於第2圖或第3圖内）。 【0045】雖然依據上述範例性實施例之源極驅動器裝置2〇〇及3〇〇 係描述成用來驅動一顯示器面板’然而源極驅動器裝置2〇〇及300 亦可用作種種不同之應用。 [0046】雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明’任何熟習此技藝者，在不脫離本發明之精神和範圍内， 當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申 請專利範圍所界定者為準。 ：:ODMA\PCDOCS\TPEDMS\41528\l 19 201029325 【圖式簡單說明】 【0047】根據本發明的各種特點、功能錢實關，皆可以從上述 詳細說明’並_參考所關式*達較佳之雜，該等圖式係包 含： 【0048】第1圖係依據一實施例之—顯示器裝置之方塊圖。 [0049】第2圖係一時序圖，其顯示第1圖之顯示器裝置1〇〇之代 ❹ 表訊號之波形之一實施例。 【主要元件符號說明】 102〜輸出緩衝電路 110〜第一放大器電路 200〜源極驅動器装置 204〜切換電路 212〜第一輸入級 220〜第二放大器電路 224〜第二輸出級 302〜輸出緩衝電路 320〜第二放大器電路 IN(+)、IN1(+)、IN2(+)〜非反相 輸入節點 Pll、P13、P21〜較高電源節點 P14、P23〜中間電源節點 SCTRL〜控制訊號 SI1-第一輸入訊號 SOI〜第一輸出訊號 SW1〜第一開關 VCA1〜第一中間電源 100〜源極驅動器裴置 104〜切換電路 120〜第二放大器電路 202〜輸出緩衝電路 210〜第一放大器電路 214〜第一輸出級 222〜第二輸入級 ❹ 300〜源極驅動器裝置 310〜第一放大器電路 IN(-)、IN1 ㈠、IN2(-)〜反相輸 入節點 FIRST_IN〜第一源極線輸入 P12、P22、P24〜較低電源節點 RU、R12、R2卜R22〜電阻 SECOND_IN〜第二源極線輸入 SI2〜第二輸入訊號 S02〜第二輸出訊號 SW2〜第二開關 ::ODMA\PCDOCS\TPEDMS\41528M 20 201029325 VC A2〜第二中間電源 VDD A〜較高電源 VS S A〜較低電源Smk) 'The electric cymbal can cause the Lai 帛2 to correct the low power supply node P24' to discharge the second output node 〇2. [0030] For example, when the level of the second input signal SI2 located at the non-inverting input node m2(+) is higher than the second output signal s〇2 of the inverting input node (1), the second The charging path of the output stage 224 is turned on, and the output load on the display panel is charged 'by taking the level of the second output signal s 〇 2 high. Conversely, when the second input signal SI2 of the non-inverting input node IN2 (10) is lower than the second output of the inverting input node IN2 (1), the discharge path of the second output stage is turned on. The output load on the display panel is discharged to lower the level of the second output signal S〇2. [003] Benefiting from the above-described power arrangement for the first output stage 214, the boost-amplifier circuit 21G may be driven by its output driving range (new to VCA1 and between) - the first Α||circuit 丨(10)i) The output driver's entertainment is limited to between VCCA and VDDA), and the dynamic power consumption is reduced. More specifically, the input stages of the 'first-amplifier circuit 110' and the two are operated in a range limited to the operating range between VDDA and the like, and thus have the same power consumption. Alternatively, the first output stage 214 of the first amplifier circuit 21 may have a power mismatch for the charging process, but the miscellaneous discharge has a lower power consumption. Overall, the first-amplifier circuit can operate with a small total power consumption. ::ODMA\PCD〇CS\TPEDMS\41528\l 14 201029325 [0032] In FIG. 2, the first input stage 212 plays a less important role in the total power consumption of the first amplifier circuit 21, for the reason. The first output stage 212 operates at a steady state current that is much lower than the operating current of the first output stage 214 that must have sufficient drive capability for the display panel. Since the first output stage 214 contributing to the reduction in dynamic power consumption is the dominant position of the total power consumption of the first amplifier circuit 210, the total power consumption of the first amplifier circuit 210 can be saved in a considerable proportion. Come down. [0033] For example, 'in the case of vca1=(v〇da+vssa)/2, and suppose that under the Changsi Temple>= Ο——>, where 〈rf, argd> and (4)> respectively represent the average The charging current and the average discharging current 'the average power consumption of the first output stage in the first amplifier circuit 21〇 is: (ρ) = (1〇,^) X {VDDA -Vol)+ (idischugei^ χ {ν〇 λ _ VCAl) = ^ x ^fdda _ VCA^ = (^arg.i) x {VDDA - VSSA) / 2. The result ' is compared with the output stage of the first amplifier circuit 110 (in the figure i) That is, the first output stage 214 can have only half the power consumption. [0034] Similarly, benefiting from the power arrangement described above for the second output stage 224, the second amplifier circuit 220 can be rotated out of the drive range (limited between office A and VCA2) than the second amplifier circuit 12 The output drive range of 〇 (i) is small (between VCCA and A) and is reduced in dynamic power consumption. More specifically, the input stages of the second amplifier circuits 120 and 22 are both operated: ODMA\PCDOCS\TPEDMS\41528\1 15 201029325 The -偈 is limited to the operating range between VDDA and VSSA, thus Can have the same power consumption. Alternatively, the second output stage of the second amplifier circuit 22 may have the same dynamic power consumption for the discharge process, but has a lower turn for the charged paste. In general, the second amplification circuit (10) can operate with a smaller total power consumption. [5] In Figure 2, the second input stage 222 plays a lesser role in the total appeal rate loss of the second amplifier circuit because the second input stage Μ2 operates with a steady state current. The steady state current can be much lower in terms of the operating current of the second output stage 224, which must have sufficient drive capability to ride the panel. Since the second output stage 224 contributing to the reduction in dynamic power consumption is the dominant position of the total power consumption of the second amplifier circuit 220, the total power consumption of the second amplifier circuit 220 can be saved by a considerable proportion. . [0036] For example, with VCA2=(vdda+vssa_❹time, <W2b2>, where <'> and “(4)> respectively represent the average charging current and the average discharging current' are in the second amplifier circuit 22〇 The average power consumption of the second output stage 224 is: (){ Ch^e2) x {VCA2 ν〇2) + {idischatse2 ^ x (y〇2 _ VSSA) = (i'cAarge2) x {VDDA - VCAl) ◊•c/iarge2>X {VDDA-VSSA)/2. As a result, the second output stage 224 can have only half of the power compared to the output stage of the second amplifier circuit 12〇 (in the figure i). Consumption: ;: 〇DMAVPCDOCS\TPEDMS\41528\1 16 201029325 [0037] In summary, since the first output stage 214 has the above-mentioned light-to-first intermediate power supply VCA1 and is coupled to the lower power supply VSSA, the first The dynamic power consumption of the discharge process of an amplifier circuit 210 can be effectively saved. Further, since the second output stage 224 has the above-described charging path that is coupled to the second intermediate power source VCA2 instead of being coupled to the higher power source VDDA, the second amplifier The dynamic power consumption of the circuit 22 〇 charging process can be effectively saved. In general, the total power consumption of the source driver device 200 is effectively reduced compared to the conventional source driver device. [0038] Although the first and second amplifier circuits 21 and 22 are displayed It is a unity gain amplifier circuit, however other configurations are possible. The only requirement may be that one of the amplifier circuits includes an input stage coupled to VSSA and Vj^DA and a face-to-face between VCA1 (greater than VSSA) and VDDA. The output stage, as well as the other amplifier, includes an input stage coupled to VSSA and VDDA and an output stage that is interfaced between VSSA and VCA2 (below VDDA). Therefore, a variety of different amplifier circuits, such as inverting amplifier circuits [0039] Figure 3 is another exemplary source driver device in accordance with another embodiment. In Figure 3, a source driver device 300 can be configured to include an output buffer circuit 302. The first amplifier circuit 310 and the second amplifier circuit 320 are included, and a switching circuit 204. Here, the 'source driver device 3' can be connected to the source driver device 200 ( 2 is substantially similar except that the first and second amplifier circuits 310 and 320 can be configured as inverting amplifier circuits instead of unity gain amplifier circuits 210::ODMA\PCDOCS\TPEDMS\41528\l 17 201029325 and 220 (Figure 2). Similar elements and nodes in Figures 2 and 3 are labeled with the same reference numerals and symbols. [0040] Like the first and second amplifier circuits 210 and 22A (in FIG. 2), the first amplifier circuit 3H) can be configured to provide a first output signal to be limited by VCA1 and VDDA. Above the first output drive range, to drive a display panel 'and the first amplifier circuit 320 can be configured to provide a first output signal S02 for the second output drive range limited by VSSA and VCA2 To drive the display panel. The first amplifier circuit 310 can include two resistors rii and an amplifier circuit 210. The resistor R11 is coupled between a first input signal SI1 and the "-inverting input node IN1(-) of the first amplifier circuit 210. The resistor R12 can be transferred between the inverting input node IN1(-) and one of the output nodes ΟΙ of the first amplifier circuit 21A. Thus, the first amplifier circuit 310 can have a gain that depends on the resistors R11 and R12. The second amplifier circuit 320 can include two resistors R2i and R22, and an amplifier circuit 220. Resistor R21 can be coupled between a second input signal SI2 and one of the inverting input nodes IN2(-) of the first amplifier circuit 220. Resistor R22 can be coupled between the inverting input node IN2(-) and one of the output nodes 02 of the second amplifier circuit 220. Therefore, the second amplifier circuit 320 can have a gain depending on the resistors R21 and R22. ::ODMA\PCD〇CS\TPEDMS\41528\1 18 201029325 [00431 Since the first and second amplifier circuits 32〇 and 33〇 respectively hold the first and the first 'one amplifier circuits 21〇 and 220 (in FIG. 2) Therefore, the power consumption of the source driver device 3 (in FIG. 3) can be reduced for similar reasons. Figure 4 is a schematic block diagram showing an exemplary display device in accordance with an embodiment. In FIG. 4, a display device 400 can employ the source driver device 200 or 300' described above and can include a source driver 410 and a display panel 420. Display panel 420 can include a plurality of source lines including source lines SL1 and SL2, and a plurality of gate lines, gli to GLn, where n is a non-zero integer. The source driver 410 can be configured to drive the source lines on the display panel 420, and can utilize the source driver device 2 (in FIG. 2) or the source driver device 300 (at the third) Figure)) to practice. In particular, the source driver 410 can include an output buffer circuit 420' that can be implemented as the output buffer circuit 202 (in FIG. 2) or the output buffer circuit 302, and the switching circuit 204 described above (in the second Figure or Figure 3). [0045] Although the source driver devices 2 and 3 are described as driving a display panel in accordance with the above exemplary embodiments, the source driver devices 2 and 300 can also be used for various applications. . [0046] While the present invention has been described in its preferred embodiments, it is not intended to limit the invention, and may be modified and modified, without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. ::ODMA\PCDOCS\TPEDMS\41528\l 19 201029325 [Simplified description of the drawings] [0047] According to the various features and functions of the present invention, the details can be described from the above description. Preferably, the drawings include: [0048] Figure 1 is a block diagram of a display device in accordance with an embodiment. Fig. 2 is a timing chart showing an embodiment of the waveform of the signal of the display device of Fig. 1 . [Description of main component symbols] 102 to output buffer circuit 110 to first amplifier circuit 200 to source driver device 204 to switching circuit 212 to first input stage 220 to second amplifier circuit 224 to second output stage 302 to output buffer circuit 320~second amplifier circuit IN(+), IN1(+), IN2(+)~ non-inverting input node P11, P13, P21~high power supply node P14, P23~intermediate power supply node SCTRL~control signal SI1- An input signal SOI to a first output signal SW1 to a first switch VCA1 to a first intermediate power source 100 to a source driver device 104 to a switching circuit 120 to a second amplifier circuit 202 to an output buffer circuit 210 to a first amplifier circuit 214 The first output stage 222 to the second input stage 〜 300 to the source driver device 310 to the first amplifier circuit IN(-), IN1 (1), IN2 (-) to the inverting input node FIRST_IN to the first source line input P12, P22, P24~lower power supply node RU, R12, R2, R22~resist SECOND_IN~second source line input SI2~second input signal S02~second output signal SW2~second switch::ODMA\PCDOCS\TPEDMS\ 41528M 20 2 01029325 VC A2 ~ second intermediate power supply VDD A ~ higher power supply VS S A ~ lower power supply
::ODMA\PCDOCS\TPEDMS\41528\1 21::ODMA\PCDOCS\TPEDMS\41528\1 21