CN101656534A - Output-stage circuit and operational amplifier - Google Patents
Output-stage circuit and operational amplifier Download PDFInfo
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- CN101656534A CN101656534A CN200810213017A CN200810213017A CN101656534A CN 101656534 A CN101656534 A CN 101656534A CN 200810213017 A CN200810213017 A CN 200810213017A CN 200810213017 A CN200810213017 A CN 200810213017A CN 101656534 A CN101656534 A CN 101656534A
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Abstract
The invention provides an output-stage circuit, which is implemented by means of an MOS transistor of the conventional twin-well process, so that not only the aim of supporting a Half AVDD framework is achieved, but also effects of power saving and energy saving are achieved and the cost of a triple well process is saved.
Description
Technical field
The present invention relevant for a kind of operational amplifier of support Half AVDD (being 1/2AVDD) framework, is to implement by the MOS transistor of traditional twin-well technology relevant for operational amplifier especially.
Background technology
Liquid crystal (liquid crystal) properties of materials is if imposed a direct current voltage constantly, liquid crystal material can be undermined, and for preventing that above-mentioned situation from taking place, industry generally can periodically reverse (inversion) add all data-signals (data line in liquid crystal layer, or title passage) polarity, this action is called AC driving (AC driving).(liquid crystal display, LCD) drive IC, system are only supplied AVDD (13.5V or 16V) and two kinds of operating voltages of VSS (hereinafter to be referred as the AVDD framework) usually for the conventional liquid crystal in positive pressure system work.Under the AVDD framework, for example channel voltage is when AVDD is pulled down to VSS, and electric charge has just slatterned, so the power consumption of traditional panel accounts for the ratio of total power consumption approximately up to seventy percent, even, when the LCD panel size is increasing, also cause the overheated problem of panel.
Be head it off, at present industry develops a kind of up-to-date solution and be: outside above-mentioned two kinds of operating voltages, system provides an operating voltage HalfAVDD (hereinafter to be referred as the HalfAVDD framework) to give drive IC in addition.Its notion is that the electric charge of positive polarity passage discharge (discharge) to Half AVDD voltage reclaimed, see through HalfAVDD voltage again with other negative polarity passage chargings (charge), therefore, the power supply of HalfAVDD is to be used for reaching less electricity consumption basically, can prevent that more the LCD panel is overheated.Be illustrated in figure 1 as and be located among one source pole drive circuit (source driver) two adjacency channel Y (n), the Y (n+1) of (figure does not show), support the known operations amplifier of HalfAVDD framework and the configuration diagram of four switches.Each passage respectively is provided with an operational amplifier 110,120 of supporting the HalfAVDD framework, is to be operated in respectively between AVDD and the Half AVDD, and between Half AVDD and the VSS.The voltage range of the positive analog picture signal A+ that operational amplifier 110 produces is between AVDD and the HalfAVDD, and the voltage range of the negative analog picture signal A-that operational amplifier 120 produces is between Half AVDD and the VSS.Every a Preset Time, need by switching four switch S 1～S4, alternately export a positive analog picture signal A+ and a negative analog picture signal A-to panel from channel output end Y (n), Y (n+1).
Yet according to known technology, the prerequisite that operational amplifier 110,120 can be supported the HalfAVDD framework is: MOS transistor must possess triple wells (triple well) technology.With NMOS is example, and technology that must many one decks deep layer n trap (deep n-well) is isolated p trap (p-well) and p mold base (p-substrate).But triple well technologies are a kind of expensive technology, and the Taiwan industry is not popularized at present as yet, and the cost of triple well technologies certainly will be higher than traditional twin-well (twin well) technology.For addressing the above problem, therefore the present invention is proposed.
Summary of the invention
Because the problems referred to above, one of purpose of the present invention provides a kind of output-stage circuit, is to implement by the MOS transistor of traditional twin-well technology, to reach the purpose of supporting the HalfAVDD framework.
For reaching above-mentioned purpose, output-stage circuit of the present invention comprises: one the one PMOS transistor, one the 2nd PMOS transistor, one first nmos pass transistor and one second nmos pass transistor.The transistorized matrix of the one PMOS is coupled to one first operating voltage, and source electrode is coupled to one first intermediate voltage, and grid is coupled to one first control signal.Transistorized source electrode of the 2nd PMOS and matrix are coupled to described first operating voltage, and grid is coupled to one second control signal.The source electrode of first nmos pass transistor is coupled to one second intermediate voltage, matrix is coupled to one second operating voltage, grid is coupled to one the 3rd control signal, wherein, described second operating voltage is to be lower than described first operating voltage, and described first intermediate voltage and described second intermediate voltage all are higher than described second operating voltage and are lower than described first operating voltage.The source electrode of second nmos pass transistor and matrix are coupled to described second operating voltage, and its grid is coupled to one the 4th control signal.Wherein, described these transistors are to make with dual well technology, and described these transistor drain couple mutually to form an output, and, a time point in office, described these control signals one of them is enabled at least, with conducting described these transistorized at least one of them.
Another object of the present invention provides a kind of operational amplifier, has a positive input terminal, a negative input end and an output, and described negative input end is coupled to described output, and described operational amplifier comprises: an input stage circuit and an output-stage circuit.Described input stage circuit is according to the voltage difference of described positive input terminal and described negative input end, to enable one of them person at least of one first control signal, one second control signal, one the 3rd control signal and one the 4th control signal.Described output-stage circuit comprises: one the one PMOS transistor, its matrix are coupled to one first operating voltage, and its source electrode is coupled to one first intermediate voltage, and its grid is coupled to described first control signal; One the 2nd PMOS transistor, its source electrode and matrix are coupled to described first operating voltage, and its grid is coupled to described second control signal; One first nmos pass transistor, its source electrode are coupled to one second intermediate voltage, and its matrix is coupled to one second operating voltage, and its grid is coupled to described the 3rd control signal; And one second nmos pass transistor, its source electrode and matrix are coupled to described second operating voltage, its grid is coupled to described the 4th control signal, wherein, described these transistors are to make with dual well technology, and described these transistor drain couple mutually in described output.
Now the detailed description and the claim that cooperate following diagram, embodiment, will on address other objects and advantages of the present invention and be specified in after.
Description of drawings
Fig. 1 shows in two adjacency channels, supports the known operations amplifier of Half AVDD framework and the configuration diagram of four switches.
Fig. 2 is the configuration diagram of an embodiment of operational amplifier of the present invention.
Fig. 3 is the electric current and voltage output characteristic curve of nmos pass transistor 223,224 in the comparison diagram 2.
Fig. 4 is shown in an example of the output end voltage waveform of following two the adjacency channel Y of two line point reversing mode (n), Y (n+1).
Fig. 5 A is the discharge path schematic diagram of the output-stage circuit of operational amplifier of the present invention in transient period.
Fig. 5 B is that the output-stage circuit of operational amplifier of the present invention is in the discharge path schematic diagram of the phase of setting up.
Fig. 5 C is the charge path schematic diagram of the output-stage circuit of operational amplifier of the present invention in transient period.
Fig. 5 D is that the output-stage circuit of operational amplifier of the present invention is in the discharge path schematic diagram of the phase of setting up.
Fig. 6 A connects a load circuit by the output at operational amplifier, the transient period that to simulate an output end voltage be the drop edge.
Fig. 6 B connects a load circuit by the output at operational amplifier, and simulating an output end voltage is setting up the phase of drop edge.
Fig. 6 C is the output end voltage V of operational amplifier of the present invention
OutSimulation measurement figure.
Drawing reference numeral
110,120,200 operational amplifiers
210 input stage circuits
220 output-stage circuits
221,222PMOS transistor
223,224NMOS transistor
S1, S2, S3, S4 switch
Embodiment
Below, be that the source electrode drive circuit with LCD illustrates that as example operational amplifier only of the present invention and output-stage circuit also can be applicable on other integrated circuits that need support Half AVDD framework.
Fig. 2 is the configuration diagram of an embodiment of operational amplifier of the present invention.With reference to figure 2, operational amplifier 200 of the present invention has a positive input terminal, a negative input end and an output, and described operational amplifier 200 comprises an input stage circuit 210 and an output-stage circuit 220.Input stage circuit 210 in operating voltage AVDD work down, receives positive input terminal voltage V respectively
+With negative input end voltage V
-, then, again according to the voltage of described positive input terminal and the voltage of described negative input end, with enable four control signal CS1, CS2, CS3, CS4 at least one of them.
Output-stage circuit 220 comprises two PMOS transistors 221,222 and bi-NMOS transistor 223,224, and the drain electrode of four transistors 221,222,223,224 couples mutually in the output of operational amplifier 200, and described output out is coupled to described negative input end again.The matrix of PMOS transistor 221 (bulk) is coupled to operating voltage AVDD, and source electrode is coupled to intermediate voltage V
Top, grid receives control signal CS1 (low state is effective, low active).The source electrode of PMOS transistor 222 and matrix are coupled to operating voltage AVDD simultaneously, and grid receives control signal CS2.The source electrode of nmos pass transistor 223 is coupled to intermediate voltage V
Bot, matrix is coupled to operating voltage VSS, and grid receives control signal CS3.The source electrode of nmos pass transistor 224 and matrix are coupled to operating voltage VSS simultaneously, and grid receives control signal CS4.In the present embodiment, intermediate voltage V
Top, V
BotAll be coupled to operating voltage HalfAVDD.Note that intermediate voltage V of the present invention
Top, V
BotSize not as limit, can adjust with demand according to design.
In addition, the difference of four transistors 221,222,223,224 is: the source voltage V of PMOS transistor 221 and nmos pass transistor 223
SWith matrix (bulk) voltage V
BDifferent (V
SB＞0), so can produce bulk effect (body effect); The source voltage V of PMOS transistor 222 and nmos pass transistor 224
SWith matrix voltage V
BIdentical (V
SB=0), so can not produce bulk effect.When transistorized threshold voltage increases because of bulk effect, can cause the conducting electric current I
DSReduce and make drives power die down.
Fig. 3 is the electric current and voltage output characteristic curve of nmos pass transistor 223,224 in the comparison diagram 2.Can observe from Fig. 3, there is the nmos pass transistor 223 of bulk effect still to can be used for sinking electric current (sinkcurrent), just the magnitude of current does not slightly have half of nmos pass transistor 224 of bulk effect approximately, these characteristics are quite important to circuit framework of the present invention, there is the nmos pass transistor 223 of bulk effect to still have the good current capacity that sinks, can be used for the output stage of amplifier.
When output end voltage need change, (drivingperiod) changed in two stages during the driving of the present invention with whole operational amplifier, was respectively transient period (transient period) and set up the phase (settling period).The transient current (transient current) of transistor 221,223 (and closing (turn off) transistor 222,224) when saving operational amplifier 200 transitions of bulk effect arranged with regard to conducting (turn on) when transient period, and when setting up the phase, do not have the transistor 222,224 (and closing transistor 221,223) of bulk effect with regard to conducting; Transient period with set up the time of phase overlapping (Overlap) can be arranged, just first conducting transistor 222,224, close transistor 221,223 again, or even not closing transistor 221,223 also can, utilize bigger sinking the settling time (settling time) that electric current (or draining out electric current, source current) amount shortens operational amplifier 200.It is noted that, transient period and set up between the phase and to want at least continuously, can not poor if having time (time gap) between the two, otherwise circuit can produce (floating) phenomenon of floating, and the needs or the circuit load size of circuit are depended in transient period and the distribution of setting up the two time of phase.
The present invention is different from two adjacency channel Y (n) in the known technology, the operational amplifier 110 of Y (n+1), the 120th, be operated between AVDD and the HalfAVDD respectively and between HalfAVDD and the VSS (as Fig. 1), for being located at two adjacency channel Y (n), two operational amplifiers of the present invention of Y (n+1) (figure does not show), circuit structure and operating voltage is identical (receives VSS equally no matter, AVDD, HalfAVDD), because operational amplifier 200 of the present invention is based on Half AVDD framework, utilization discharges and recharges the default polarity (will describe in detail in Fig. 5 A～5D) that reaches described channel output end voltage, therefore can give up and utilize 4 switch S 1～S4 to come the alternately mechanism of switch data polarity among Fig. 1.
Generally speaking, liquid crystal polarity inversion pattern roughly is divided into following several: picture frame counter-rotating (frameinversion), row counter-rotatings (row inversion), hurdle counter-rotating (column inversion), some counter-rotating (dotinversion), 2 line points counter-rotatings (two line dot inversion) or the like.Application of the present invention is not limited to any specific reversing mode, below, with two line point reversing mode circuit running of the present invention is described.
Fig. 4 is shown in an example of the output end voltage waveform of following two the adjacency channel Y of two line point reversing mode (n), Y (n+1).Fig. 5 A is the discharge path schematic diagram of the output-stage circuit of operational amplifier of the present invention in transient period.Fig. 5 B is that the output-stage circuit of operational amplifier of the present invention is in the discharge path schematic diagram of the phase of setting up.Fig. 5 C is the charge path schematic diagram of the output-stage circuit of operational amplifier of the present invention in transient period.Fig. 5 D is that the output-stage circuit of operational amplifier of the present invention is in the discharge path schematic diagram of the phase of setting up.
Please also refer to Fig. 2 and Fig. 5 A, is example with a decline edge (falling edge) I of Fig. 4 passage Y (n+1) output end voltage, as output end voltage V
Out(equal negative input end voltage V
-) and positive input terminal voltage V
+When being positive polarity, change in two stages, comprise transient period and set up the phase.At first, circuit enters transient period, input stage circuit 210 enables control signal CS3 earlier, with conducting nmos pass transistor 223, drag down by the output end voltage of Half AVDD operating voltage operational amplifier, discharging current promptly imports Half AVDD along the direction of arrow of Fig. 5 A, and reclaims Charge Storage on the electric capacity of Half AVDD and then reach purpose of power saving.After a period of time, transient period finishes, enter the phase of foundation: input stage circuit 210 enables control signal CS4 earlier, with conducting nmos pass transistor 224, forbidden energy control signal CS3 is to close nmos pass transistor 223 (or continuing to enable control signal CS3 with conducting nmos pass transistor 223) again, electric current promptly along the direction of arrow discharge of Fig. 5 B, utilizes the output end voltage V of operating voltage VSS with operational amplifier
OutBe pulled down to target voltage apace, and because this electric current of setting up the phase is to import VSS, so electric charge can't reclaim.
On the other hand, when output end voltage is a decline edge, but output end voltage V
OutAnd positive input terminal voltage V
+When not meeting above-mentioned positive polarity and requiring (for example drop edge III), can only utilize VSS to drag down this moment, and electric charge can't reclaim, so have only stage variation during the driving of whole operational amplifier, promptly sets up the phase.Input stage circuit 210 directly enables control signal CS4, with conducting nmos pass transistor 224 (or enabling control signal CS3 simultaneously with conducting nmos pass transistor 223), with the output end voltage V of operational amplifier
OutBe pulled down to target voltage apace.
Please also refer to the 2nd figure and 5C figure, is example with a rising edge (risingedge) II of the 4th figure passage Y (n), as output end voltage V
OutAnd positive input terminal voltage V
+When being negative polarity, change in two stages, comprise transient period and set up the phase.Circuit at first enters transient period, input stage circuit 210 enables control signal CS1 earlier, with conducting PMOS transistor 221, utilize Half AVDD operating voltage that the output end voltage of operational amplifier is drawn high, charge by Half AVDD operating voltage supplying charging current and along the direction of arrow of 5C figure.Please note, the electric charge of passage Y this moment (n) charging is the recovery electric charge that common-use tunnel Y (n+1) leads HalfAVDD, in other words, when passage Y (n+1) is drop-down by electric charge that load end reclaimed, can supply with to reach the power saving purpose so can save the power supply of HalfAVDD for drawing the required power consumption of load end on the passage Y (n).Similarly, after a period of time, transient period finishes, circuit enters the phase of foundation: input stage circuit 210 enables control signal CS2 earlier, with conducting PMOS transistor 222, forbidden energy control signal CS1 utilizes the output end voltage V of AVDD operating voltage with operational amplifier to close PMOS transistor 221 (or continuing to enable control signal CS1 with conducting PMOS transistor 221) again
OutDraw high target voltage apace, electric current is promptly along the direction of arrow quick charge of 5D figure.
On the other hand, when output end voltage be a rising edge but output end voltage V
OutAnd positive input terminal voltage V
+When not meeting above-mentioned negative polarity and requiring (for example rising edge IV), can only utilize AVDD to draw high this moment, the recovery electric charge of can't common-use tunnel Y (n+1) leading HalfAVDD, so have only a stage to change during the driving of whole operational amplifier, promptly set up the phase, input stage circuit 210 directly enables control signal CS2, with conducting PMOS transistor 222 (or enabling control signal CS1 simultaneously with conducting PMOS transistor 221), with the output end voltage V of operational amplifier
OutDraw high target voltage apace.
6A figure connects a load circuit by the output at operational amplifier, the transient period that to simulate an output end voltage be the drop edge.6B figure connects a load circuit by the output at operational amplifier, and simulating an output end voltage is setting up the phase of drop edge.6C figure is the output end voltage V of operational amplifier of the present invention
OutSimulation measurement figure.
With reference to 6A figure and 6B figure, this simulated experiment is to utilize N rank RC-π models (Model) to be used as load circuit, and selects following data to measure: resistance R=10k ohm, capacitor C=125p farad, AVDD=13.5V, V
Bot=6.75V.Simultaneously, when the hypothetical simulation experiment began to carry out, the starting voltage of capacitor C was 13.5V (equaling 13.5V as output end voltage), positive input terminal voltage V
+Equal 6.75V.Circuit enters transient period, so input stage circuit 210 enables control signal CS3 (being transient period) earlier, with conducting nmos pass transistor 223, discharging current promptly imports HalfAVDD along the direction of arrow of 6A figure, and the output end voltage of operational amplifier is pulled down to about 7V by 13.5V.After a period of time, transient period finishes, and enters the phase of foundation, and input stage circuit 210 enables control signal CS4 (being plateau), with conducting nmos pass transistor 224, and forbidden energy control signal CS3 again.After transient period enters the phase of foundation, can see output end voltage V from Fig. 6 C
OutReach target current potential 6.75V apace.
Can be observed by above-mentioned explanation, in the process of operational amplifier running of the present invention, be to come control output end voltage V by switch-over control signal CS1, CS2, CS3, CS4
OutThe position is accurate, and without any the action of Switching power (VSS, AVDD, HalfAVDD), because all MOS transistor were fixed with being connected all of power supply, the power supply of IC can not done any switching yet, therefore, circuit has fully been avoided the risk of power supply short circuit fully.As mentioned above, needn't use complicated and expensive triple well technologies, the present invention utilizes traditional twin-well artwork body pipe and special circuit framework to implement the output-stage circuit of operational amplifier, reaches the purpose and the power and energy saving effect of supporting the HalfAVDD framework equally.
The specific embodiment that is proposed in the detailed description of preferred embodiment is only in order to convenient explanation technology contents of the present invention, but not with narrow sense of the present invention be limited to the foregoing description, in the situation that does not exceed spirit of the present invention and following claim, the many variations of being done is implemented, and all belongs to scope of the present invention.
Claims (22)
1. an output-stage circuit is characterized in that, described output-stage circuit comprises:
One the one PMOS transistor, its matrix are coupled to one first operating voltage, and its source electrode is coupled to one first intermediate voltage, and its grid is coupled to one first control signal;
One the 2nd PMOS transistor, its source electrode and matrix are coupled to described first operating voltage, and its grid is coupled to one second control signal;
One first nmos pass transistor, its source electrode is coupled to one second intermediate voltage, its matrix is coupled to one second operating voltage, its grid is coupled to one the 3rd control signal, wherein, described second operating voltage is to be lower than described first operating voltage, and described first intermediate voltage and described second intermediate voltage all are higher than described second operating voltage and are lower than described first operating voltage; And
One second nmos pass transistor, its source electrode and matrix are coupled to described second operating voltage, and its grid is coupled to one the 4th control signal;
Wherein, described these transistors are to make with dual well technology, and described these transistor drain couple mutually to form an output, and, a time point in office, described these control signals one of them is enabled at least, with conducting described these transistorized at least one of them.
2. output-stage circuit as claimed in claim 1 is characterized in that, described first intermediate voltage and described second intermediate voltage are between described first operating voltage and described second operating voltage.
3. output-stage circuit as claimed in claim 2 is characterized in that, described first intermediate voltage and described second intermediate voltage equal described first operating voltage and described second operating voltage and 1/2nd.
4. output-stage circuit as claimed in claim 1 is characterized in that, described output-stage circuit is to be applied to an operational amplifier.
5. output-stage circuit as claimed in claim 4 is characterized in that, described these control signals are controlled by an input stage circuit of described operational amplifier.
6. output-stage circuit as claimed in claim 1, it is characterized in that, when the voltage of described output needs to be drawn high, described first control signal and described second control signal one of them is enabled at least, with the described PMOS transistor of conducting and described the 2nd PMOS transistorized at least one of them.
7. output-stage circuit as claimed in claim 1, it is characterized in that, when the voltage of described output needs to be dragged down, described the 3rd control signal and described the 4th control signal one of them is enabled at least, with described first nmos pass transistor of conducting and second nmos pass transistor at least one of them.
8. an operational amplifier is characterized in that, described operational amplifier has a positive input terminal, a negative input end and an output, and described negative input end is coupled to described output, and described operational amplifier comprises:
One input stage circuit is according to the voltage of described positive input terminal and the voltage of described negative input end, to enable one of them person at least of one first control signal, one second control signal, one the 3rd control signal and one the 4th control signal; And
One output-stage circuit comprises:
One the one PMOS transistor, its matrix are coupled to one first operating voltage, and its source electrode is coupled to one first intermediate voltage, and its grid is coupled to described first control signal;
One the 2nd PMOS transistor, its source electrode and matrix are coupled to described first operating voltage, and its grid is coupled to described second control signal;
One first nmos pass transistor, its source electrode are coupled to one second intermediate voltage, and its matrix is coupled to one second operating voltage, and its grid is coupled to described the 3rd control signal; And
One second nmos pass transistor, its source electrode and matrix are coupled to described second operating voltage, and its grid is coupled to described the 4th control signal, wherein, described these transistors are to make with dual well technology, and described these transistor drain couple mutually in described output.
9. operational amplifier as claimed in claim 8 is characterized in that, described operational amplifier is to be applied to one of LCD source electrode drive circuit.
10. operational amplifier as claimed in claim 8 is characterized in that, described first intermediate voltage and described second intermediate voltage are between described first operating voltage and described second operating voltage.
11. operational amplifier as claimed in claim 10 is characterized in that, described first intermediate voltage and described second intermediate voltage equal described first operating voltage and described second operating voltage and 1/2nd.
12. operational amplifier as claimed in claim 8 is characterized in that, described input stage circuit is to work under described first operating voltage and described second operating voltage.
13. operational amplifier as claimed in claim 8, it is characterized in that, when the voltage of described output will be dragged down, if the voltage of described positive input terminal and the voltage of described negative input end are positive polarity, then being divided into one first transient period and one first during the driving of described operational amplifier in regular turn sets up the phase, otherwise, include only described first during the driving of described operational amplifier and set up the phase.
14. operational amplifier as claimed in claim 13 is characterized in that, when described operational amplifier was in described first transient period, described input stage circuit enabled described the 3rd control signal, with described first nmos pass transistor of conducting.
15. operational amplifier as claimed in claim 13 is characterized in that, when described operational amplifier is in described first when setting up the phase, described input stage circuit enables described the 4th control signal, with described second nmos pass transistor of conducting.
16. operational amplifier as claimed in claim 15 is characterized in that, when described operational amplifier is in described first when setting up the phase, described input stage circuit more enables described the 3rd control signal, with described first nmos pass transistor of conducting.
17. operational amplifier as claimed in claim 13 is characterized in that, the time of described first transient period and described first time of setting up the phase are that overlap or continuous.
18. operational amplifier as claimed in claim 8, it is characterized in that, when the voltage of described output will be drawn high, if the voltage of described positive input terminal and the voltage of described negative input end are negative polarity, then being divided into one second transient period and one second during the driving of described operational amplifier in regular turn sets up the phase, otherwise, include only described second during the driving of described operational amplifier and set up the phase.
19. operational amplifier as claimed in claim 18 is characterized in that, when described operational amplifier was in described second transient period, described input stage circuit enabled described first control signal, with the described PMOS transistor of conducting.
20. operational amplifier as claimed in claim 18 is characterized in that, when described operational amplifier is in described second when setting up the phase, described input stage circuit enables described second control signal, with described the 2nd PMOS transistor of conducting.
21. operational amplifier as claimed in claim 20 is characterized in that, when described operational amplifier is in described second when setting up the phase, described input stage circuit more enables described first control signal, with the described PMOS transistor of conducting.
22. operational amplifier as claimed in claim 18 is characterized in that, the time of described second transient period and described second time of setting up the phase are that overlap or continuous.
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| CN102270969A (en) * | 2010-06-04 | 2011-12-07 | 原景科技股份有限公司 | Light-emitting diode circuit and error amplifier thereof |
| CN105099432A (en) * | 2014-05-19 | 2015-11-25 | 奇景光电股份有限公司 | Output buffer |
| TWI581233B (en) * | 2016-03-25 | 2017-05-01 | Chipone Technology (Beijing)Co Ltd | Low power source drive circuit |
| CN109147684A (en) * | 2017-06-16 | 2019-01-04 | 拉碧斯半导体株式会社 | output circuit and display driver |
| CN112201212A (en) * | 2020-10-13 | 2021-01-08 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
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| US5162753A (en) * | 1991-11-27 | 1992-11-10 | At&T Bell Laboratories | Amplifier arrangement for use as a line driver |
| US5959475A (en) * | 1998-01-13 | 1999-09-28 | Xerox Corporation | Complementary push-pull CMOS source follower analog video buffer |
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| CN102270969A (en) * | 2010-06-04 | 2011-12-07 | 原景科技股份有限公司 | Light-emitting diode circuit and error amplifier thereof |
| CN105099432A (en) * | 2014-05-19 | 2015-11-25 | 奇景光电股份有限公司 | Output buffer |
| CN105099432B (en) * | 2014-05-19 | 2019-04-30 | 奇景光电股份有限公司 | Output buffer |
| TWI581233B (en) * | 2016-03-25 | 2017-05-01 | Chipone Technology (Beijing)Co Ltd | Low power source drive circuit |
| CN109147684A (en) * | 2017-06-16 | 2019-01-04 | 拉碧斯半导体株式会社 | output circuit and display driver |
| JP2019003088A (en) * | 2017-06-16 | 2019-01-10 | ラピスセミコンダクタ株式会社 | Output circuit and display driver |
| TWI746246B (en) * | 2019-11-20 | 2021-11-11 | 聯詠科技股份有限公司 | Electronic device and display driving chip |
| US11176861B2 (en) | 2019-11-20 | 2021-11-16 | Novatek Microelectronics Corp. | Electronic device and display driver chip |
| CN112201212A (en) * | 2020-10-13 | 2021-01-08 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
| CN112201212B (en) * | 2020-10-13 | 2022-04-01 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
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|---|---|
| CN101656534B (en) | 2011-05-18 |
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