TWI569375B - Memory device and method of manufacturing the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

With the rapid development of technology, in order to reduce the cost, simplify the process steps and save the wafer area, it has become a trend to integrate the elements of the memory cell array and the peripheral circuit area on the same wafer. However, as the aspect ratio of the memory element becomes higher and higher, since the pattern density between the memory cell array region and the peripheral circuit region is different, it is easy to cause a micro-loading effect. The micro-loading effect generally refers to a variation in the size of a semiconductor element due to a difference in pattern density when an etching process is performed. For example, Sub-trench defects are prone to occur in peripheral circuit areas with low pattern density, and sub-channel defects will cause difficulties in subsequent process margins. Therefore, how to solve the micro-load effect between the memory cell array region and the peripheral circuit region and improve the problem of sub-channel defects in the peripheral circuit region will become a very important issue.

The invention provides a memory element and a manufacturing method thereof, which can solve the micro-load effect between the memory cell array region and the peripheral circuit region, and improve the problem of sub-ditch defects in the peripheral circuit region.

The present invention provides a memory element including a substrate, a first stacked structure, and a plurality of second stacked structures. The substrate has a first zone and a second zone. The first stack structure is located on the substrate of the first zone. The first stack structure includes a plurality of first conductor layers and a plurality of first dielectric layers. The first conductor layer and the first dielectric layer are stacked on each other. A plurality of second stacked structures are located on the substrate of the second zone. Each of the second stacked structures includes a plurality of second conductor layers and a plurality of second dielectric layers. The second conductor layer and the second dielectric layer are stacked on each other. The sidewalls of the first stack structure and the sidewalls of the second stack structure are respectively concave and convex surfaces.

In an embodiment of the invention, the contours of the sidewalls of the first stack structure and the second stack structure comprise at least two perpendicular tangents.

In an embodiment of the invention, a bottom dielectric structure is further included between the substrate and the first stacked structure and between the substrate and the second stacked structure. The bottom dielectric structure has a main body portion, a first protruding portion, and a plurality of second protruding portions. The first protrusion extends from the body portion and is located between the body portion and the first stack structure. The second protrusions extend from the body portion and are respectively located between the body portion and the second stack structure. A distance between a top surface of the body portion adjacent to the first stack structure and a top surface remote from the body portion of the first stack structure is less than 100 Å.

In an embodiment of the invention, adjacent to the body portion of the first stack structure The distance between the top surface and the top surface remote from the body portion of the first stacked structure is 10 Å to 100 Å.

The present invention provides a memory element including a substrate, a first stacked structure, a plurality of second stacked structures, and a bottom dielectric structure. The substrate has a first zone and a second zone. The first stack structure is located on the substrate of the first zone. The first stack structure includes a plurality of first conductor layers and a plurality of first dielectric layers. The first conductor layer and the first dielectric layer are stacked on each other. A plurality of second stacked structures are located on the substrate of the second zone. Each of the second stacked structures includes a plurality of second conductor layers and a plurality of second dielectric layers. The second conductor layer and the second dielectric layer are stacked on each other. A bottom dielectric structure is between the substrate and the first stack structure and between the substrate and the second stack structure. The bottom dielectric structure has a main body portion, a first protruding portion, and a plurality of second protruding portions. The first protrusion extends from the body portion and is located between the body portion and the first stack structure. The second protrusions extend from the body portion and are respectively located between the body portion and the second stack structure. a distance between a top surface of the first stacked structure and a top surface adjacent to the main body portion of the first stacked structure is a distance between a top surface of the second stacked structure and a top surface of the main body portion adjacent to the second stacked structure 1 to 1.1 times.

In an embodiment of the invention, a charge storage layer and a third conductor layer are further included. A charge storage layer covers the surfaces of the first stacked structure and the second stacked structure. The third conductor layer covers the surface of the charge storage layer.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A substrate is provided. The substrate has a first zone and a second zone. A bottom dielectric layer is formed on the substrate. The bottom dielectric layer traverses the first zone and the second zone. A stacked layer is formed on the bottom dielectric layer. Stacking layer A plurality of first conductor layers and a plurality of first dielectric layers are included. The first conductor layer and the first dielectric layer are stacked on each other. An etching process is performed on the stacked layers, and a portion of the stacked layers are removed to form a first stacked structure on the substrate of the first region, and a plurality of second stacked structures are formed on the substrate of the second region. The etching process includes a plurality of first etching steps and a plurality of second etching steps. The first etching step and the second etching step alternate.

In an embodiment of the invention, the first etching step includes removing a portion of the first conductor layer. The second etching step includes removing a portion of the first dielectric layer. The first etching step is different from the reaction gas used in the second etching step.

In an embodiment of the invention, the method further includes forming a charge storage layer on the first stacked structure and the second stacked structure. A second conductor layer is formed on the charge storage layer.

In an embodiment of the invention, during the etching process, a portion of the bottom dielectric layer is removed to form a bottom dielectric structure. The bottom dielectric structure has a body portion, a first protrusion, and a plurality of second protrusions. The first protrusion extends from the body portion and is located between the body portion and the first stack structure. The second protrusions extend from the body portion and are respectively located between the body portion and the second stack structure.

Based on the above, the manufacturing method of the memory element of the present invention may alternately perform the first etching step and the second etching step to alternately remove the conductor layer and the dielectric layer. Therefore, the stacked layers of the present invention having a plurality of conductor layers and a plurality of dielectric layers can be sequentially removed, thereby reducing the micro-loading effect between the memory cell array regions and the peripheral circuit regions. In this way, the present invention can improve the problem of sub-drain defects in the peripheral circuit area to increase the margin of subsequent processes.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

100‧‧‧Base

102‧‧‧ bottom dielectric layer

102a‧‧‧ Main body

102b‧‧‧First protrusion

102c‧‧‧second protrusion

103‧‧‧Bottom dielectric structure

104‧‧‧Stacking layer

104a‧‧‧First stacking structure

104b‧‧‧Second stacking structure

106, 106a, 106b, 114‧‧‧ conductor layer

108, 108a, 108b‧‧‧ dielectric layer

110a, 110b, 110c, 110d‧‧‧ patterned mask layer

112‧‧‧Charge storage layer

d, H1, H2‧‧‧ distance

Part P‧‧‧

R1‧‧‧ first district

R2‧‧‧Second District

T1, T2‧‧‧ thickness

W1, W2‧‧‧ width

BCD1, BCD2, BCD3, BCD4‧‧‧ bottom critical dimensions

MCD1, MCD2, MCD3, MCD4‧‧‧ intermediate key size

TCD1, TCD2, TCD3, TCD4‧‧‧ top key size

1A to 1C are schematic cross-sectional views showing a manufacturing process of a memory element according to an embodiment of the present invention.

2A to 2B are enlarged schematic views of a portion of the stacked structure P of Fig. 1B, respectively.

1A to 1C are schematic cross-sectional views showing a manufacturing process of a memory element according to an embodiment of the present invention.

Referring to FIG. 1A, first, a substrate 100 is provided. The substrate 100 has a first region R1 and a second region R2. In the present embodiment, the first region R1 may be, for example, a peripheral circuit region, and the second region R2 may be, for example, a memory cell array region. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Next, a bottom dielectric layer 102 is formed on the substrate 100. The bottom dielectric layer 102 traverses the first region R1 and the second region R2. The material of the bottom dielectric layer 102 may include tantalum oxide, tantalum nitride or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. bottom The thickness of the dielectric layer 102 can be, for example, 200 Å to 5000 Å. In an embodiment, the bottom dielectric layer 102 can be, for example, a Bottom Oxide Layer (BOX).

Then, a stacked layer 104 is formed on the bottom dielectric layer 102. The stacked layer 104 includes a plurality of conductor layers 106 and a plurality of dielectric layers 108. The conductor layer 106 and the dielectric layer 108 are stacked one on another. In an embodiment, the material of the conductor layer 106 may include doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition, and the thickness of the conductor layer 106 may be, for example, 200 Å to 1000 Å. . The material of the dielectric layer 108 may include tantalum oxide, tantalum nitride or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition, and the thickness of the dielectric layer 108 may be, for example, 200 Å to 1000 Å. Although FIG. 1A only shows the 5-layer conductor layer 106 and the 5-layer dielectric layer 108, the invention is not limited thereto. In other embodiments, the number of the conductor layers 106 may be, for example, 8 layers or 16 layers. , 32 or more layers. Similarly, the dielectric layer 108 is disposed between two adjacent conductor layers 106. Therefore, the dielectric layer 108 can also be, for example, 8 layers, 16 layers, 32 layers, or more.

Next, patterned mask layers 110a, 110b are formed on the stacked layer 104. The patterned mask layer 110a, 110b can be, for example, an Advanced Patterning Film (APF), a nitride layer, or a combination thereof. The material of the advanced patterned film (APF) includes a carbonaceous material, and the carbonaceous material may be, for example, amorphous carbon. In this embodiment, a nitride layer may be formed on the stacked layer 104 to form an advanced patterned film (APF).

Referring to FIG. 1A and FIG. 1B, the patterned mask layer 110a, 110b is used as a mask, and the stacked layer 104 is etched to remove a portion of the bottom dielectric layer 102 and The layers 104 are partially stacked to form a first stacked structure 104a, a plurality of second stacked structures 104b, and a bottom dielectric structure 103. Since the partially patterned mask layer 110a, 110b is consumed during the etching process described above, the patterned mask layer 110c is formed on the first stacked structure 104a and simultaneously formed on the second stacked structure 104b. A patterned mask layer 110d (shown in Figure 1B). In the present embodiment, the thickness of the patterned mask layers 110c, 110d may be, for example, 200 Å to 2000 Å.

The first stack structure 104a is located on the substrate 100 of the first region R1. The first stacked structure 104a includes a plurality of conductor layers 106a and a plurality of dielectric layers 108a. The conductor layer 106a and the dielectric layer 108a are stacked one on another. The second stack structure 104b is located on the substrate 100 of the second region R2. Each of the second stacked structures 104b includes a plurality of conductor layers 106b and a plurality of dielectric layers 108b. The conductor layer 106b and the dielectric layer 108b are stacked on each other. The bottom dielectric structure 103 is located between the substrate 100 and the first stacked structure 104a and between the substrate 100 and the second stacked structure 104b. In detail, the bottom dielectric structure 103 has a main body portion 102a, a first protruding portion 102b, and a plurality of second protruding portions 102c. The first protrusion 102b extends from the body portion 102a between the body portion 102a and the first stack structure 104a, and the second protrusion portion 102c extends from the body portion 102a between the body portion 102a and the second stack structure 104b, respectively. The structure of the memory element of this embodiment will be described in detail in the following paragraphs, and will not be described in detail herein.

It should be noted that the above etching process includes a plurality of first etching steps and a plurality of second etching steps. The first etching step is for removing a portion of the conductor layer 106; the second etching step is for removing a portion of the dielectric layer 108, and the first etching step and the second etching step are alternated. Specifically, the partial stack layer 104 is removed. When the first etching step, the second etching step, the first etching step, the second etching step, and the like are sequentially performed, the partial conductor layer 106, the partial dielectric layer 108, the partial conductor layer 106, and the portion are sequentially removed. Dielectric layer 108 and the like. Next, a portion of the bottom dielectric layer 102 is removed using a second etching step to expose the sidewalls of the first protrusion 102b and the second protrusion 102c. In one embodiment, the first etching step is different from the reaction gas used in the second etching step.

In the present embodiment, the etching process is performed by alternately performing the first etching step and the second etching step to alternately remove the portion of the conductor layer 106 and the portion of the dielectric layer 108. Since the first etching step is for removing the conductor layer 106 and the second etching step is for removing the dielectric layer 108, the present embodiment can completely remove the unpatterned mask layers 110a, 110b. A portion of the conductor layer 106 and a portion of the dielectric layer 108 are shielded. In other words, even if the pattern density between the first region R1 (which may be, for example, a memory cell array region) and the second region R2 (which may be, for example, a peripheral circuit region) is different, the above etching process is used to remove the stacked layer of high aspect ratio, The micro-loading effect between the memory cell array region and the peripheral circuit region can be reduced. In this way, the present invention can improve the problem of sub-drain defects in the peripheral circuit area to increase the margin of subsequent processes.

In this embodiment, the etching process can be, for example, a dry etch. The dry etching can be, for example, reactive ion etching (RIE). The first etching step may be, for example, using a flow rate of 200 sccm to 400 sccm of HBr and a flow rate of 7.5 sccm to 20 sccm of O ₂ at a pressure of 10 to 70 mTorr, a source power source (Source Power, Ws) of 400 W to 1200 W, and a bias power supply (Bias). Power, Wb) is performed from 100W to 800W. The second etching step may be, for example, CF ₄ with a flow rate of 100 sccm to 300 sccm, CHF ₃ with a flow rate of 100 sccm to 300 sccm, CH ₂ F ₂ with a flow rate of 10 sccm to 300 sccm, N ₂ with a flow rate of 100 sccm to 500 sccm, and O ₂ with a flow rate of 5 sccm to 20 sccm. The source power source (Source Power, Ws) is 400W to 1200W, the source power (Bias Power, Wb) is 100W to 800W, and the plasma frequency is 200Hz to 1000Hz at a pressure of 10mTorr to 50mTorr.

Next, referring to FIG. 1C, a charge storage layer 112 is formed on the first stacked structure 104a and the second stacked structure 104b. The charge storage layer 112 is conformally formed along the surface of the first stacked structure 104a and the second stacked structure 104b. In one embodiment, the charge storage layer 112 may be, for example, a composite layer composed of an oxide layer/nitride layer/Oxide (ONO), and the composite layer may be three or more layers. The present invention is not limited thereto, and the formation method thereof may be a chemical vapor deposition method, a thermal oxidation method, or the like.

Then, a conductor layer 114 is formed on the charge storage layer 112. In an embodiment, the conductor layer 114 located in the second region R2 (which may be, for example, a memory cell array region) may be, for example, a word line (WL Line); and the second stacked structure 104b may be, for example, a bit line. (Bit Line, BL). However, the invention is not limited thereto, and in other embodiments, the second stack structure 104b may be, for example, a word line, and the conductor layer 114 may be, for example, a bit line. The material of the conductor layer 114 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may utilize a chemical vapor deposition method. The thickness of the conductor layer 114 can be, for example, 200 Å to 3,000 Å.

2A to 2B are enlarged views of a portion of the stacked structure P of FIG. 1B, respectively. intention.

Referring to FIG. 1B, FIG. 2A and FIG. 2B, the present invention provides a memory element including a substrate 100, a first stacked structure 104a, a plurality of second stacked structures 104b, and a bottom dielectric structure 102. The substrate 100 has a first region R1 and a second region R2. In the present embodiment, the first region R1 may be, for example, a peripheral circuit region, and the second region R2 may be, for example, a memory cell array region. The first stack structure 104a is located on the substrate 100 of the first region R1. A plurality of second stacked structures 104b are located on the substrate 100 of the second region R2. The bottom dielectric structure 102 is located between the substrate 100 and the first stacked structure 104a and between the substrate 100 and the second stacked structure 104b. In detail, the bottom dielectric structure 103 has a main body portion 102a, a first protruding portion 102b, and a plurality of second protruding portions 102c. The first protrusion 102b extends from the body portion 102a between the body portion 102a and the first stack structure 104a, and the second protrusion portion 102c extends from the body portion 102a between the body portion 102a and the second stack structure 104b, respectively. In the present embodiment, the distance d between the top surface of the main body portion 102a adjacent to the first stacked structure 104a and the top surface of the main body portion 102a away from the first stacked structure 104a may be less than 100 Å. This distance d can be, for example, 10 Å to 100 Å. Compared with the sub-ditch defect in the prior art, the top surface of the main portion 102a adjacent to the first stacked structure 104a in the first region R1 of the present invention (which may be, for example, a peripheral circuit region) is less recessed, so that it can be increased The margin of subsequent processes.

In an embodiment, the first region R1 may be, for example, a peripheral circuit region, and the second region R2 may be, for example, a memory cell array region. The bottom width W1 of the first stacked structure 104a located in the first region R1 is greater than the bottom width W2 of the second stacked structure 104b located in the second region R2. In this embodiment, the bottom of the first stack structure 104a The width W1 may be, for example, 10 to 500 times the bottom width W2 of the second stacked structure 104b.

It should be noted that the above etching process alternates between the first etching step and the second etching step to alternately remove portions of the conductor layer 106 and the portion of the dielectric layer 108. Since the first etching step is different from the etching condition of the second etching step, the outline of the sidewall of the first stacked structure 104a and the outline of the sidewall of the second stacked structure 104b can be regarded as two in a giant view. Vertical tangent.

On the other hand, microscopically, the contour of the side wall of the first stacked structure 104a and the side wall of the second stacked structure 104b have concave and convex surfaces, respectively. In other words, the contour of the sidewall of the first stack structure 104a and the profile of the sidewall of the second stack structure 104b may each be, for example, a zig-Zag, a dumbbell shape, a corrugated paper shape, or a combination thereof.

In detail, taking the second stacked structure 104b as an example, as shown in FIG. 2A, the dielectric layer 108b of the second stacked structure 104b has a first top critical dimension TCD1, a first intermediate critical dimension MCD1, and a first bottom critical dimension BCD1. . Since the shape of the dielectric layer 108b can be, for example, an egg shape, the first intermediate key dimension MCD1 is greater than the first top critical dimension TCD1, and the first intermediate critical dimension MCD1 is greater than the first bottom critical dimension BCD1. In an embodiment, the sidewalls of the dielectric layer 108b may be curved. However, the present invention is not limited thereto. In other embodiments, the sidewall of the dielectric layer 108b may also be angular. On the other hand, the conductor layer 106b has a second top critical dimension TCD2, a second intermediate critical dimension MCD2, and a second bottom critical dimension BCD2. Since the shape of the conductor layer 106b can be, for example, a rectangle, the second intermediate key dimension MCD2 is equal to the second top critical dimension TCD2, and the second intermediate key The size MCD2 is equal to the second bottom critical dimension BCD2. As can be seen from FIG. 2A, the first intermediate key dimension MCD1 is larger than the second intermediate key dimension MCD2, and therefore, the contour of the sidewall of the second stack structure 104b exhibits a dumbbell shape. In an embodiment, the first intermediate critical dimension MCD1 may be, for example, 10 nm to 100 nm; and the second intermediate critical dimension MCD2 may be, for example, 10 nm to 100 nm.

In another embodiment, as shown in FIG. 2B, the dielectric layer 108b of the second stacked structure 104b has a third top critical dimension TCD3, a third intermediate critical dimension MCD3, and a third bottom critical dimension BCD3. Since the shape of the dielectric layer 108b can be, for example, an egg shape, the third intermediate key dimension MCD3 is greater than the third top critical dimension TCD3, and the third intermediate critical dimension MCD3 is greater than the third bottom critical dimension BCD3. Likewise, in an embodiment, the sidewalls of the dielectric layer 108b may be curved. However, the present invention is not limited thereto. In other embodiments, the sidewall of the dielectric layer 108b may also be angular. On the other hand, the conductor layer 106b has a fourth top critical dimension TCD4, a fourth intermediate critical dimension MCD4, and a fourth bottom critical dimension BCD4. Since the shape of the conductor layer 106b may be, for example, an hourglass shape, the fourth intermediate key dimension MCD4 is smaller than the fourth top critical dimension TCD4, and the fourth intermediate critical dimension MCD4 is smaller than the fourth bottom critical dimension BCD4. As can be seen from FIG. 2B, the third intermediate key size MCD3 is larger than the fourth intermediate key size MCD4, and therefore, the outline of the side wall of the second stacked structure 104b exhibits a corrugated shape. In an embodiment, the third intermediate critical dimension MCD3 may be, for example, 10 nm to 100 nm; and the fourth intermediate critical dimension MCD4 may be, for example, 10 nm to 100 nm. In addition, in the present embodiment, the first stack structure 104a also has a sidewall profile similar to that of the second stack structure 104b described above, and will not be described in detail herein.

Referring back to FIG. 1B, in the present embodiment, the distance H1 between the top surface of the first stacked structure 104a and the top surface of the main body portion 102a adjacent to the first stacked structure 104a may be, for example, 5000A to 20000A; the second stack structure The distance H2 between the top surface of 104b and the top surface of the body portion 102a adjacent to the second stack structure 104b may be, for example, 5000A to 20000A. The above distance H1 may be, for example, 1 to 1.1 times the distance H2. On the other hand, the thickness T1 of the first protrusion 102b may be, for example, 2000A to 5000A; the thickness T2 of the second protrusion 102c may be, for example, 2000A to 5000A. The thickness T1 of the first protruding portion 102b may be, for example, 1 to 2 times the thickness T2 of the second protruding portion 102c.

In summary, the method of fabricating the memory device of the present invention alternately performs the first etching step and the second etching step to alternately remove the conductor layer and the dielectric layer. Therefore, the stacked layers of the present invention having a plurality of conductor layers and a plurality of dielectric layers can be sequentially removed, thereby reducing the micro-loading effect between the memory cell array region and the peripheral circuit regions. Thus, in an embodiment, the distance between the top surface of the memory element adjacent the body portion of the first stack structure and the top surface of the body portion remote from the first stack structure may be less than 100 Å. In another aspect, in an embodiment, a distance between a top surface of the first stacked structure of the memory element and a top surface adjacent to the main body portion of the first stacked structure may be a top surface and a neighboring portion of the second stacked structure The distance between the top surfaces of the body portions of the second stacked structure is 1 to 1.1 times. In this way, the present invention can improve the problem of sub-drain defects in the peripheral circuit area to increase the margin of subsequent processes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art without departing from the invention. In the spirit and scope, the scope of protection of the present invention is subject to the definition of the appended patent application.

100‧‧‧Base

102a‧‧‧ Main body

102b‧‧‧First protrusion

102c‧‧‧second protrusion

103‧‧‧Bottom dielectric structure

104a‧‧‧First stacking structure

104b‧‧‧Second stacking structure

106a, 106b‧‧‧ conductor layer

108a, 108b‧‧‧ dielectric layer

110c, 110d‧‧‧ patterned mask layer

d, H1, H2‧‧‧ distance

Part P‧‧‧

R1‧‧‧ first district

R2‧‧‧Second District

T1, T2‧‧‧ thickness

W1, W2‧‧‧ width

Claims (10)

A memory device includes: a substrate having a first region and a second region; a first stacked structure on the substrate of the first region, the first stacked structure comprising: a plurality of first conductor layers and a plurality of first dielectric layers, wherein the first conductive layers and the first dielectric layers are stacked on each other; a plurality of second stacked structures are located on the substrate of the second region, and each of the second stacked structures includes a plurality of second conductor layers and a plurality of second dielectric layers, wherein the second conductor layers and the second dielectric layers are stacked on each other, wherein sidewalls of the first stacked structure and the second stacked structures The sidewalls each have a concave-convex surface; and a charge storage layer conformally covering the sidewalls of the first stacked structure and the second stacked structures. The memory element of claim 1, wherein the first stack structure and the sidewalls of the second stack structure comprise at least two perpendicular tangents. The memory device of claim 1, further comprising a bottom dielectric structure between the substrate and the first stacked structure and between the substrate and the second stacked structure, the bottom dielectric structure The utility model has a main body portion, a first protruding portion and a plurality of second protruding portions extending from the main body portion between the main body portion and the first stacking structure, and the second protruding portions are self-contained Extending the main body portion between the main body portion and the second stacking structure, wherein a top surface of the main body portion adjacent to the first stacking structure and a top surface of the main body portion away from the first stacking structure are The distance is less than 100Å. The memory element of claim 3, wherein a distance between a top surface of the main body portion adjacent to the first stacked structure and a top surface of the main body portion away from the first stacked structure is 10 Å to 100 Å. . A memory device includes: a substrate having a first region and a second region; a first stacked structure on the substrate of the first region, the first stacked structure comprising: a plurality of first conductor layers and a plurality of first dielectric layers, wherein the first conductive layers and the first dielectric layers are stacked on each other; a plurality of second stacked structures are located on the substrate of the second region, and each of the second stacked structures includes a plurality of second conductor layers and a plurality of second dielectric layers, wherein the second conductor layers and the second dielectric layers are stacked on each other; a bottom dielectric structure is located between the substrate and the first stacked structure Between the substrate and the second stacked structure, the bottom dielectric structure has a main body portion, a first protruding portion and a plurality of second protruding portions, the first protruding portion extending from the main body portion Between the main body portion and the first stacking structure, the second protruding portions extend from the main body portion between the main body portion and the second stacking structure, wherein the top surface of the first stacking structure is adjacent to the first stacking structure The body of the first stacked structure The distance between the top surfaces is 1 to 1.1 times the distance between the top surface of the second stacked structure and the top surface of the body portion adjacent to the second stacked structures; and a charge storage layer The first stacked structure and the sidewalls of the second stacked structures are covered. For example, the memory element described in claim 1 or 5, further includes: A third conductor layer covering the surface of the charge storage layer. A method of fabricating a memory device, comprising: providing a substrate having a first region and a second region; forming a bottom dielectric layer on the substrate, the bottom dielectric layer traversing the first region and the a second region; a stacked layer is formed on the bottom dielectric layer, the stacked layer includes a plurality of first conductive layers and a plurality of first dielectric layers, wherein the first conductive layers and the first dielectric layers Stacking on each other; and performing an etching process on the stacked layer, removing a portion of the stacked layer to form a first stacked structure on the substrate of the first region, and forming a plurality of the substrate on the second region The second stack structure, wherein the etching process comprises a plurality of first etching steps and a plurality of second etching steps, the first etching steps and the second etching steps alternate. The method of manufacturing the memory device of claim 7, wherein the first etching step comprises removing a portion of the first conductor layers, and the second etching step comprises removing a portion of the first dielectric layers a layer, wherein the first etching steps are different from the reaction gases used in the second etching steps. The method of manufacturing the memory device of claim 7, after performing the etching process, further comprising: forming a charge storage layer on the first stacked structure and the second stacked structures; and the charge A second conductor layer is formed on the storage layer. The method for fabricating a memory device according to claim 7, further comprising removing a portion of the bottom dielectric layer to form a bottom dielectric structure, the bottom dielectric structure having a body a first protruding portion and a plurality of second protruding portions extending from the main body portion between the main body portion and the first stacking structure, and the second protruding portions are from the main body portion The extension is located between the main body portion and the second stack structures.