TWI565024B - Electrostatic discharge protection structure - Google Patents

Description

Electrostatic discharge protection structure

This invention relates to a semiconductor structure and, more particularly, to an electrostatic discharge protection structure.

During the manufacture or use of semiconductor components, excessive current generated by various types of electrostatic discharge (ESD) is a major factor causing damage to semiconductor components or functional circuits, and affects the efficiency of the process and the yield of the product.

After entering the deep sub-micron or even nano-scale process, the resistance of the ESD is further improved because the semiconductor element of the reduced size is relatively inferior to ESD tolerance. There are many ESD protection designs that prevent ESD, but they affect the performance of the semiconductor components or functional circuits they protect. Therefore, it is the object of the present invention to provide a good ESD protection capability without affecting the performance of a semiconductor component or a functional circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrostatic discharge protection structure including a semiconductor substrate, a well region, a first conductive region, a second conductive region, and a first doped region. A plurality of isolation structures are completed on the semiconductor substrate. The well region has a first type of conductive carrier disposed between the isolation structures. The first conductive region and the second conductive region have second type conductive carriers, respectively disposed on the semiconductor substrate in the well region surface. The first doped region is disposed under the first conductive region to form a high resistance region in the electrostatic discharge protection structure.

The invention forms a high resistance zone in various types of electrostatic discharge protection structures, and is used for adjusting the trigger voltage of the electrostatic discharge protection structure and the distribution path of the electrostatic discharge current through the electrostatic discharge protection structure, thereby effectively improving the electrostatic discharge protection structure. The ability to protect various circuit components and maintain the performance of various circuit components.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A-1E are schematic cross-sectional views showing parts and structures of an embodiment of the present invention.

Referring to FIG. 1A, a semiconductor substrate 100 is provided. The semiconductor substrate 100 is formed with a plurality of isolation structures 101. The partial isolation structures define an ESD protection structure region 110 and a circuit component region 120. The well region 111, 121 having the first type of conductive carrier is completed in the ESD protection structure region 110 and the circuit component region 120; the first conduction region 112, 122 and the second conduction region 113 having the second type of conductive carrier, 123. The well regions 111, 121 are disposed between the isolation structures 101, and the first conductive regions 112, 122 and the second conductive regions 113, 123 are respectively disposed on the surface of the semiconductor substrate 100 in the well regions 111, 121, wherein the first conductive regions 112 The concentration of the second type conductive carrier in the 122 and the second conducting regions 113, 123 is higher than the concentration of the first type conductive carrier in the well regions 111, 121.

In the present embodiment, the semiconductor substrate 100 is a germanium substrate, which also has a doped version of the first type of conductive carrier. Manufacturing electrostatic discharge protection structure 110 can be integrated For the manufacturing process of the functional device region 120, for example, a field effect transistor, a complementary field effect transistor or a bipolar complementary field effect transistor (MOS, CMOS or Bi-CMOS) process. In detail, first, in the ESD protection structure region 110 and the circuit component region 120, a doping process of the first type of conductive carriers is performed a plurality of times to form well regions 111 and 121 having the first type of conductive carriers. After the gate structures 115 and 125 are formed, a mask is formed on the surface of the substrate 100 to expose a portion of the surface of the electrostatic discharge protection structure 110 and a portion of the circuit element region 120, and a doping process of the second type conductive carrier is performed. The doping concentration of the second conductivity type carrier is higher than the doping concentration of the first conductivity type carrier on the surface of the well regions 111, 121, and is in the exposed portion of the electrostatic discharge protection structure region 110 and the exposed portion of the circuit component region 120. A lightly doped region having a second type of conductive carrier is formed. Then, after the gate sidewalls 115a and 125a are formed, a mask is formed on the surface of the substrate 100 to expose a portion of the surface of the lightly doped region, and then a doping process of the second type conductive carrier is performed, and the second conductive type is doped. The concentration of the sub-concentration is higher than that of the lightly doped region, and light doping of the first conductive regions 112, 122, the second conductive regions 113, 123 and the low-concentration second-type conductive carriers having a high concentration of the second-type conductive carriers is formed. Areas 112a, 122a, 113a, 123a (lightly doped drain, abbreviated as LDD). Thereafter, a mask may be formed on the first conductive regions 112, 122, the second conductive regions 113, 123, the gate structures 115, 125, and the gate sidewalls 115a, 125a to expose portions of the electrostatic discharge protection structure 110 and portions thereof. On the surface of the circuit component region 120, a doping process of the first type of conductive carriers is performed to increase the concentration of the first type of conductive carriers in the partial well regions 111 and 121, thereby forming a third conduction having a high concentration of the first type of conductive carriers. Areas 114, 124.

1B to 1E are only cross-sectional views of the electrostatic discharge protection structure region 110 of FIG. 1A.

Referring to FIG. 1B, a mask 130 is formed on the surface of the semiconductor substrate 100, The mask 130 has an opening 130a to expose only a portion of the first conductive region 112 surface of the portion of the ESD protection structure region 110. Next, a first doping process is performed using the mask 130 to dope the first type of conductive carriers in the well region 111 that provides the dopant neutralization portion of the second type of conductive carrier. In this embodiment, the first type of conductive carrier is a P type carrier, the second type of conductive carrier is an N type carrier, and the first doping process has an electron carrier. The dopant, for example, a phosphorus atom (P) or an arsenic atom (As), the concentration of a hole carrier in the P well region of the radical neutralizing portion. It is worth mentioning that in other embodiments, the first type of conductive carrier can be an electron, the second type of conductive carrier can be a hole, and the first doping process can provide a dopant for the hole carrier. For example: a boron atom (B) or a gallium atom (Ga), an electron carrier in the N-well region of the neutralizing portion. The present invention does not limit the corresponding conductive carrier type between the first type of conductive carrier and the second type of conductive carrier.

Referring to FIG. 1C, after the first doping process is completed, a first doping region 116 is formed under the exposed portion of the N+ first conducting region 112, wherein the first doping region 116 and the N+ first conducting region 112 are separated from each other. There is a P well area 111 that is not electrically neutralized. Further, the present invention can control the formation of the first doping region 116 by adjusting process conditions of the first doping process, such as dopant concentration, doping time, doping angle, doping energy, annealing diffusion, and the like. The type, concentration or doping range and position of the conductive carrier. In this embodiment, after the first doping process electrically neutralizes the hole carrier in the P well region, the first doping region 116 is formed to have a low concentration of the electron carrier region (N-), in other In an embodiment, the first doped region 116 may be an electrically neutral or low concentration hole carrier region (P-). In general, when the concentration of the conductive carrier in the first doping region is lower than the concentration of the conductive carrier in the well region, when the electrostatic discharge protection structure is triggered to turn on the electrostatic discharge current (abbreviation: ESD current), the first doping The region 116 forms a high resistance region, which can be adjusted by using different resistance profiles in the electrostatic discharge protection structure. The electric discharge protection structure turns on the path of the ESD current.

Referring to FIG. 1D, in the present invention, the second masking process may be selectively performed by the same mask 130 to increase the first type of conductive carriers in the well region that is not electrically neutralized, and the exposed portion is exposed. A second doped region 117 is formed between the first conductive region 112 and the first doped region 116. Briefly, in the electrostatic discharge protection structure 110, the first conductive region 112, the well region 111 and the second conductive region 113 constitute a parasitic bipolar junction transistor (abbreviated as BJT); the first conductive region 112. The well region 111 and the third conductive region form a series of parasitic diodes 111b (parasitic diodes, as indicated by the dotted line circuit symbols). In this embodiment, the parasitic bipolar transistor is an NPN type BJT. The second doping process is doped with a P type dopant to increase a portion of the hole carrier in the P well region 111 that is not electrically neutralized, because the P+ second doping region 117 is bonded to the N+ first conduction region. Below, the P+ second doped region 117 and the N+ first conductive region 112 form a high concentration PN junction interface (PN junction), which can moderately reduce the breakdown voltage of the BJT.

Referring to FIG. 1E, after the mask 130 is removed, the ESD protection structure 110 can cooperate with a salicide process in the circuit component region, in the first conductive region 112, the second conductive region 113, and the third conductive region 114. Metal halide layers 112b, 113b, 114b, and 115b are formed in the gate structure 115, and each of the metal halide layers formed on the surface of the germanium substrate can serve as a contact region for internal circuit wiring. In this embodiment, the length dimension of the metal telluride layer 112b may also be selectively formed, for example, a sacilide blocking process is performed to adjust the conduction resistance of the first conductive region 112 (as shown in FIG. A line resistance symbol 112c) in a conduction region 112. Thereafter, various internal circuit wiring processes are performed in which the N+ first conduction region 112 can be electrically connected to the drain voltage V1; the N+ second conduction region 112 and the P+ third conduction region can be electrically connected to the ground voltage V2. Complete various internal circuits After the connection, when the ESD current occurs, the ESD current can be quickly turned to the ground through the parasitic BJT111a and the parasitic diode 111b in the electrostatic discharge protection structure 110, and the energy released by the ESD current is evenly dispersed to reduce the electrostatic discharge protection structure and The risk of the circuit component area being destroyed; when the normal signal is output/input, the electrostatic discharge protection structure is in a closed state, because the first doping region 116 having a high resistance value is disposed in the electrostatic discharge protection structure 110, and is not abnormally turned on. A leakage current is generated.

Referring to FIG. 2, FIG. 2 is a cross-sectional view showing a portion of a structure of another embodiment of the present invention. The electrostatic discharge protection structure 210 is a bipolar transistor (BJT) type structure. As shown in the embodiment of FIG. 1, the electrostatic discharge protection structure 210 can also be integrated into the process of various circuit components, and the electrostatic discharge protection structure 210 and the electrostatic discharge. The difference between the first conductive region 112 and the second conductive region 113 is that an isolation structure 101 is disposed between the first conductive region 112 and the second conductive region 113. The gate structure and the lightly doped region are not formed in the electrostatic discharge protection structure 210.

Finally, please refer to FIG. 3. FIG. 3 is a cross-sectional view showing a partial structure of another embodiment of the present invention. The electrostatic discharge protection structure 310 is a structure of a silicon controller rectifier (SCR) type. As shown in the embodiment of FIG. 2, an isolation structure 101 is disposed between the first conductive region 112 and the second conductive region 113. The difference between the electrostatic discharge protection structure 310 and the electrostatic discharge protection structure 210 is that the second doping region 117 is respectively Bonding to the first conductive region 112 and the first doping region 116, the first doping region covers the periphery of the second doping region 117 to make the first conductive region 112, the second doping region 117 and the first doping region 116 Two PN joint faces are formed between them. The first conductive region 112, the second doped region 117, the first doped region 116, and the third conductive region 114 constitute a germanium rectifier controller. When ESD current occurs, the ESD current can be conducted to ground via the path of the above-described 矽 rectification controller.

The invention integrates the process of the existing circuit components, and does not need to increase the process cost, only benefit By using a mask to do the doping process, a high resistance region can be formed in various types of ESD protection structures to adjust the trigger voltage of the ESD protection structure and the distribution path of the ESD current through the ESD protection structure. Turn on various types of ESD current. In summary, the technical solution of the present invention can effectively improve the protection capability of the electrostatic discharge protection structure, and achieve the effects of protecting various circuit components and maintaining the performance of various circuit components.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Semiconductor substrate

101‧‧‧Isolation structure

110, 210, 310‧‧‧ Electrostatic discharge protection structure

111, 121‧‧‧ Well Area

111a‧‧‧Bipolar transistor

111b‧‧‧ diode

112, 122‧‧‧ first conduction zone

112a, 113a, 122a, 123a‧‧‧lightly doped areas

112b, 113b, 114b, 115b‧‧‧ metal telluride layer

112c‧‧‧resistance

113, 123‧‧‧Second conduction zone

114, 124‧‧‧ third conduction zone

115, 125‧‧ ‧ gate structure

115a, 125a‧‧‧ gate sidewall

116‧‧‧First doped area

117‧‧‧Second doped area

120‧‧‧Circuit component area

130‧‧‧ mask

130a‧‧‧Mask opening

V1‧‧‧汲polar voltage

V2‧‧‧ Grounding voltage

1A-1E are schematic cross-sectional views showing parts and structures of an embodiment of the present invention.

2 is a cross-sectional view showing a portion of a structure of another embodiment of the present invention.

3 is a cross-sectional view showing a portion of a structure according to still another embodiment of the present invention.

100‧‧‧Semiconductor substrate

101‧‧‧Isolation structure

110‧‧‧Electrostatic discharge protection structure

111‧‧‧ Well Area

111a‧‧‧Bipolar transistor

111b‧‧‧ diode

112‧‧‧First conduction zone

112a, 113a‧‧‧lightly doped areas

112b, 113b, 114b, 115b‧‧‧ metal telluride layer

112c‧‧‧resistance

113‧‧‧Second conduction zone

114‧‧‧ third conduction zone

115‧‧‧ gate structure

115a‧‧‧ gate sidewall

116‧‧‧First doped area

117‧‧‧Second doped area

V1‧‧‧汲polar voltage

V2‧‧‧ Grounding voltage

Claims (8)

An electrostatic discharge protection structure comprising: a semiconductor substrate having a plurality of isolation structures formed thereon; a gate structure formed on a surface of the semiconductor substrate; and a well region having a first type of conductive carrier formed Disposed between the isolation structures in the semiconductor substrate; a first conductive region and a second conductive region, having second conductivity carriers, respectively disposed on the surface of the semiconductor substrate in the well region Two sides of the structure; and a first doped region disposed under the first conductive region, and the first doped region is not located directly under the gate structure when viewed from a cross section, wherein the The first doped region has a first type of conductive carrier, and the concentration of the first type of conductive carrier in the first doped region is less than the concentration of the first type of conductive carrier in the well region. The electrostatic discharge protection structure of claim 1, wherein the first doped region and the first conductive region are separated by the well region. The electrostatic discharge protection structure of claim 1, further comprising a second doped region having a first type of conductive carrier disposed between the first doped region and the first conductive region, wherein the The concentration of the first conductivity type carrier in the second doping region is higher than the concentration of the first conductive carrier in the well region. The electrostatic discharge protection structure of claim 3, wherein the second doped region is bonded below the first conductive region. The electrostatic discharge protection structure of claim 4, wherein the first doped region and the second doped region are separated by the well region. The electrostatic discharge protection structure according to claim 1, wherein the first type of conductive carrier is a hole, and the second type of conductive carrier is an electron. The electrostatic discharge protection structure of claim 6, further comprising a third conductive region having a first type of conductive carrier disposed on the surface of the semiconductor substrate in the well region, the first conductive region, the first The well region is separated from the second conductive region and the third conductive region, wherein the concentration of the first type conductive carrier in the third conductive region is higher than the concentration of the first type conductive carrier in the well region. The electrostatic discharge protection structure of claim 7, wherein the first conductive region is adapted to be coupled to a high voltage source, and the second conductive region and the third conductive region are adapted to be coupled to a low voltage source.