TWI563537B - Method for semiconductor self-aligned patterning - Google Patents
Method for semiconductor self-aligned patterningInfo
- Publication number
- TWI563537B TWI563537B TW103110615A TW103110615A TWI563537B TW I563537 B TWI563537 B TW I563537B TW 103110615 A TW103110615 A TW 103110615A TW 103110615 A TW103110615 A TW 103110615A TW I563537 B TWI563537 B TW I563537B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor self
- aligned patterning
- patterning
- aligned
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/951,717 US9318412B2 (en) | 2013-07-26 | 2013-07-26 | Method for semiconductor self-aligned patterning |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201505071A TW201505071A (zh) | 2015-02-01 |
TWI563537B true TWI563537B (en) | 2016-12-21 |
Family
ID=52389800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103110615A TWI563537B (en) | 2013-07-26 | 2014-03-21 | Method for semiconductor self-aligned patterning |
Country Status (3)
Country | Link |
---|---|
US (1) | US9318412B2 (zh) |
CN (1) | CN104347350B (zh) |
TW (1) | TWI563537B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9484202B1 (en) * | 2015-06-03 | 2016-11-01 | Applied Materials, Inc. | Apparatus and methods for spacer deposition and selective removal in an advanced patterning process |
US9558942B1 (en) | 2015-09-29 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | High density nanowire array |
US10428241B2 (en) * | 2017-10-05 | 2019-10-01 | Fujifilm Electronic Materials U.S.A., Inc. | Polishing compositions containing charged abrasive |
CN108550522B (zh) * | 2018-04-27 | 2020-09-04 | 上海集成电路研发中心有限公司 | 一种多次图形化的方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060240361A1 (en) * | 2005-04-21 | 2006-10-26 | Ji-Young Lee | Method of forming small pitch pattern using double spacers |
US20060273456A1 (en) * | 2005-06-02 | 2006-12-07 | Micron Technology, Inc., A Corporation | Multiple spacer steps for pitch multiplication |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6942811B2 (en) * | 1999-10-26 | 2005-09-13 | Reflectivity, Inc | Method for achieving improved selectivity in an etching process |
TW480680B (en) * | 2001-04-03 | 2002-03-21 | Nanya Technology Corp | Method for producing self-aligned separated gate-type flash memory cell |
WO2008059440A2 (en) | 2006-11-14 | 2008-05-22 | Nxp B.V. | Double patterning for lithography to increase feature spatial density |
KR101102422B1 (ko) * | 2007-02-28 | 2012-01-05 | 도쿄엘렉트론가부시키가이샤 | 비결정 탄소막의 형성 방법, 비결정 탄소막, 다층 레지스트막, 반도체 장치의 제조 방법 및 컴퓨터 가독 기억 매체 |
US9640396B2 (en) | 2009-01-07 | 2017-05-02 | Brewer Science Inc. | Spin-on spacer materials for double- and triple-patterning lithography |
US8026179B2 (en) * | 2009-04-09 | 2011-09-27 | Macronix International Co., Ltd. | Patterning method and integrated circuit structure |
JP5698923B2 (ja) | 2009-06-26 | 2015-04-08 | ローム・アンド・ハース・エレクトロニック・マテリアルズ,エル.エル.シー. | 自己整合型スペーサー多重パターニング方法 |
US8314034B2 (en) * | 2010-12-23 | 2012-11-20 | Intel Corporation | Feature size reduction |
-
2013
- 2013-07-26 US US13/951,717 patent/US9318412B2/en active Active
-
2014
- 2014-03-21 TW TW103110615A patent/TWI563537B/zh active
- 2014-04-04 CN CN201410135484.0A patent/CN104347350B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060240361A1 (en) * | 2005-04-21 | 2006-10-26 | Ji-Young Lee | Method of forming small pitch pattern using double spacers |
US20060273456A1 (en) * | 2005-06-02 | 2006-12-07 | Micron Technology, Inc., A Corporation | Multiple spacer steps for pitch multiplication |
Also Published As
Publication number | Publication date |
---|---|
TW201505071A (zh) | 2015-02-01 |
CN104347350B (zh) | 2017-06-13 |
CN104347350A (zh) | 2015-02-11 |
US20150028459A1 (en) | 2015-01-29 |
US9318412B2 (en) | 2016-04-19 |
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