TWI562254B - Metal on both sides with clock gated power and signal routing underneath - Google Patents

Metal on both sides with clock gated power and signal routing underneath

Info

Publication number
TWI562254B
TWI562254B TW104114137A TW104114137A TWI562254B TW I562254 B TWI562254 B TW I562254B TW 104114137 A TW104114137 A TW 104114137A TW 104114137 A TW104114137 A TW 104114137A TW I562254 B TWI562254 B TW I562254B
Authority
TW
Taiwan
Prior art keywords
metal
sides
signal routing
gated power
clock gated
Prior art date
Application number
TW104114137A
Other languages
English (en)
Other versions
TW201606892A (zh
Inventor
Donald W Nelson
Patrick Morrow
Kimin Jun
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201606892A publication Critical patent/TW201606892A/zh
Application granted granted Critical
Publication of TWI562254B publication Critical patent/TWI562254B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW104114137A 2014-06-16 2015-05-04 Metal on both sides with clock gated power and signal routing underneath TWI562254B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462012822P 2014-06-16 2014-06-16
PCT/US2014/057920 WO2015195152A1 (en) 2014-06-16 2014-09-27 Metal on both sides with clock gated power and signal routing underneath

Publications (2)

Publication Number Publication Date
TW201606892A TW201606892A (zh) 2016-02-16
TWI562254B true TWI562254B (en) 2016-12-11

Family

ID=54935949

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104114137A TWI562254B (en) 2014-06-16 2015-05-04 Metal on both sides with clock gated power and signal routing underneath

Country Status (7)

Country Link
US (2) US10186484B2 (zh)
EP (1) EP3155666B1 (zh)
JP (1) JP2017525129A (zh)
KR (2) KR102312250B1 (zh)
CN (1) CN106463530A (zh)
TW (1) TWI562254B (zh)
WO (1) WO2015195152A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015195152A1 (en) * 2014-06-16 2015-12-23 Intel Corporation Metal on both sides with clock gated power and signal routing underneath
US11430740B2 (en) * 2017-03-29 2022-08-30 Intel Corporation Microelectronic device with embedded die substrate on interposer
US10943045B2 (en) * 2018-01-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same
US11450600B2 (en) * 2020-05-12 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices including decoupling capacitors
DE102020122823B4 (de) 2020-05-12 2022-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtungen mit entkopplungskondensatoren
US11437379B2 (en) 2020-09-18 2022-09-06 Qualcomm Incorporated Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits
US11404374B2 (en) 2020-09-30 2022-08-02 Qualcomm Incorporated Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060012029A1 (en) * 2004-07-15 2006-01-19 Nec Corporation Semiconductor device
US20060115943A1 (en) * 2001-11-05 2006-06-01 Zycube Co., Ltd. Method of fabricating semiconductor device using low dielectric constant material film
TW201039439A (en) * 2010-03-18 2010-11-01 Omnivision Tech Inc Apparatus having thinner interconnect line for photodetector array and thicker interconnect line for periphery region
US8004085B2 (en) * 2007-03-30 2011-08-23 Nec Corporation Semiconductor device and method of manufacturing semiconductor device

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
JP3917683B2 (ja) * 1996-04-25 2007-05-23 株式会社ルネサステクノロジ 半導体集積回路装置
JP4058234B2 (ja) * 1999-12-22 2008-03-05 株式会社東芝 半導体装置
US6483176B2 (en) * 1999-12-22 2002-11-19 Kabushiki Kaisha Toshiba Semiconductor with multilayer wiring structure that offer high speed performance
JP2007335888A (ja) * 2000-12-18 2007-12-27 Renesas Technology Corp 半導体集積回路装置
CN100499125C (zh) * 2005-07-06 2009-06-10 精工爱普生株式会社 半导体装置
US20080277778A1 (en) 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
JP2009054760A (ja) * 2007-08-27 2009-03-12 Nec Electronics Corp 半導体装置、配線設計方法、配線設計装置、及びプログラム
JP5413371B2 (ja) * 2008-10-21 2014-02-12 日本電気株式会社 半導体装置及びその製造方法
JP2011187473A (ja) * 2010-03-04 2011-09-22 Nec Corp 半導体素子内蔵配線基板
US8525342B2 (en) * 2010-04-12 2013-09-03 Qualcomm Incorporated Dual-side interconnected CMOS for stacked integrated circuits
US20120061794A1 (en) * 2010-09-10 2012-03-15 S.O.I. Tec Silicon On Insulator Technologies Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods
JP5876249B2 (ja) * 2011-08-10 2016-03-02 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2013183119A (ja) 2012-03-05 2013-09-12 Elpida Memory Inc 半導体装置及びその設計方法
WO2014013581A1 (ja) * 2012-07-19 2014-01-23 ルネサスエレクトロニクス株式会社 半導体装置
WO2015195152A1 (en) * 2014-06-16 2015-12-23 Intel Corporation Metal on both sides with clock gated power and signal routing underneath

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060115943A1 (en) * 2001-11-05 2006-06-01 Zycube Co., Ltd. Method of fabricating semiconductor device using low dielectric constant material film
US20060012029A1 (en) * 2004-07-15 2006-01-19 Nec Corporation Semiconductor device
US8004085B2 (en) * 2007-03-30 2011-08-23 Nec Corporation Semiconductor device and method of manufacturing semiconductor device
TW201039439A (en) * 2010-03-18 2010-11-01 Omnivision Tech Inc Apparatus having thinner interconnect line for photodetector array and thicker interconnect line for periphery region

Also Published As

Publication number Publication date
US10658291B2 (en) 2020-05-19
WO2015195152A1 (en) 2015-12-23
JP2017525129A (ja) 2017-08-31
EP3155666B1 (en) 2021-05-12
EP3155666A1 (en) 2017-04-19
US20170077030A1 (en) 2017-03-16
TW201606892A (zh) 2016-02-16
KR20210125609A (ko) 2021-10-18
US10186484B2 (en) 2019-01-22
CN106463530A (zh) 2017-02-22
KR20170016325A (ko) 2017-02-13
US20190122985A1 (en) 2019-04-25
KR102312250B1 (ko) 2021-10-14
KR102502496B1 (ko) 2023-02-23
EP3155666A4 (en) 2018-03-14

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