TWI561940B - - Google Patents

Info

Publication number
TWI561940B
TWI561940B TW103122342A TW103122342A TWI561940B TW I561940 B TWI561940 B TW I561940B TW 103122342 A TW103122342 A TW 103122342A TW 103122342 A TW103122342 A TW 103122342A TW I561940 B TWI561940 B TW I561940B
Authority
TW
Taiwan
Application number
TW103122342A
Other versions
TW201520702A (zh
Inventor
lian-sheng Zhong
Original Assignee
Huang Tian Xing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huang Tian Xing filed Critical Huang Tian Xing
Priority to TW103122342A priority Critical patent/TW201520702A/zh
Priority to US14/546,645 priority patent/US9490181B2/en
Publication of TW201520702A publication Critical patent/TW201520702A/zh
Priority to US15/281,083 priority patent/US10186443B2/en
Application granted granted Critical
Publication of TWI561940B publication Critical patent/TWI561940B/zh

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/682—Mask-wafer alignment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70141—Illumination system adjustment, e.g. adjustments during exposure or alignment during assembly of illumination system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW103122342A 2013-11-19 2014-06-27 對準誤差補償方法、系統，及圖案化方法 TW201520702A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW103122342A TW201520702A (zh) 2013-11-19 2014-06-27 對準誤差補償方法、系統，及圖案化方法
US14/546,645 US9490181B2 (en) 2013-11-19 2014-11-18 Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning
US15/281,083 US10186443B2 (en) 2013-11-19 2016-09-30 Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW102142045 2013-11-19
TW103122342A TW201520702A (zh) 2013-11-19 2014-06-27 對準誤差補償方法、系統，及圖案化方法

Publications (2)

Publication Number Publication Date
TW201520702A TW201520702A (zh) 2015-06-01
TWI561940B true TWI561940B (zh) 2016-12-11

Family

ID=53173697

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103122342A TW201520702A (zh) 2013-11-19 2014-06-27 對準誤差補償方法、系統，及圖案化方法

Country Status (2)

Country Link
US (2) US9490181B2 (zh)
TW (1) TW201520702A (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9753373B2 (en) * 2015-11-12 2017-09-05 United Microelectronics Corp. Lithography system and semiconductor processing process
US10859924B2 (en) 2017-11-15 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device and system for performing the same
CN111272126A (zh) * 2018-12-05 2020-06-12 长春设备工艺研究所 零件壳体复杂曲面测量误差分析与建模方法
CN110400745B (zh) * 2019-07-17 2021-04-13 上海华力集成电路制造有限公司 快速补偿芯片内图形线宽均匀性的方法
JP2022065794A (ja) * 2020-10-16 2022-04-28 イビデン株式会社 プリント配線板の検査方法
CN114690593A (zh) * 2020-12-30 2022-07-01 科磊股份有限公司 一种制造集成电路的方法和系统
CN114678282B (zh) * 2022-05-27 2022-08-02 湖北三维半导体集成创新中心有限责任公司 一种键合补偿方法及装置、芯片再布线方法、键合结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200416500A (en) * 2002-09-20 2004-09-01 Asml Netherlands Bv Alignment systems and methods for lithographic systems
US20050186517A1 (en) * 2004-02-19 2005-08-25 Asml Holding N.V. Overlay correction by reducing wafer slipping after alignment
TW201003826A (en) * 2008-05-07 2010-01-16 Lam Res Corp Dynamic alignment of wafers using compensation values obtained through a series of wafer movements
CN101900945A (zh) * 2009-05-27 2010-12-01 中芯国际集成电路制造(上海)有限公司 叠对误差补偿方法
TW201126638A (en) * 2009-09-22 2011-08-01 Ev Group E Thallner Gmbh Device for alignment of two substrates
CN103026299A (zh) * 2010-02-26 2013-04-03 密克罗尼克麦达塔公司 用于执行图案对准的方法和装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4709511B2 (ja) * 2004-08-18 2011-06-22 株式会社東芝 マスクパターン補正方法、マスクパターン補正プログラム、フォトマスクの作製方法及び半導体装置の製造方法
US7187400B2 (en) * 2004-12-01 2007-03-06 Lexmark International, Inc. Method and apparatus for compensating for image misalignment due to variations in laser power in a bi-directional raster imaging system
US7415319B2 (en) * 2006-04-04 2008-08-19 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US8092961B2 (en) * 2008-04-28 2012-01-10 Renesas Electronics Corporation Position aligning apparatus, position aligning method, and semiconductor device manufacturing method
JP5840584B2 (ja) * 2012-09-06 2016-01-06 株式会社東芝 露光装置、露光方法および半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200416500A (en) * 2002-09-20 2004-09-01 Asml Netherlands Bv Alignment systems and methods for lithographic systems
US20050186517A1 (en) * 2004-02-19 2005-08-25 Asml Holding N.V. Overlay correction by reducing wafer slipping after alignment
TW201003826A (en) * 2008-05-07 2010-01-16 Lam Res Corp Dynamic alignment of wafers using compensation values obtained through a series of wafer movements
CN101900945A (zh) * 2009-05-27 2010-12-01 中芯国际集成电路制造(上海)有限公司 叠对误差补偿方法
TW201126638A (en) * 2009-09-22 2011-08-01 Ev Group E Thallner Gmbh Device for alignment of two substrates
CN103026299A (zh) * 2010-02-26 2013-04-03 密克罗尼克麦达塔公司 用于执行图案对准的方法和装置

Also Published As

Publication number Publication date
TW201520702A (zh) 2015-06-01
US10186443B2 (en) 2019-01-22
US20170018447A1 (en) 2017-01-19
US20150140693A1 (en) 2015-05-21
US9490181B2 (en) 2016-11-08

Similar Documents

Publication Publication Date Title
BR112015007533A2 (zh)
BR112016000707A2 (zh)
BR112014018502A2 (zh)
BR112016008639A2 (zh)
BR112014019326A2 (zh)
BR112014018516A2 (zh)
BR112014020341A2 (zh)
BR112014018480A2 (zh)
BR112014017855A2 (zh)
BR112014021878A2 (zh)
BR112016001596A2 (zh)
BR112016000233A2 (zh)
BR112016000950A2 (zh)
BR112014018468A2 (zh)
BR112014018207A2 (zh)
BR112014017901A2 (zh)
BR112014019204A2 (zh)
BR112015015948A2 (zh)
BR112014018578A2 (zh)
BR112014018483A2 (zh)
BR112014017794A2 (zh)
BR112014017601A2 (zh)
BR112015015312A2 (zh)
BR112014018353A2 (zh)
TWI561940B (zh)