TWI561460B - Methods for self-aligned patterning and iterative self-aligned patterning - Google Patents
Methods for self-aligned patterning and iterative self-aligned patterningInfo
- Publication number
- TWI561460B TWI561460B TW104134168A TW104134168A TWI561460B TW I561460 B TWI561460 B TW I561460B TW 104134168 A TW104134168 A TW 104134168A TW 104134168 A TW104134168 A TW 104134168A TW I561460 B TWI561460 B TW I561460B
- Authority
- TW
- Taiwan
- Prior art keywords
- self
- aligned patterning
- methods
- iterative
- patterning
- Prior art date
Links
- 238000000059 patterning Methods 0.000 title 2
- 238000000034 method Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/517,252 US9685332B2 (en) | 2014-10-17 | 2014-10-17 | Iterative self-aligned patterning |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201615535A TW201615535A (zh) | 2016-05-01 |
TWI561460B true TWI561460B (en) | 2016-12-11 |
Family
ID=55749610
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104134168A TWI561460B (en) | 2014-10-17 | 2015-10-19 | Methods for self-aligned patterning and iterative self-aligned patterning |
Country Status (4)
Country | Link |
---|---|
US (1) | US9685332B2 (zh) |
KR (3) | KR20160045527A (zh) |
CN (1) | CN106158600A (zh) |
TW (1) | TWI561460B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9673059B2 (en) * | 2015-02-02 | 2017-06-06 | Tokyo Electron Limited | Method for increasing pattern density in self-aligned patterning integration schemes |
US9449880B1 (en) * | 2015-02-26 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin patterning methods for increased process margin |
US9997369B2 (en) | 2016-09-27 | 2018-06-12 | International Business Machines Corporation | Margin for fin cut using self-aligned triple patterning |
CN108010966B (zh) * | 2016-10-28 | 2020-08-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
US10832908B2 (en) * | 2016-11-11 | 2020-11-10 | Lam Research Corporation | Self-aligned multi-patterning process flow with ALD gapfill spacer mask |
US9941164B1 (en) * | 2016-12-05 | 2018-04-10 | Samsung Electronics Co., Ltd. | Self-aligned block patterning with density assist pattern |
US10483108B2 (en) * | 2017-04-28 | 2019-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US10643858B2 (en) | 2017-10-11 | 2020-05-05 | Samsung Electronics Co., Ltd. | Method of etching substrate |
WO2019108237A1 (en) | 2017-11-30 | 2019-06-06 | Intel Corporation | Fin patterning for advanced integrated circuit structure fabrication |
US11404275B2 (en) | 2018-03-02 | 2022-08-02 | Lam Research Corporation | Selective deposition using hydrolysis |
CN108511330A (zh) * | 2018-03-29 | 2018-09-07 | 上海华力集成电路制造有限公司 | 掩模图案的形成方法、半导体器件和集成电路 |
EP4256161A1 (en) * | 2021-01-08 | 2023-10-11 | Labforinvention | Window coating transmissible to wireless communication signals |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130244437A1 (en) * | 2012-03-15 | 2013-09-19 | Globalfoundries Inc. | Methods of forming features on an integrated circuit product using a novel compound sidewall image transfer technique |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100310257B1 (ko) | 1999-08-07 | 2001-09-29 | 박종섭 | 반도체소자의 미세 패턴의 제조방법 |
US6632741B1 (en) * | 2000-07-19 | 2003-10-14 | International Business Machines Corporation | Self-trimming method on looped patterns |
KR100387242B1 (ko) * | 2001-05-26 | 2003-06-12 | 삼성전기주식회사 | 반도체 발광소자의 제조방법 |
US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
US7807575B2 (en) * | 2006-11-29 | 2010-10-05 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices |
KR100866723B1 (ko) | 2006-12-28 | 2008-11-05 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 미세 패턴 형성 방법 |
US7972959B2 (en) | 2008-12-01 | 2011-07-05 | Applied Materials, Inc. | Self aligned double patterning flow with non-sacrificial features |
KR20120019917A (ko) * | 2010-08-27 | 2012-03-07 | 삼성전자주식회사 | 반도체 장치의 제조방법 |
US9384962B2 (en) * | 2011-04-07 | 2016-07-05 | United Microelectronics Corp. | Oxygen treatment of replacement work-function metals in CMOS transistor gates |
JP5710436B2 (ja) * | 2011-09-26 | 2015-04-30 | 株式会社東芝 | パターン形成方法 |
US8836049B2 (en) * | 2012-06-13 | 2014-09-16 | United Microelectronics Corp. | Semiconductor structure and process thereof |
CN103779191B (zh) * | 2012-10-26 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
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2014
- 2014-10-17 US US14/517,252 patent/US9685332B2/en active Active
- 2014-12-18 KR KR1020140182989A patent/KR20160045527A/ko active Search and Examination
-
2015
- 2015-04-22 CN CN201510193323.1A patent/CN106158600A/zh active Pending
- 2015-10-19 TW TW104134168A patent/TWI561460B/zh active
-
2017
- 2017-03-15 KR KR1020170032419A patent/KR20170033830A/ko active Search and Examination
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2018
- 2018-07-23 KR KR1020180085587A patent/KR101992569B1/ko active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130244437A1 (en) * | 2012-03-15 | 2013-09-19 | Globalfoundries Inc. | Methods of forming features on an integrated circuit product using a novel compound sidewall image transfer technique |
Also Published As
Publication number | Publication date |
---|---|
KR101992569B1 (ko) | 2019-06-24 |
US20160111297A1 (en) | 2016-04-21 |
KR20180089339A (ko) | 2018-08-08 |
CN106158600A (zh) | 2016-11-23 |
KR20160045527A (ko) | 2016-04-27 |
CN112542377A (zh) | 2021-03-23 |
TW201615535A (zh) | 2016-05-01 |
US9685332B2 (en) | 2017-06-20 |
KR20170033830A (ko) | 2017-03-27 |
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