TWI560750B - Systems and methods for generating backside substrate texture maps for determining adjustments for front side patterning - Google Patents

Systems and methods for generating backside substrate texture maps for determining adjustments for front side patterning

Info

Publication number
TWI560750B
TWI560750B TW104102481A TW104102481A TWI560750B TW I560750 B TWI560750 B TW I560750B TW 104102481 A TW104102481 A TW 104102481A TW 104102481 A TW104102481 A TW 104102481A TW I560750 B TWI560750 B TW I560750B
Authority
TW
Taiwan
Prior art keywords
systems
methods
front side
texture maps
backside substrate
Prior art date
Application number
TW104102481A
Other languages
English (en)
Other versions
TW201545203A (zh
Inventor
Anton J Devilliers
Todd A Mathews
Rodney Lee Robison
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW201545203A publication Critical patent/TW201545203A/zh
Application granted granted Critical
Publication of TWI560750B publication Critical patent/TWI560750B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)
  • A Measuring Device Byusing Mechanical Method (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
TW104102481A 2014-01-24 2015-01-26 Systems and methods for generating backside substrate texture maps for determining adjustments for front side patterning TWI560750B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201461931555P 2014-01-24 2014-01-24

Publications (2)

Publication Number Publication Date
TW201545203A TW201545203A (zh) 2015-12-01
TWI560750B true TWI560750B (en) 2016-12-01

Family

ID=53678723

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104102481A TWI560750B (en) 2014-01-24 2015-01-26 Systems and methods for generating backside substrate texture maps for determining adjustments for front side patterning

Country Status (6)

Country Link
US (1) US20150211836A1 (zh)
JP (1) JP6649552B2 (zh)
KR (1) KR20160111512A (zh)
CN (1) CN105934812A (zh)
TW (1) TWI560750B (zh)
WO (1) WO2015112884A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6267141B2 (ja) * 2014-06-04 2018-01-24 東京エレクトロン株式会社 液塗布方法、液塗布装置、及びコンピュータ読み取り可能な記録媒体
US10241418B2 (en) 2014-12-01 2019-03-26 Asml Netherlands B.V. Method and apparatus for obtaining diagnostic information relating to a lithographic manufacturing process, lithographic processing system including diagnostic apparatus
KR20170130674A (ko) * 2016-05-18 2017-11-29 삼성전자주식회사 공정 평가 방법 및 그를 포함하는 기판 제조 장치의 제어 방법
US10770327B2 (en) 2017-07-28 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for correcting non-ideal wafer topography
JP7012538B2 (ja) * 2018-01-11 2022-01-28 株式会社ディスコ ウエーハの評価方法
FI128841B (en) * 2018-03-22 2021-01-15 Univ Helsinki Sensor calibration
US11036147B2 (en) * 2019-03-20 2021-06-15 Kla Corporation System and method for converting backside surface roughness to frontside overlay

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040253748A1 (en) * 2001-08-13 2004-12-16 Neo Chee Peng Method and apparatus for detecting topographical features of microelectronic substrates
US20100203250A1 (en) * 2009-02-06 2010-08-12 Tokyo Electron Limited Developing device, developing method and storage medium

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JP4207976B2 (ja) * 2006-05-17 2009-01-14 住友電気工業株式会社 化合物半導体基板の表面処理方法、および化合物半導体結晶の製造方法
JPS54153290U (zh) * 1978-04-14 1979-10-24
CA1143869A (en) * 1980-10-01 1983-03-29 Northern Telecom Limited Surface relief measuring equipment
US4504144A (en) * 1982-07-06 1985-03-12 The Perkin-Elmer Corporation Simple electromechanical tilt and focus device
US4750141A (en) * 1985-11-26 1988-06-07 Ade Corporation Method and apparatus for separating fixture-induced error from measured object characteristics and for compensating the measured object characteristic with the error, and a bow/warp station implementing same
US4931962A (en) * 1988-05-13 1990-06-05 Ade Corporation Fixture and nonrepeatable error compensation system
US5446824A (en) * 1991-10-11 1995-08-29 Texas Instruments Lamp-heated chuck for uniform wafer processing
JP2000180157A (ja) * 1998-12-16 2000-06-30 Super Silicon Kenkyusho:Kk 平坦度測定センサ
SE514309C2 (sv) * 1999-05-28 2001-02-05 Ericsson Telefon Ab L M Förfarande för att bestämma ytstruktur
JP2002033268A (ja) * 2000-07-18 2002-01-31 Nikon Corp 表面形状測定方法及びこれを用いた露光方法とデバイスの製造方法
JP4380039B2 (ja) * 2000-08-22 2009-12-09 ソニー株式会社 半導体装置の製造方法および半導体製造装置
US6624078B1 (en) * 2001-07-13 2003-09-23 Lam Research Corporation Methods for analyzing the effectiveness of wafer backside cleaning
JP2003317285A (ja) * 2002-04-25 2003-11-07 Ricoh Co Ltd 光ディスク原盤露光装置および光ディスク原盤露光方法、並びに回転振れ検出方法
US7968354B1 (en) * 2002-10-04 2011-06-28 Kla-Tencor Technologies Corp. Methods for correlating backside and frontside defects detected on a specimen and classification of backside defects
US7760347B2 (en) * 2005-05-13 2010-07-20 Applied Materials, Inc. Design-based method for grouping systematic defects in lithography pattern writing system
US7348556B2 (en) * 2005-07-19 2008-03-25 Fei Company Method of measuring three-dimensional surface roughness of a structure
JP5009564B2 (ja) * 2006-07-20 2012-08-22 株式会社ミツトヨ 表面追従型測定器
WO2012008484A1 (ja) * 2010-07-14 2012-01-19 国立大学法人静岡大学 接触状態検出装置、接触状態検出方法、接触状態検出用コンピュータプログラム、接触状態検出装置を備える電気伝導度測定システムおよび接触状態検出方法を含む電気伝導度測定方法
US9354526B2 (en) * 2011-10-11 2016-05-31 Kla-Tencor Corporation Overlay and semiconductor process control using a wafer geometry metric

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040253748A1 (en) * 2001-08-13 2004-12-16 Neo Chee Peng Method and apparatus for detecting topographical features of microelectronic substrates
US20100203250A1 (en) * 2009-02-06 2010-08-12 Tokyo Electron Limited Developing device, developing method and storage medium

Also Published As

Publication number Publication date
JP6649552B2 (ja) 2020-02-19
US20150211836A1 (en) 2015-07-30
WO2015112884A1 (en) 2015-07-30
CN105934812A (zh) 2016-09-07
JP2017505438A (ja) 2017-02-16
KR20160111512A (ko) 2016-09-26
TW201545203A (zh) 2015-12-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees