TWI555246B - Resistive random access memory structure and method for operating resistive random access memory - Google Patents

Description

Resistive random access memory structure and operation method of resistive random access memory

The present invention relates to a memory and a method of operating the same, and more particularly to a resistive random access memory structure and a method of operating a resistive random access memory.

Since non-volatile memory has the advantage that the data will not disappear after power-off, many such electrical products must have such memory to maintain the normal operation of the electrical product when it is turned on. At present, a non-volatile memory component actively developed in the industry is a resistive random access memory (RRAM), which has a low write operation voltage, a short write erase time, a long memory time, and a non-volatile memory. Destructive reading, multi-state memory, simple structure and small required area make it one of the non-volatile memory components widely used in personal computers and electronic devices in the future.

At present, a high-density three-dimensional resistive random access memory (RRAM) is proposed in the industry. However, how to further reduce the operational complexity, power consumption and leakage of the three-dimensional resistive random access memory It is the goal that the industry is actively pursuing.

The present invention provides a resistive random access memory structure that can have better electrical performance.

The present invention provides a method of operating a resistive random access memory that can have better operational performance.

The invention provides a resistive random access memory structure comprising a first transistor, a second transistor and a resistive random access memory cell string. The first transistor is electrically connected to the second transistor through the first terminal of the first transistor, and the first transistor is connected in series with the second transistor. The resistive random access memory cell string includes a plurality of memory cells electrically connected to each other and electrically connected to the second terminal of the first transistor.

According to an embodiment of the invention, in the resistive random access memory structure, the first transistor and the second transistor are connected in series, for example, by sharing the first terminal.

According to an embodiment of the present invention, in the resistive random access memory structure, the first transistor includes a first gate, a first doped region, and a second doped region. The first gate is disposed on the substrate. The first doped region and the second doped region are respectively disposed in the substrate on one side and the other side of the first gate, and respectively serve as the first terminal and Second terminal. The second transistor includes a second gate, a third doped region, and a first doped region. The second gate is disposed on the substrate. The third doped region and the first doped region are respectively disposed in one side of the second gate and the substrate on the other side, wherein the third doped region serves as a third terminal.

According to an embodiment of the invention, in the resistive random access memory structure, the substrate includes a protrusion. The protrusion is located between the first gate and the second gate, and the first terminal is located in the protrusion.

According to an embodiment of the present invention, in the resistive random access memory structure, the first transistor and the second transistor are electrically connected to the first terminal and the second terminal of the first transistor, for example. The fourth terminal of the transistor is connected in series.

According to an embodiment of the present invention, in the resistive random access memory structure, the first transistor includes a first gate, a first doped region, and a second doped region. The first gate is disposed on the substrate. The first doped region and the second doped region are respectively disposed in one side of the first gate and the other side of the substrate, and serve as a first terminal and a second terminal, respectively. The second transistor includes a second gate, a third doped region, and a fourth doped region. The second gate is disposed on the substrate. The third doping region and the fourth doping region are respectively disposed in the substrate on one side and the other side of the second gate, and serve as a third terminal and a fourth terminal, respectively.

According to an embodiment of the present invention, in the resistive random access memory structure, the first doped region and the fourth doped region are electrically connected by, for example, an interconnect structure.

According to an embodiment of the present invention, in the resistive random access memory structure, each memory cell includes a first electrode, a second electrode, and a variable resistor. structure. The second electrode is disposed on the first electrode. The variable resistance structure is disposed between the first electrode and the second electrode.

According to an embodiment of the present invention, in the resistive random access memory structure, the resistive random access memory cell string further includes an interconnect structure, and the first electrode of the plurality of memory cells of the same string Make a connection.

According to an embodiment of the present invention, in the resistive random access memory structure, the first transistor and the second transistor are, for example, a gold oxide half field effect transistor and a double carrier junction transistor, respectively. (bipolar junction transistor), junction field effect transistor, metal-semiconductor field effect transistor or modulation doped field effect transistor.

The invention provides a method for operating a resistive random access memory, wherein the resistive random access memory comprises at least one resistive random access memory structure. The resistive random access memory structure includes a first transistor, a second transistor, a resistive random access memory cell string, a first word line, a second word line, a plurality of bit lines and a source line. The first transistor is electrically connected to the second transistor through the first terminal of the first transistor, and the first transistor is connected in series with the second transistor. The resistive random access memory cell string includes a plurality of memory cells electrically connected to each other and electrically connected to the second terminal of the first transistor. The first word line is electrically connected to the first gate of the first transistor. The second word line is electrically connected to the second gate of the second transistor. The bit lines are electrically connected to the corresponding memory cells, respectively. The source line is electrically connected to the third terminal of the second transistor, wherein the third terminal is located on a side of the second gate remote from the first gate. Above electricity The method of operating a resistive random access memory includes grounding the source line when one of a programmed memory cell, an erase operation, and a read operation is performed on the selected memory cell.

According to an embodiment of the present invention, in the method for operating a resistive random access memory, the following steps are further included in the program operation of the selected memory cell. A first turn-on voltage is applied to the first word line. A second turn-on voltage is applied to the second word line. A stylized voltage is applied to the bit line.

According to an embodiment of the invention, in the method for operating a resistive random access memory, the following steps are further included in performing an erase operation on the selected memory cell. A third turn-on voltage is applied to the first word line. A fourth turn-on voltage is applied to the second word line. Apply a erase voltage to the bit line.

According to an embodiment of the present invention, in the method for operating a resistive random access memory, the following steps are further included in performing a read operation on a selected memory cell. A fifth turn-on voltage is applied to the first word line. A sixth turn-on voltage is applied to the second word line. A read voltage is applied to the bit line.

According to an embodiment of the present invention, in the method of operating the resistive random access memory, the absolute value of the operating voltage of the stylized operation is, for example, greater than the absolute value of the erase voltage of the erase operation, and The absolute value of the divided voltage is, for example, greater than the absolute value of the read voltage of the read operation.

According to an embodiment of the present invention, when the number of resistive random access memory structures is multiple and the selected memory cells are operated, No voltage is applied to other first word lines, other second word lines, and other bit lines that are not connected to the selected memory cell.

According to an embodiment of the present invention, when the number of resistive random access memory structures is multiple and the selected memory cells are operated, Connect other source lines that are not connected to the selected memory cell to ground.

Based on the above, in the resistive random access memory structure and the method of operating the resistive random access memory proposed by the present invention, the resistive random access memory cell string is controlled by two transistors connected in series with each other. It can effectively reduce the operational complexity, power consumption and leakage, and effectively improve the electrical performance and operational efficiency of the resistive random access memory.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Resistive random access memory

20‧‧‧Resistive random access memory structure

100‧‧‧First transistor

102‧‧‧Second transistor

104‧‧‧First Gate

106‧‧‧First doped area

108‧‧‧Second doped area

110, 120‧‧‧ gate dielectric layer

112, 122‧‧ ‧ clearance wall

114, 124‧‧‧Doped extension

116‧‧‧second gate

118‧‧‧ Third doped area

126‧‧‧fourth doping zone

128, WLx1~WLx3‧‧‧ first word line

130, WLy1~WLy3‧‧‧second character line

132, BL1~BL4‧‧‧ bit line

134, SL1~SL3‧‧‧ source line

136, 138, 140, 204, 500‧‧‧ interconnection structure

200‧‧‧Resistive random access memory cell string

202, R1~R36‧‧‧ memory cells

206‧‧‧First electrode

208‧‧‧second electrode

210‧‧‧Variable Resistor Structure

300‧‧‧Isolation structure

400‧‧‧Base

402‧‧‧Protruding

X, Y‧‧ direction

1 is a perspective view of a resistive random access memory according to an embodiment of the present invention.

2 is an enlarged view of the structure of the transistor of FIG. 1.

Fig. 3 is a cross-sectional view showing the structure of the transistor taken along the line I-I' in Fig. 2.

4 and 5 are cross-sectional views showing the structure of a transistor of another embodiment of the present invention, respectively.

6 is a circuit diagram of the resistive random access memory of FIG. 1.

1 is a perspective view of a resistive random access memory according to an embodiment of the present invention. The cutouts in Fig. 1 should actually be filled by a dielectric layer. To clearly illustrate Fig. 1, the depiction of the dielectric layer is omitted. Further, with regard to the number of the memory cell in Fig. 1, in order to clearly illustrate Fig. 1, only the selected memory cell R33 is indicated. 2 is an enlarged view of the structure of the transistor of FIG. 1. A portion of the interconnect structure is illustrated in FIG. 2 to illustrate the connection relationship between the transistor and the interconnect structure. Fig. 3 is a cross-sectional view showing the structure of the transistor taken along the line I-I' in Fig. 2.

Referring to FIG. 1 to FIG. 3 simultaneously, the resistive random access memory 10 includes at least one resistive random access memory structure 20. In this embodiment, the nine resistive random access memory structures 20 are taken as an example. However, the number of resistive random access memory structures 20 that can be used by those skilled in the art according to product design requirements is known in the art. Make adjustments.

Each of the resistive random access memory structures 20 includes a first transistor 100, a second transistor 102, and a resistive random access memory cell string 200. The first transistor 100 is electrically connected to the second transistor 102 by the first terminal of the first transistor 100 (eg, the first doping region 106 of FIG. 2), such that the first transistor 100 is connected in series with the second transistor 102. The resistive random access memory cell string 200 includes a plurality of memory cells 202 electrically connected to each other and electrically connected to a second terminal of the first transistor 100 (eg, the second doping region 108 of FIG. 2). In addition, the active regions of two adjacent resistive random access memory structures 20 are isolated by, for example, isolation structure 300. The isolation structure 300 is, for example, a shallow trench isolation structure (STI).

The first transistor 100 and the second transistor 102 are, for example, a gold oxide half field effect transistor (MOSFET), a bipolar junction transistor, and a junction field effect transistor. , a metal-semiconductor field effect transistor or a modulation doped field effect transistor. The resistive random access memory cell string 200 is, for example, a vertically connected resistive random access memory cell string or a horizontally connected resistive random access memory cell string. However, the present invention is not particularly limited to the aspect of the resistive random access memory cell string 200. In this embodiment, the first transistor 100 and the second transistor 102 are exemplified by a gold oxide half field effect transistor, and the resistive random access memory cell string 200 is, for example, a vertical connection type resistive random. The access memory cell string is taken as an example for description, but the invention is not limited thereto.

In this embodiment, the first transistor 100 and the second transistor 102 are connected in series, for example, by sharing the first doping region 106 (first terminal).

The first transistor 100 includes a first gate 104, a first doped region 106, and a second doped region 108. The first gate 104 is disposed on the substrate 400. The first doping region 106 and the second doping region 108 are respectively disposed in one side of the first gate 104 and the substrate 400 on the other side, and serve as a first terminal and a second terminal, respectively. In addition, the first transistor 100 further selectively includes at least one of the gate dielectric layer 110, the spacers 112, and the doped extension regions 114. The gate dielectric layer 110 is disposed between the first gate 104 and the substrate 400. The spacer 112 is disposed on a sidewall of one side of the first gate 104. The doped extension region 114 is disposed in the substrate 400 below the spacer 112 and can be used as a lightly doped germanium Extreme (LDD) use. The materials and manufacturing methods of the respective members in the first transistor 100 are well known to those skilled in the art, and thus will not be described herein.

The second transistor 102 includes a second gate 116, a third doped region 118, and a first doped region 106. The second gate 116 is disposed on the substrate 400. The third doping region 118 and the first doping region 106 are respectively disposed in one side of the second gate 116 and the substrate 400 on the other side, wherein the third doping region 118 serves as a third terminal. Moreover, the second transistor 102 more selectively includes at least one of the gate dielectric layer 120, the spacers 122, and the doped extension regions 124. The gate dielectric layer 120 is disposed between the second gate 116 and the substrate 400. The spacer 122 is disposed on a sidewall of one side of the second gate 116. The doped extension region 124 is disposed in the substrate 400 below the spacers 122 and can be used as a lightly doped drain (LDD). The materials and manufacturing methods of the members in the second transistor 102 are well known to those skilled in the art, and thus will not be described herein.

Further, the substrate 400 includes a protrusion 402, and the protrusion 402 is located between the first gate 104 and the second gate 116, and the first doping region 106 (first terminal) is located in the protrusion 402. When the first transistor 100 and the second transistor 102 are as shown in FIG. 2 and FIG. 3, the wafer area occupied by the first transistor 100 and the second transistor 102 only needs to be slightly larger than a planar gold. The area of the oxygen half field effect transistor can be completed, so that the utilization of the wafer area can be effectively improved.

In addition, the type of the transistor structure used in the resistive random access memory structure 20 is not limited to the first transistor 100 and the second transistor 102 in the above embodiment, as long as the two transistors are connected in series. And it can be used to control the operation of the resistive random access memory cell string 200.

4 and 5 are cross-sectional views showing the structure of a transistor of another embodiment of the present invention, respectively. Hereinafter, a transistor structure of another embodiment of the present invention will be described with reference to FIGS. 4 and 5.

Referring to FIG. 4, the difference between the transistor structure of FIG. 4 and the transistor structure of FIG. 3 is as follows. In FIG. 4, the substrate 400a does not have the protrusion 402 of FIG. 3, and the spacer 112 and the doping extension 114 in the first transistor 100a are disposed on both sides of the first gate 104, and in the second transistor 102a. The spacers 122 and the doping extensions 124 are disposed on both sides of the second gate 116. In the embodiment of FIG. 4, the first transistor 100a and the second transistor 102a are connected in series, for example, by sharing the first doping region 106 (first terminal).

Referring to FIG. 5, the difference between the transistor structure of FIG. 5 and the transistor structure of FIG. 4 is as follows. In the embodiment of FIG. 5, the first transistor 100b and the second transistor 102b are electrically connected to the first doping region 106 (first terminal) of the first transistor 100b and the second transistor 102b, for example. It is connected in series with the fourth doping region 126 (fourth terminal). In FIG. 5, the first transistor 100b and the second transistor 102b do not share the first doping region 106 (first terminal). The first transistor 100b includes a first doping region 106 and a second doping region 108 disposed in a substrate 400a on one side and the other side of the first gate 104, wherein the first doping region 106 and the second doping region The miscellaneous regions 108 serve as a first terminal and a second terminal, respectively. The second transistor 102b includes a third doping region 118 and a fourth doping region 126 disposed in the substrate 400a on one side and the other side of the second gate 116, wherein the third doping region 118 and the fourth doping region The miscellaneous regions 126 serve as a third terminal and a fourth terminal, respectively. The third doping region 118 and the fourth doping region 126 are, for example, connected by an interconnect structure 500. Power connection. The material of the interconnect structure 500 is, for example, copper, aluminum, tungsten, or a combination thereof. Those skilled in the art can adjust the number of conductor layers that make up the interconnect structure 500 in accordance with product design requirements.

Referring to FIG. 1 to FIG. 3 , each of the resistive random access memory structures 20 further includes a first word line 128 , a second word line 130 , a plurality of bit lines 132 , and a source line 134 .

The first word line 128 is electrically connected to the first gate 104 of the first transistor 100. In this embodiment, the first word line 128 is electrically connected to the first gate 104 of the first transistor 100 located in the same column, for example, along the X direction. The material of the first word line 128 is, for example, a metal such as copper, aluminum or tungsten. The first word line 128 is electrically connected to the first gate 104, for example, by an interconnect structure 136. The material of the interconnect structure 136 is, for example, copper, aluminum, tungsten, or a combination thereof. Those skilled in the art can adjust the number of conductor layers that make up the interconnect structure 136 in accordance with product design requirements.

The second word line 130 is electrically connected to the second gate 116 of the second transistor 102. In this embodiment, the second word line 130 is electrically connected to the second gate 116 of the second transistor 102 on the same row, for example, along the Y direction. The material of the second word line 130 is, for example, a metal such as copper, aluminum or tungsten. The second word line 130 is electrically connected to the second gate 116 by, for example, an interconnect structure 138. The material of the interconnect structure 138 is, for example, copper, aluminum, tungsten, or a combination thereof. Those skilled in the art can adjust the number of conductor layers that make up the interconnect structure 138 in accordance with product design requirements.

The bit lines 132 are electrically connected to the corresponding memory cells 202, respectively. The material of the bit line 132 is, for example, a metal such as copper, aluminum or tungsten. In this embodiment, each bit line 132 is connected to, for example, nine memory cells 202.

The source line 134 is electrically connected to the third doping region 118 (third terminal) of the second transistor 102, wherein the third doping region 118 is located on a side of the second gate 116 away from the first gate 104. In this embodiment, the source lines 134 are electrically connected, for example, along the third direction of the third doping regions 118 of the second transistor 102 on the same row. The material of the source line 134 is, for example, a metal such as copper, aluminum or tungsten. The source line 134 is electrically connected to the third doping region 118, for example, by the interconnect structure 140. The material of the interconnect structure 140 is, for example, copper, aluminum, tungsten, or a combination thereof. Those skilled in the art can adjust the number of conductor layers that make up the interconnect structure 140 in accordance with product design requirements.

The resistive random access memory cell string 200 further includes an interconnect structure 204. The interconnect structure 204 electrically connects the first electrodes 206 of the plurality of memory cells 202 of the same string, and electrically connects the memory cells 202 to the second doped regions 108 (second terminals) of the first transistor 100. . The material of the interconnect structure 204 is, for example, copper, aluminum, tungsten, or a combination thereof. Those skilled in the art can adjust the number of conductor layers that make up the interconnect structure 204 in accordance with product design requirements.

Each memory cell 202 includes a first electrode 206, a second electrode 208, and a variable resistance structure 210. The first electrode 206 is, for example, part of the interconnect structure 204. The second electrode 208 is disposed on the first electrode 206. The second electrode 208 is, for example, a portion of the bit line 132. The variable resistance structure 210 is disposed on the first electrode 206 and the second electrode Between 208. The material of the variable resistance structure 210 is, for example, a metal oxide such as cerium oxide, magnesium oxide, nickel oxide, cerium oxide, titanium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide or cobalt oxide. In addition, the variable resistance structure 210 may further include an insulating layer (not shown), thereby making the variable resistance structure 210 have a diode effect, and can effectively block a sneak current, thereby preventing malfunction. produce.

Based on the above embodiments, the resistive random access memory structure 20 is a type in which two transistors drive N resistive memory cells (2T-NR), and thus are connected in series with each other. The first transistor 100 and the second transistor 102 control the resistive random access memory cell string 200, which can effectively reduce operational complexity, power consumption and leakage, thereby effectively improving electrical performance and operational efficiency. . In addition, when the resistive random access memory cell string 200 in the above embodiment is used in the resistive random access memory 10, the deep etching process and the deep process are not required in the manufacturing process of the resistive random access memory 10. The hole filling process is deep, so it can be directly integrated with advanced logic processes.

6 is a circuit diagram of the resistive random access memory of FIG. 1.

Referring to FIG. 6, a plurality of first word lines 128, a plurality of second word lines 130, a plurality of bit lines 132, and a plurality of source lines in the resistive random access memory 10 of FIG. 134 and the plurality of memory cells 202 are numbered as first word lines WLx1 to WLx3, second word lines WLy1 to WLy3, word lines BL1 to BL4, source lines SL1 to SL3, and memory cells R1 to R36, respectively.

In this embodiment, the selected memory cell R33 is described as an operation object. The method of operating the resistive random access memory 10 includes the selected memory When the cell R33 performs one of the program operation, the erase operation, and the read operation, the source line SL3 is grounded. At this time, the other source lines SL1 to SL2 not connected to the selected memory cell R33 can be grounded at the same time. Further, the absolute value of the operating voltage of the stylized operation is, for example, greater than the absolute value of the erase voltage of the erase operation, and the absolute value of the erase voltage is, for example, greater than the absolute value of the read voltage of the read operation.

In the stylization of the selected memory cell R33, the following steps are further included. A first turn-on voltage is applied to the first word line WLx3. A second turn-on voltage is applied to the second word line WLy3. A stylized voltage is applied to bit line BL1. The first turn-on voltage and the second turn-on voltage may be voltages that can turn on the first transistor 100 and the second transistor 102, respectively.

The following steps are further included in the erasing operation of the selected memory cell R33. A third turn-on voltage is applied to the first word line WLx3. A fourth turn-on voltage is applied to the second word line WLy3. An erase voltage is applied to the bit line BL1. The third turn-on voltage and the fourth turn-on voltage may be voltages that can turn on the first transistor 100 and the second transistor 102, respectively.

The following steps are further included in the reading operation of the selected memory cell R33. A fifth turn-on voltage is applied to the first word line WLx3. A sixth turn-on voltage is applied to the second word line WLy3. A read voltage is applied to the bit line BL1. The fifth turn-on voltage and the sixth turn-on voltage may be voltages that enable the first transistor 100 and the second transistor 102 to be turned on, respectively.

In addition, when operating on the selected memory cell, other first word lines WLx1~WLx2 and other second words not connected to the selected memory cell R33 may be omitted. The voltages of the WLy1~WLy2 and the other bit lines BL2~BL4 are applied, so that the required power consumption can be reduced, and the chance of leakage can be reduced, thereby reducing the leakage current.

According to the above embodiment, when the selected memory cell R33 is operated, only the first word line WLx3, the second word line WLy3, and the bit line BL1 need to be powered on, and the other operations are not required. The voltage is applied to one of the word lines WLx1 to WLx2 and the other second word lines WLy1 to WLy2 and the other bit lines BL2 to BL4, so that the operational complexity can be effectively reduced. In addition, by operating the selected memory cell R33 using the first transistor 100 and the second transistor 102 in series, the leakage current of the transistor can be effectively reduced.

The above embodiment is described by taking the memory cell R33 as an example. Those skilled in the art can refer to the operation mode of the above embodiment to other memory cells (for example, any of the memory cells R1 to R32, R34 to R36). ) to operate.

In summary, in the resistive random access memory structure and the method for operating the resistive random access memory of the above embodiment, the resistive random access memory cell string is controlled by two transistors connected in series with each other. , can effectively reduce the operational complexity, power consumption and leakage, and thus effectively improve the electrical performance and operational efficiency

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Resistive random access memory

20‧‧‧Resistive random access memory structure

100‧‧‧First transistor

102‧‧‧Second transistor

128, WLx1~WLx3‧‧‧ first word line

130, WLy1~WLy3‧‧‧second character line

132, BL1~BL4‧‧‧ bit line

134, SL1~SL3‧‧‧ source line

136, 138, 140, 204‧‧‧ interconnection structure

200‧‧‧Resistive random access memory cell string

202, R33‧‧‧ memory cells

206‧‧‧First electrode

208‧‧‧second electrode

210‧‧‧Variable Resistor Structure

300‧‧‧Isolation structure

400‧‧‧Base

402‧‧‧Protruding

X, Y‧‧ direction

Claims (17)

A resistive random access memory structure, comprising: a first transistor and a second transistor, wherein a first terminal of the first transistor is electrically connected to the second transistor, so that the first a transistor is connected in series with the second transistor; a resistive random access memory cell string comprising a plurality of memory cells electrically connected to each other and electrically connected to a second terminal of the first transistor, wherein the transistor The second terminal and the first terminal are respectively located at two sides of the first transistor; and a first word line and a second word line are electrically connected to the first transistor and the second transistor, respectively And the first word line and the second word line are perpendicular to each other. The resistive random access memory structure according to claim 1, wherein the first transistor and the second transistor are connected in series by sharing the first terminal. The resistive random access memory structure of claim 2, wherein the first transistor comprises: a first gate disposed on a substrate; and a first doped region and a second The doped regions are respectively disposed in the substrate on one side and the other side of the first gate, and are respectively used as the first terminal and the second terminal, and the second transistor includes: a second gate. Disposed on the substrate; A third doped region and the first doped region are respectively disposed in the substrate on one side and the other side of the second gate, wherein the third doped region serves as a third terminal. The resistive random access memory structure of claim 3, wherein the substrate comprises a protrusion, wherein the protrusion is located between the first gate and the second gate, and the first The terminal is located in the protrusion. The resistive random access memory structure of claim 1, wherein the first transistor and the second transistor are electrically connected to the first terminal and the second of the first transistor A fourth terminal of the transistor is connected in series. The resistive random access memory structure of claim 5, wherein the first transistor comprises: a first gate disposed on a substrate; and a first doped region and a second The doped regions are respectively disposed in the substrate on one side and the other side of the first gate, and are respectively used as the first terminal and the second terminal, and the second transistor includes: a second gate. Provided on the substrate; and a third doped region and a fourth doped region are respectively disposed in the substrate on one side and the other side of the second gate, and respectively serve as a third terminal and the The fourth terminal. The resistive random access memory structure of claim 6, wherein the first doped region and the fourth doped region are electrically connected by an interconnect structure. Resistive random access memory junction as described in claim 1 Each of the memory cells includes: a first electrode; a second electrode disposed on the first electrode; and a variable resistance structure disposed between the first electrode and the second electrode. The resistive random access memory structure of claim 8, wherein the resistive random access memory cell string further comprises an interconnect structure, the first of the same string of the memory cells The electrodes are connected. The resistive random access memory structure according to claim 1, wherein the first transistor and the second transistor respectively comprise a gold oxide half field effect transistor and a bipolar junction transistor (bipolar junction). A transistor, a junction field effect transistor, a metal-semiconductor field effect transistor, or a modulation doped field effect transistor. A method for operating a resistive random access memory, wherein the resistive random access memory comprises at least one resistive random access memory structure, the resistive random access memory structure comprising: a first transistor and a second transistor is electrically connected to the second transistor by a first terminal of the first transistor, and the first transistor is connected in series with the second transistor; a resistive random access memory The cell string includes a plurality of memory cells electrically connected to each other and electrically connected to a second terminal of the first transistor; a first word line electrically connected to a first of the first transistor Gate a second word line electrically connected to a second gate of the second transistor; a plurality of bit lines electrically connected to the corresponding memory cells; and a source line, electrical Connecting to a third terminal of the second transistor, wherein the third terminal is located on a side of the second gate remote from the first gate, and the method for operating the resistive random access memory comprises selecting The memory cell is grounded by a stylization operation, an erase operation, and a read operation. The method for operating a resistive random access memory according to claim 11, wherein the performing the programming operation on the selected memory cell further comprises: applying a first opening to the first word line a voltage; applying a second turn-on voltage to the second word line; and applying a stylized voltage to the bit line. The method for operating a resistive random access memory according to claim 11, wherein the performing the erasing operation on the selected memory cell further comprises: applying a third turn-on voltage to the first word line Applying a fourth turn-on voltage to the second word line; and applying a erase voltage to the bit line. The method for operating a resistive random access memory according to claim 11, wherein the performing the reading operation on the selected one of the memory cells further comprises: applying a fifth turn-on voltage to the first word line Applying a sixth turn-on voltage to the second word line; and applying a read voltage to the bit line. The method of operating a resistive random access memory according to claim 11, wherein an absolute value of an operating voltage of the stylizing operation is greater than an absolute value of an erasing voltage of the erasing operation, and the erasing The absolute value of the voltage is greater than the absolute value of a read voltage of the read operation. The method of operating a resistive random access memory according to claim 11, wherein when the number of the at least one resistive random access memory structure is plural, and when the selected one of the memory cells is operated No voltage is applied to other first word lines, other second word lines, and other bit lines that are not connected to the selected memory cell. The method of operating a resistive random access memory according to claim 11, wherein when the number of the at least one resistive random access memory structure is plural, and when the selected one of the memory cells is operated Connect other source lines that are not connected to the selected memory cell to ground.