TWI659502B - Non-volatile memory structure - Google Patents

Abstract

A non-volatile memory structure includes a substrate and a plurality of memory cells. The plurality of memory cells include at least a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The second memory cell and the third memory cell are located on one side of the first memory cell, and the fourth memory cell is located on the other side of the first memory cell. Each memory cell includes a first well region, a first doped region, and a second doped region disposed in the substrate separately from each other. The first memory cell and the second memory cell share a first well region. The first memory cell and the third memory cell share the first doped region. The first memory cell and the fourth memory cell share a second doped region.

Description

Non-volatile memory structure

The invention relates to a memory structure, and more particularly to a non-volatile memory structure.

Because non-volatile memory (non-volatile memory) can perform multiple operations of data storage, reading, and erasing, and has the ability to save stored data when the power supply is interrupted, the data access time is short And low power consumption, it has become a kind of memory widely used in personal computers and electronic devices.

However, under the situation of increasing the accumulation of non-volatile memory elements, how to effectively reduce the area of the memory cells and increase the density of the elements are the goals of the ongoing efforts of the industry.

The invention provides a non-volatile memory structure, which can effectively reduce the memory cell area and increase the element density.

The invention provides a non-volatile memory structure including a base and a plurality of memory cells. The plurality of memory cells include at least a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The second memory cell and the third memory cell are located on one side of the first memory cell, and the fourth memory cell is located on the other side of the first memory cell. Each memory cell includes a first well region, a first doped region, and a second doped region disposed in the substrate separately from each other. The first memory cell and the second memory cell share a first well region. The first memory cell and the third memory cell share the first doped region. The first memory cell and the fourth memory cell share a second doped region.

According to an embodiment of the present invention, in the non-volatile memory structure, each memory cell may further include a second well region, a floating gate, and a dielectric layer. A second well region is disposed in the substrate. The second well area and the first well area are separated from each other. The floating gate is disposed on the substrate and covers part of the first well area and part of the second well area. The first doped region and the second doped region may be located in a second well region on one side and the other side of the floating gate, respectively. A dielectric layer is disposed between the floating gate and the substrate.

According to an embodiment of the present invention, in the above non-volatile memory structure, the first well area shared by the first memory cell and the second memory cell may extend from below the floating gate of the first memory cell to Below the floating gate of the second memory cell.

According to an embodiment of the present invention, in the above non-volatile memory structure, the first well region and one side of the floating gate may intersect, and the first well region and the other side of the floating gate may not intersect.

According to an embodiment of the present invention, in the above non-volatile memory structure, the first well region, the first doped region, and the second doped region may have a first conductivity type, and the second well region may have Second conductivity type.

According to an embodiment of the present invention, in the non-volatile memory structure, each memory cell may further include a third doped region. The third doped region is disposed in the first well region on one side of the floating gate. The third doped region may have a first conductivity type. The first memory cell and the second memory cell may share a third doped region.

According to an embodiment of the present invention, in the above non-volatile memory structure, the floating gate of the first memory cell and the floating gate of the second memory cell may be located above different second well regions.

According to an embodiment of the present invention, in the non-volatile memory structure, the floating gate of the first memory cell, the floating gate of the third memory cell, and the floating gate of the fourth memory cell may be Located above the same second well area.

According to an embodiment of the present invention, in the non-volatile memory structure, the first memory cell and the second memory cell may be misaligned, and the first memory cell and the third memory cell may be misaligned.

According to an embodiment of the present invention, in the non-volatile memory structure, the first memory cell and the fourth memory cell may be mirror-symmetrical.

Based on the above, in the non-volatile memory structure proposed by the present invention, the first memory cell and the second memory cell share a first well region, the first memory cell and the third memory cell share a first doped region, and the first A memory cell shares a second doped region with the fourth memory cell. The layout design can effectively reduce the memory cell area and increase the device density.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a top view of a non-volatile memory structure according to an embodiment of the present invention. FIG. 2 is an enlarged view of a part shown in a frame in FIG. 1. Fig. 3 is a cross-sectional view taken along the line I-I 'and line II-II' in Fig. 2. In FIG. 3, the contact window in FIG. 2 is omitted for simpler description.

Please refer to FIGS. 1 to 3. The non-volatile memory structure 100 includes a substrate 102 and a plurality of memory cells. The non-volatile memory structure 100 can be applied to a multi-time programmable (MTP) memory element or a one-time programmable (OTP) memory element. The substrate 102 may be a semiconductor substrate, such as a silicon substrate.

The plurality of memory cells include at least memory cell MC1, memory cell MC2, memory cell MC3, and memory cell MC4. In this embodiment, the memory cell MC1, the memory cell MC2, the memory cell MC3, and the memory cell MC4 are taken as examples to illustrate the layout design of the non-volatile memory structure 100. Memory cell MC2 and memory cell MC3 are located on one side of memory cell MC1, and memory cell MC4 is located on the other side of memory cell MC1. The memory cells MC1 and MC2 can be misaligned, and the memory cells MC1 and MC3 can be misaligned, thereby helping to reduce the memory cell area and increase the element density. Memory cell MC1 and memory cell MC4 can be mirror-symmetric.

Taking the memory cell MC1 as an example, each memory cell includes a well region 104, a doped region 106, and a doped region 108 that are separately disposed in the substrate 102. The well area 104 can serve as a control gate. The doped region 106 and the doped region 108 may serve as one and the other of a source and a drain, respectively. Memory cell MC1 and memory cell MC2 share well region 104, memory cell MC1 and memory cell MC3 share doped region 106, and memory cell MC1 and memory cell MC4 share doped region 108. This layout design can effectively reduce the memory cell Area and increase element density.

In addition, the well region 104, the doped region 106, and the doped region 108 may have a first conductivity type. Hereinafter, the first conductive type and the second conductive type may be one of an N-type conductive type and a P-type conductive type, respectively. In this embodiment, the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, but the present invention is not limited thereto. In another embodiment, the first conductivity type may be a P-type conductivity type, and the second conductivity type may be a P-type conductivity type. The formation method of the well region 104, the doped region 106, and the doped region 108 is, for example, an ion implantation method.

In addition, taking the memory cell MC1 as an example, each memory cell may further include at least one of a well region 110, a floating gate 112, a dielectric layer 114, and a doped region 116. The well region 110 is disposed in the substrate 102. The well area 110 and the well area 104 are separated from each other. The well region 110 may have a second conductivity type (eg, P-type). A method of forming the well region 110 is, for example, an ion implantation method.

The floating gate electrode 112 is disposed on the substrate 102. The floating gate 112 can be used to store charge. The floating gate electrode 112 covers part of the well area 104 and part of the well area 110, thereby reducing process damage to the well area 104 and the well area 110. The material of the floating gate 112 may be polycrystalline silicon, such as doped polycrystalline silicon or undoped polycrystalline silicon. The doped region 106 and the doped region 108 may be located in the well region 110 on one side and the other side of the floating gate 112, respectively. The method for forming the floating gate electrode 112 is, for example, a combination of a deposition process, a lithography process, and an etching process.

In addition, the well 104 shared by the memory cell MC1 and the memory cell MC2 may extend from below the floating gate 112 of the memory cell MC1 to below the floating gate 112 of the memory cell MC2. The well area 104 and one side of the floating gate 112 may intersect, and the well area 104 and the other side of the floating gate 112 may not intersect. Because the corner 118 at the intersection of the well area 104 and the floating gate 112 is prone to generate a leakage path, the well can be reduced if the well area 104 does not intersect with the other side of the floating gate 112 The number of corners 118 where the region 104 intersects the floating gate 112. That is, the leakage path can be reduced to reduce the leakage situation. Taking FIG. 2 as an example, there are only two corners 118 at the intersection of each well area 104 and each floating gate electrode 112, but the present invention is not limited thereto.

In addition, the floating gate 112 of the memory cell MC1 and the floating gate 112 of the memory cell MC2 may be located above different well regions 110. The floating gate 112 of the memory cell MC1, the floating gate 112 of the memory cell MC3, and the floating gate 112 of the memory cell MC4 may be located above the same well area 110.

A dielectric layer 114 is disposed between the floating gate 112 and the substrate 102. The material of the dielectric layer 114 is, for example, silicon oxide. A method of forming the dielectric layer 114 is, for example, a thermal oxidation method.

The doped region 116 is disposed in the well region 104 on one side of the floating gate 112. The doped region 116 may have a first conductivity type (eg, N-type). The memory cell MC1 and the memory cell MC2 may share the doped region 116. A method of forming the doped region 116 is, for example, an ion implantation method.

In addition, the non-volatile memory structure 100 may further include at least one of an isolation structure 120, a contact window 122, a contact window 124, and a contact window 126. The isolation structure 120 may be disposed between adjacent well regions 104, between adjacent well regions 110, and between adjacent well regions 104 and 110. The material of the isolation structure 120 is, for example, silicon oxide. The isolation structure 120 is, for example, a shallow trench isolation structure.

The contact window 122 may be electrically connected to the well area 104. In this embodiment, the contact window 122 is electrically connected to the well region 104 via the doped region 116, but the invention is not limited thereto. The contact window 124 and the contact window 126 may be electrically connected to the doped region 106 and the doped region 108 respectively. Materials of the contact window 122, the contact window 124, and the contact window 126 are, for example, metals such as tungsten, copper, or aluminum.

In each memory cell, taking the memory cell MC1 as an example, a capacitor C of a first conductivity type (eg, N type) can be formed by the floating gate 112, the dielectric layer 114, and the well region 104, and the floating gate can be formed by the floating gate 112. The dielectric layer 114, the doped region 106, and the doped region 108 form a transistor T of a first conductivity type (eg, N type). The floating gate 112 is connected between the capacitor C and the transistor T. The well region 104 in the capacitor C can be used as a control gate to control the on / off of the transistor T.

In addition, the non-volatile memory structure 100 may further have other interconnection structures electrically connected to the contact window 122, the contact window 124 and the contact window 126. For example, the non-volatile memory structure 100 may further include interconnect structures such as word lines, bit lines, and source lines. Those with ordinary knowledge in the technical field may determine the word lines and bit lines according to the layout design. The arrangement of lines and source lines is omitted here.

In addition, the memory cells in the non-volatile memory structure 100 can be programmed using hot carrier injection or FN tunneling, and can also use band-to-band tunneling. (Band-to-band tunneling, BTBT) or FN tunneling effect.

Based on the above examples, it is known that in the non-volatile memory structure 100, the memory cell MC1 and the memory cell MC2 share the well region 104, the memory cell MC1 and the memory cell MC3 share the doped region 106, and the memory cell MC1 and the memory cell MC4 share The doped region 108 can effectively reduce the memory cell area and increase the device density by the layout design.

In the above embodiment, although the layout of the non-volatile memory structure 100 is described by taking the layout design of the memory cell MC1 and its adjacent memory cell as an example, the above layout design can also be applied to the non-volatile memory structure 100. Other memory cells in the memory structure 100.

In summary, in the non-volatile memory structure of the above embodiment, the layout design between a single memory cell and its adjacent memory cells can effectively reduce the memory cell area and increase the element density.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧Non-volatile memory structure

102‧‧‧ substrate

104, 110‧‧‧well area

106, 108, 116‧‧‧ doped regions

112‧‧‧Floating Gate

114‧‧‧ Dielectric layer

118‧‧‧ Corner

120‧‧‧Isolation structure

122, 124, 126‧‧‧ contact windows

C‧‧‧Capacitor

MC1 ~ MC4‧‧‧Memory cells

T‧‧‧Transistor

FIG. 1 is a top view of a non-volatile memory structure according to an embodiment of the present invention. FIG. 2 is an enlarged view of a part shown in a frame in FIG. 1. Fig. 3 is a cross-sectional view taken along the line I-I 'and line II-II' in Fig. 2.

Claims (10)

A non-volatile memory structure includes: a substrate; and a plurality of memory cells, including at least a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, wherein the second memory cell and the memory cell A third memory cell is located on one side of the first memory cell, the fourth memory cell is located on the other side of the first memory cell, and each memory cell includes a first well disposed in the base separately from each other. Region, first doped region and second doped region, the first memory cell and the second memory cell share the first well region, and the first memory cell and the third memory cell share the same The first doped region, and the first memory cell and the fourth memory cell share the second doped region. The non-volatile memory structure according to item 1 of the scope of the patent application, wherein each memory cell further comprises: a second well region disposed in the substrate, wherein the second well region and the first well Regions are separated from each other; a floating gate is disposed on the substrate and covers part of the first well region and part of the second well region, wherein the first doped region and the second doped region The second well region is located on one side and the other side of the floating gate, respectively; and a dielectric layer is provided between the floating gate and the substrate. The non-volatile memory structure according to item 2 of the scope of patent application, wherein the first well area shared by the first memory cell and the second memory cell is obtained from the first memory cell. The floating gate extends below the floating gate of the second memory cell. The non-volatile memory structure according to item 3 of the scope of patent application, wherein the first well region intersects one side of the floating gate, and the first well region and the floating gate Disjoint on the other side. The non-volatile memory structure according to item 2 of the patent application scope, wherein the first well region, the first doped region, and the second doped region have a first conductivity type, and the first The second well area has a second conductivity type. The non-volatile memory structure according to item 5 of the scope of patent application, wherein each memory cell further includes a third doped region, and the third doped region is disposed on a side of the floating gate. The first well region has the first conductivity type, and the first memory cell and the second memory cell share the third doped region. The non-volatile memory structure according to item 2 of the scope of patent application, wherein the floating gate of the first memory cell and the floating gate of the second memory cell are in different locations. Said above the second well area. The non-volatile memory structure according to item 2 of the patent application scope, wherein the floating gate of the first memory cell, the floating gate of the third memory cell, and the fourth The floating gate of the memory cell is located above the same second well region. The non-volatile memory structure according to item 1 of the scope of patent application, wherein the first memory cell and the second memory cell are arranged in a misalignment, and the first memory cell and the third memory cell are Misaligned. The non-volatile memory structure according to item 1 of the patent application scope, wherein the first memory cell and the fourth memory cell are mirror-symmetrical.