CN101488502A - Non-volatile semiconductor memory device - Google Patents
Non-volatile semiconductor memory device Download PDFInfo
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- CN101488502A CN101488502A CNA2009100036943A CN200910003694A CN101488502A CN 101488502 A CN101488502 A CN 101488502A CN A2009100036943 A CNA2009100036943 A CN A2009100036943A CN 200910003694 A CN200910003694 A CN 200910003694A CN 101488502 A CN101488502 A CN 101488502A
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Abstract
A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.
Description
Technical field
The present invention relates to a kind of Nonvolatile semiconductor memory device with memory cell of anti-fuse-type.
Background technology
LSI (Large Scale Integration: the storage of the security code large scale integrated circuit) towards digital household appliances, mobile phone, (Liquid Crystal Display: LCD) tone in the driver is adjusted parameter, temperature compensating type crystal oscillator (TCXO:temperature compensated crystal oscillator: in the fine setting of the temperature parameter of control crystal oscillator) etc. etc., more and more need the non-volatile ROM of low capacity to LCD.Under a lot of situations of non-volatile ROM by SIP (System in Package: system in package) carry EEPROM (Electronically Erasable and Programmable Read Only Memory: other chips electric erasable programmable memory device).Following technology is disclosed recently: standard CMOS (the Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductors (CMOS)) handle, can form non-volatile ROM that appends operation by nothing.For example, patent documentation 1,2, non-patent literature 1 grade discloses anti-fuse-type memory.
In anti-fuse-type memory, for example as shown in Figure 8, have the transistor 108 of selection, it forms the source (zone) 103 of N+ type in the passage both sides of P type semiconductor substrate 101, and forms gate electrode 106 by thick gate insulating film 104 on passage.With select in transistor 108 adjacent areas, has anti-fuse 109, on the semiconductor substrate 101 between its element separated region 102 that on fuse lower electrode diffusion layer 127 that is connected with a side in the source 103 and semiconductor substrate 101, forms, thin gate insulating film 105 by thinner than thick gate insulating film 104 forms the fuse upper electrode 107 that is made of poly-silicon.Select the opposing party's of transistor 108 the contactor 110 of source 103 by imbedding in the following hole that forms on the interlayer dielectric 111, BL is electrically connected with bit line.Gate electrode 106 is electrically connected with word line WR.Fuse upper electrode 107 is electrically connected with printed line WP.
The write activity of this anti-fuse storage unit is undertaken by the thin gate insulating film 105 that destroys anti-fuse 109.At this moment, apply high positive potential when destroying thin gate insulating film 105 to fuse lower electrode diffusion layer 127 as the N+ of the lower electrode of non-fuse 109, when the heat carriers such as passage between snowslide, light belt are injected into thin gate insulating film 105, cause insulation breakdown, so time to rupture instability, easily produce fluctuation, reliability is not good.Therefore in write activity, set and apply current potential, when making it can suppress thin gate insulating film 105 and destroy near the generation of the heat carrier the source 103.
For example, in write activity, select as shown in Figure 9/during non-select storage unit, in select storage unit 113, making and selecting the current potential Vwp1 of printed line WP1 is high just destruction current potential VPP, making and selecting the current potential Vwr1 of word line WR1 is VPP/2, and making and selecting the current potential Vb11 of bit line BL1 is 0v, destroys thin gate insulating film 105 thereby do not apply current potential ground to fuse lower electrode diffusion layer 127.In non-select storage unit 114, the current potential Vb12 that makes non-selection bit line BL2 is VPP/2, and the grid that does not produce anti-fuse applies the inhibition current potential with destroying.
In reading action, the electric current that flows in the anti-fuse of select storage unit 113 is identical with the write activity direction, this point is very important on reliability, but select transistor to flow into bit line from the upper electrode of anti-fuse by lower electrode in order to make electronics, making and selecting the current potential Vwp1 of printed line WP1 is the power supply potential VddIO of IO portion, the current potential Vwr1 that selects transistorized selection word line WR1 is power supply potential Vdd, selecting the current potential Vb11 of bit line BL1 is 0V, the current potential Vb12 of non-selection bit line BL2 is and selects the identical Vdd of word line WR1, thereby carries out reading of select storage unit 113.
Patent documentation 1: No. 6798693 specification of United States Patent (USP)
Patent documentation 2: TOHKEMY 2001-308283 communique
Non-patent literature 1:Bernard Aroson (Kilopass), " A Novel embeddedOTP NVM Using Standard Foundry CMOS Logic Technology ", IEDM206 (international electronic equipment meeting: International Electron Devices Meeting), the U.S., U.S. electric/electronic communication association (IEEE), 2006 the 24th page
But, in conventional example (with reference to Fig. 8～10), in write activity, need VPP, VPP/W, three kinds of current potentials of 0v, in reading action, need three kinds of VddIO, Vdd, 0v, amounting in the unit action needs five kinds of current potentials, exist peripheral control circuit to become complicated, the problem that circuit scale is excessive.
Summary of the invention major subjects of the present invention provides a kind of Nonvolatile semiconductor memory device, its have action potential kind (number of level) less, can reduce the memory cell of the circuit scale of peripheral circuit.
In the 1st viewpoint of the present invention, a kind of Nonvolatile semiconductor memory device is provided, memory cell with anti-fuse-type, it is characterized in that, have: select transistor, its passage both sides at semiconductor substrate have formation source/drain (zone), and on above-mentioned passage, have gate electrode by the 1st gate insulating film; The element separated region is formed on the above-mentioned semiconductor substrate with above-mentioned selection transistor adjacent areas; Anti-fuse, has the lower electrode that on above-mentioned semiconductor substrate, forms, and adjacent, and on the above-mentioned semiconductor substrate in the zone between said elements separated region and the above-mentioned lower electrode, has upper electrode by the 2nd gate insulating film with the said elements separated region; And the connection contactor, be electrically connected between the side and above-mentioned upper electrode in the above-mentioned regions and source, and contact with a side and above-mentioned upper electrode in the above-mentioned regions and source.
In the 2nd viewpoint of the present invention, a kind of Nonvolatile semiconductor memory device is provided, have the memory cell of anti-fuse-type, it is characterized in that having: anti-fuse; Select transistor, be electrically connected with an end of above-mentioned anti-fuse; And controller, it carries out following control: when carrying out write activity, apply the current potential that can destroy above-mentioned anti-fuse from the above-mentioned end of the above-mentioned anti-fuse of above-mentioned selection transistor one side direction.
In the 3rd viewpoint of the present invention, a kind of Nonvolatile semiconductor memory device is provided, memory cell with anti-fuse-type, it is characterized in that, have: a plurality of memory cell, select the upper electrode of side in the transistorized regions and source and anti-fuse to connect, and become ranks ground to dispose by being connected contactor; A plurality of word lines are electrically connected with the transistorized gate electrode of each above-mentioned selection of line direction; A plurality of bit lines are electrically connected with the opposing party of the transistorized regions and source of each above-mentioned selection of column direction; And source electrode line, between adjacent unit, be electrically connected at least with the lower electrode of above-mentioned anti-fuse.
According to the present invention, during write activity, need not to apply the current potential that suppresses destruction to non-selected bit line, word line, do not need to suppress current potential in the memory cell action control, the action potential kind is few, and action is simple, so the circuit scale of peripheral circuit can diminish.
Description of drawings
Fig. 1 is the partial cross section schematic diagram of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.
Fig. 2 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.
Fig. 3 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.
Fig. 4 is the partial cross section schematic diagram of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 2.
Fig. 5 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 2.
Fig. 6 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 2.
Fig. 7 is the schematic diagram that the circuit of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 3 constitutes.
Fig. 8 is the partial cross section schematic diagram for the formation that the memory cell in the Nonvolatile semiconductor memory device that conventional example relates to is described.
Fig. 9 is the schematic circuit diagram for the formation that the Nonvolatile semiconductor memory device that conventional example relates to is described.
Figure 10 is the table that an example of fashionable and the current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression conventional example.
Figure 11 is the schematic cross-section between the X-X ' formation, Figure 12 of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 4.
Figure 12 is the part schematic plan view of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 4.
Figure 13 is the part schematic section of the formation of the memory cell in the Nonvolatile memory devices that relates to of expression embodiments of the invention 5.
Figure 14 is the schematic circuit diagram of the formation of the Nonvolatile memory devices that relates to of expression embodiments of the invention 5.
Figure 15 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 5.
Figure 16 is the part schematic section of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.
Figure 17 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.
Figure 18 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.
Figure 19 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 7.
Figure 20 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 7.
Figure 21 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 8.
Figure 22 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 8.
Figure 23 is the part schematic section of variation (variation 1) of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.
Figure 24 is the schematic of the relation of the horizontal range of conducting place after the writing in the anti-fuse of expression memory cell and the magnitude of current.
Figure 25 is the part schematic section of variation (variation 2) of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 4.
Figure 26 is the part schematic section of variation (variation 3) of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 5.
Figure 27 is the part schematic section of variation (variation 4) of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.
Embodiment
In the Nonvolatile semiconductor memory device that the present invention relates to, have: select transistor (Fig. 1 8), its passage both sides at semiconductor substrate (Fig. 1 1) have source electrode and drain electrode (side and the opposing party of regions and source) (Fig. 1 3), and on above-mentioned passage, has gate electrode (Fig. 1 6) by the 1st gate insulating film (Fig. 1 4); Element separated region (Fig. 1 2), be formed on the above-mentioned semiconductor substrate of above-mentioned selection transistor (Fig. 1 8) adjacent areas (Fig. 1 1) on; Anti-fuse (Fig. 1 9), adjacent with said elements separated region (Fig. 1 2), and go up at above-mentioned semiconductor substrate (Fig. 1 1) and to form lower electrode (Fig. 1 27), on the above-mentioned semiconductor substrate in the zone between said elements separated region (Fig. 1 2) and the above-mentioned lower electrode (Fig. 1 27) (Fig. 1 1), has upper electrode (Fig. 1 7) by the 2nd gate insulating film (Fig. 1 5); Connect contactor (Fig. 1 28), be electrically connected between above-mentioned source electrode (side in the regions and source) (Fig. 1 3) and the above-mentioned upper electrode (Fig. 1 7), and contact with above-mentioned source electrode (Fig. 1 3) and above-mentioned upper electrode (Fig. 1 7).
(embodiment 1)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 1.Fig. 1 is the partial cross section schematic diagram of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.
In the memory cell of the Nonvolatile semiconductor memory device that embodiment 1 relates to, have the transistor 8 of selection and anti-fuse 9.
In selecting transistor 8, form the source (regions and source) 3 of N+ type in the passage both sides of P type semiconductor substrate 1, on passage, form gate electrode 6 by thick gate insulating film 4.The connection contactor 28 of one side's source 3 by imbedding in the following hole that forms on the interlayer dielectric 11 is electrically connected with the fuse upper electrode 7 of anti-fuse 9.The contactor 10 of the opposing party's source 3 by imbedding in the following hole that forms on the interlayer dielectric 11, BL is electrically connected with bit line.Gate electrode 6 is electrically connected with word line WR.
Anti-fuse 9 is: thin gate insulating film 5 carried out insulation breakdown, makes short circuit between semiconductor substrate 1 and the fuse upper electrode 7, and the storage that can write joint.Anti-fuse 9 is formed on lower area: with the semiconductor substrate 1 of a side's who selects transistor 8 source 3 adjacent areas on STI (the Shallow Trench Isolation: shallow-trench isolation) on 2 adjacent areas of type element separated region that forms.In anti-fuse 9, it is the MOS transistor structure, on the semiconductor substrate 1 in N+ type fuse lower electrode diffusion layer 27 that forms on the semiconductor substrate 1 and the zone between the element separated region 2, thin gate insulating film 5 by thinner than thick gate insulating film 4 forms the fuse upper electrode 7 that is made of poly-silicon.The connection contactor 28 of fuse upper electrode 7 (end of anti-fuse) by imbedding in the following hole that forms on the interlayer dielectric 11 is electrically connected with a side's who selects transistor 8 source 3.Fuse lower electrode diffusion layer 27 (other end of anti-fuse) is electrically connected with universal source polar curve SOURCE.In addition, the thin gate insulating film 5 under the fuse upper electrode 7 can be identical thickness with thick gate insulating film 4 on element separated region 2.
Connect contactor 28 and be the electric conductor of imbedding in the following hole that forms on the interlayer dielectric 11 of film forming on selecting transistor 8 and anti-fuse 9 (peristome that comprises the part of the part of source 3 and fuse upper electrode 7) (for example tungsten).Connection contactor 28 disposes till the part on the surface of fuse upper electrode 7 continuously since the part on the surface of a side source 3, with the source 3 that strides across a side who selects transistor 8 and the fuse upper electrode 7 of anti-fuse 9, and contact respectively with a side source 3 and fuse upper electrode 7.
In addition, the fuse lower electrode diffusion layer 27 of anti-fuse 9 is the member of diffusion of impurities to the P type semiconductor substrate 1 of N+ type at this, but the also member after the P+ type diffusion of impurities on the P type semiconductor substrate 1.Fuse lower electrode diffusion layer 27 is if the member of the P+ type diffusion of impurities on P type semiconductor substrate 1 then has the advantage of the resistance that can reduce anti-fuse part.And the transistor 8 of hypothesis selection here is that the memory cell of N channel-style describes, but the P channel-style also is the same.
Anti-fuse 9 preferably makes upper electrode 7 separate (horizontal (horizontal direction) at figure goes up separation) (with reference to Figure 23) with lower electrode 27.That is, lower electrode 27 relative upper electrodes 7, preferred levels position relation does not repeat.This structure is easy to realize by the following method: in the CMOS of standard manufacturing process, (lightly doped drain: the light dope seepage) injection or flexible the injection are carried out the mask inhibition, thereby make upper electrode 7 and lower electrode 27 only separate the wide X of sidewall 16 to LDD.By this structure, can suppress the fluctuation of read current.To junction (the ジ ヤ Application Network シ ヨ Application) position of the electrode 27 of substrate surface and the horizontal range that writes conducting place that the back forms (the time near the conducting of lower electrode 27 places, equal the distance X of Figure 23), and upper electrode after writing 7 and lower electrode 27 between the relation of current amount flowing (Icell) investigate, then as shown in figure 24.When distance X was too small, Icell extremely increased as can be known.Therefore in order to realize steady I cell, the value of preferred distance X is more than the 10nm.On the other hand, when distance X is excessive, can become the displacement transistor, so the problem that exists Icell obviously to reduce.Therefore the value of distance X is preferably formed and is 10nm～50nm.
Memory cell shown in Figure 1 (group) as shown in Figure 2, its formation is to select transistor and anti-fuse to be connected in series.Memory cell is arranged as ranks, the gate electrode of each memory cell of line direction is connected with word line WR1, WR2, the opposing party's of each memory cell of column direction source is connected with bit line BL1, BL2, and the other end of the fuse of each memory cell is electrically connected with universal source polar curve SOURCE.
In addition, the Nonvolatile semiconductor memory device that relates to of embodiment 1 can be by the standard CMOS process manufacturing.For example, on semiconductor substrate 1, form element separated region 2, afterwards by making semiconductor substrate 1 surface heat oxidation form heat oxide film, afterwards the heat oxide film in the zone that forms thick gate insulating film 4 being carried out etching removes, afterwards by thermal oxidation is carried out on semiconductor substrate 1 surface, form thick and thin heat oxide film, make poly-silicon film forming afterwards, and by etching formation gate electrode 6 and thick gate insulating film 4, with fuse upper electrode 7 and thin gate insulating film 5, form source 3 and fuse lower electrode diffusion layer 27 by importing impurity afterwards, make interlayer dielectric 11 film forming afterwards, the following hole that is formed for forming contactor 10 afterwards and connects contactor 28, by imbedding contactor 10 and connect contactor 28 in the hole down, make memory cell shown in Figure 1 afterwards.
Follow the action of the Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 1.Fig. 2 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.Fig. 3 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 1.
In write activity, make semiconductor substrate (Fig. 1 1) and the universal source polar curve SOURCE that is connected with fuse lower electrode diffusion layer (Fig. 1 27) is an earthing potential, to selecting bit line BL1, reaching selection word line WR1 and apply and write current potential VPP (positive high potential).So, only apply the destruction current potential, destroy the thin gate insulating film (Fig. 1 5) of anti-fuse (Fig. 1 9) to the fuse upper electrode of the anti-fuse of select storage unit 13 (Fig. 1 9) (Fig. 1 7).That is, apply the current potential that can destroy anti-fuse from an end of selecting the anti-fuse of transistor one side direction.
In reading action, make semiconductor substrate (Fig. 1 1) and the universal source polar curve SOURCE that is connected with fuse lower electrode diffusion layer (Fig. 1 27) is an earthing potential, to selecting word line WR1, reaching selection bit line BL1 and apply IO current potential VddIO.So, with regard to conducting,, can read the data that have been written to memory cell when as long as the thin gate insulating film of (Fig. 1 9) anti-fuse (Fig. 1 5) is destroyed as not destroyed just non-conduction.
And the control of Electric potentials of each wiring is undertaken by not shown controller.In the write activity here, make semiconductor substrate (Fig. 1 1) and fuse lower electrode diffusion layer (Fig. 1 27) be earthing potential, making the drain electrode of selecting transistor (Fig. 1 8) (Fig. 1 3) and gate electrode (Fig. 1 6) is positive high potential, but also can make semiconductor substrate (Fig. 1 1) and fuse lower electrode diffusion layer (Fig. 1 27) be positive high potential, making the drain electrode of selecting transistor (Fig. 1 8) (Fig. 1 3) and gate electrode (Fig. 1 6) is earthing potential.
According to embodiment 1, the action of memory cell control does not need to suppress current potential, and the action potential kind is few, and action is simple, so the circuit scale of peripheral circuit is little, can obtain that micro-dimension is little, the low-cost device of little chip size.And, the thin gate insulating film 5 of anti-fuse 9 is carried out insulation breakdown and write fashionablely, have following effect: insulation breakdown carries out conscientiously, does not have resistance variations after the destruction, can obtain the Nonvolatile semiconductor memory device of good reliability.Promptly, be applied to fuse upper electrode 7 by the current potential that writes of selecting transistor 8 to be sent to anti-fuse 9, therefore the destruction of thin gate insulating film 5 of the anti-fusing point 9 of select storage unit 13 can be produced by the FN channel current, the grid destruction that causes because of heat carrier that snowslide uniform that near fuse lower electrode diffusion layer 27 1 sides the poly-silicon end produce, passage between light belt produce can be suppressed.Further, in standard CMOS process, do not append technology, can reduce manufacturing this locality and form.
(embodiment 2)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 2.Fig. 4 is the partial cross section schematic diagram of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 2.
In the Nonvolatile semiconductor memory device that embodiment 2 relates to, in the interlayer dielectric 11 on a side source 3 and the connection contactor 28a that is connected with fuse upper electrode 7, be formed with from lower floor's one side and begin the electric capacity 31 that lamination capacitor lower electrode 32, capacitor insulating film 33, electric capacity upper electrode 34 successively form.Capacitor lower electrode 32 is by connecting contactor 28b and being connected contactor 28a electrical connection.Electric capacity upper electrode 34 is electrically connected with electric capacity printed line CAP by connecting contactor 28c.Other basic comprisings (selecting transistor 8, anti-fuse 9) are identical with embodiment 1.And memory cell shown in Figure 4 is a formation of selecting transistor and anti-fuse to be connected in series as shown in Figure 5.Memory cell is arranged as ranks, the gate electrode of each memory cell of line direction is connected with word line WR1, WR2, the opposing party's of each memory cell of column direction source is connected with bit line BL1, BL2, one end of the fuse of each memory cell is connected with universal source polar curve SOURCE, and the electric capacity upper electrode of each memory cell is connected with general electric capacity printed line CAP.
Follow the action of the non-volatile semiconductor storage that relates to reference to description of drawings embodiments of the invention 2.Fig. 5 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 2.Fig. 6 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 2.
In write activity, the universal source polar curve SOURCE that makes semiconductor substrate (Fig. 4 1) and be connected with fuse lower electrode diffusion layer (Fig. 4 27) is an earthing potential, to selecting bit line BL1 to apply VPP/2, to selecting word line WR1 to apply VPP, after the joint charging to fuse upper electrode (Fig. 4 7), reduce the current potential of selecting word line WR1 and selecting bit line BL1, to applying the current potential that writes of VPP/2 with electric capacity upper electrode (Fig. 4 34) the electric capacity printed line CAP that is connected, the potential rise of the fuse upper electrode that will be connected with capacitor lower electrode (Fig. 4 32) (Fig. 4 7) is pressed onto about this VPP, destroys thin gate insulating film under the fuse upper electrode (Fig. 4 7) (Fig. 4 5).
It is identical with embodiment 1 to read action, therefore omits explanation.
According to embodiment 2, the destruction of the thin gate insulating film 5 of anti-fuse 9 is undertaken by the current potential that boosts that electric capacity 31 produces, and does not therefore have excess current and flows, and has and can reduce the advantage of writing fashionable power consumption.And electric capacity 31 is formed on the top of anti-fuse 9, and therefore need not increase memory cell area can form.
(embodiment 3)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 3.Fig. 7 is the schematic diagram that the circuit of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 3 constitutes.
The Nonvolatile semiconductor memory device that embodiment 3 relates to has: cell group 40, control circuit 50, mode setting circuit 60.
The 1st selects circuit 51 according to the control signal from mode setting circuit 60, control each memory cell 40a, 40b ..., the switch of each wiring between 40n and the AND circuit 54.The 1st selects circuit 51 when a-signal is input to mode setting circuit 60, makes each wiring for the ON state, when the B signal is input to mode setting circuit 60, makes each wiring be the OFF state.
The 2nd selects circuit according to the control signal from mode setting circuit 60, control each memory cell 40a, 40b ..., the switch of each wiring between 40n and the OR circuit 55.The 2nd selects circuit 52 when a-signal is input to mode setting circuit 60, makes each wiring for the OFF state, when the B signal is input to mode setting circuit 60, makes each wiring be the ON state.
The 3rd selects circuit 53 according to controlling from the control signal of mode setting circuit 60, selects information and output from the side in AND circuit 54 and the OR circuit 55.The 3rd selects circuit 53 when a-signal is input to mode setting circuit 60, and output is from the information of AND circuit 54, and when the B signal was input to mode setting circuit 60, output was from the information of OR circuit 55.
AND circuit 54 from each memory cell 40a, 40b of cell group 40 ..., when 40n selects the signal of circuit 51 inputs all to be 1 (anti-fuse 9 conductings of Fig. 1) by the 1st, select circuit 53 as stored information output 1 to the 3rd, under the situation beyond this, select circuit 53 as stored information output 0 to the 3rd.
OR circuit 55 from each memory cell 40a, 40b of cell group 40 ..., 40n by the 2nd select circuit 52 inputs signal any one or when all being 1 (anti-fuse 9 conductings of Fig. 1), select circuit 53 as stored information output 1 to the 3rd, under the situation beyond this, select circuit 53 as stored information output 0 to the 3rd.
The pattern of 60 pairs of control circuits 50 of mode setting circuit is controlled.When mode setting circuit 60 is imported at a-signal, carry out following control, the output control signal makes the 1st to select circuit 51 to be the ON state, and makes the 2nd to select circuit 52 to be the OFF state, makes the 3rd to select circuit 53 to select AND circuit 54 1 sides.When mode setting circuit 60 is imported at the B signal, carry out following control, the output control signal makes the 1st to select circuit 51 to be the OFF state, and makes the 2nd to select circuit 52 to be the ON state, makes the 3rd to select circuit 53 to select OR circuit 55 1 sides.
One example of the action of Nonvolatile semiconductor memory device is described.
When before dispatching from the factory, a-signal being input to mode setting circuit 60, from each memory cell 40a, 40b of cell group 40 ..., the signal of 40n selects circuit 51 to be input to AND circuit 54 by the 1st, if each signal all is 1, then select circuit 53 as stored information output 1 by the 3rd from AND circuit 54.
When dispatching from the factory the B signal being input to mode setting circuit 60, from each memory cell 40a, 40b of cell group 40 ..., the signal of 40n selects circuit 52 to be input to OR circuit 55 by the 2nd, if any one of each signal or all be 1 then selects circuit 53 as stored information output 1 from OR circuit 55 by the 3rd.
According to embodiment 3, for example make the whether qualified criterion of anti-fuse (Fig. 1 9) in the back of dispatching from the factory than loose before dispatching from the factory, for memory cell 40a, 40b ..., the resistance change of the anti-fuse after the writing of 40n (Fig. 1 9) etc. through the time/through strain variation, can reduce the back of dispatching from the factory and cause bad probability because of anti-fuse (Fig. 1 9).
(embodiment 4)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 4.Figure 11 represents the schematic cross-section between the X-X ' formation, Figure 12 of the memory cell in the Nonvolatile semiconductor memory device that embodiments of the invention 4 relate to.Figure 12 is the part schematic plan view of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 4.
In the Nonvolatile semiconductor memory device that embodiment 1 (with reference to Fig. 1) relates to, connect contactor (Fig. 1 28) and be formed on the interlayer dielectric of selecting transistor (Fig. 1 8) and anti-fuse (Fig. 1 9) to go up film forming (Fig. 1 11), and be formed in the peristome of a part of the part that contains source (Fig. 1 3) and fuse upper electrode (Fig. 1 7).On the other hand, in the Nonvolatile semiconductor memory device that embodiment 4 relates to, connecting contactor is made of following: connect contactor 61a, be formed on the interlayer dielectric 11 of selecting film forming on transistor 8 and the anti-fuse 9, and be formed in the 1st peristome of a part that contains source 3; Connect contactor 61b, be formed on the interlayer dielectric 11, and be formed in the 2nd peristome of a part that contains fuse upper electrode 7; And metal line 62, be electrically connected connection contactor 61a and be connected contactor 61b.In anti-fuse 9, it is MOS semitransistor structure, on the part of the semiconductor substrate 1 in the zone between fuse lower electrode diffusion layer 27 and the element separated region 2 or fuse lower electrode diffusion layer 27, form the fuse upper electrode 7 that constitutes by poly-silicon by thin gate insulating film 5.In addition, other structures and action are identical with embodiment 1.
In addition, anti-fuse 9 preferably makes upper electrode 7 separate (with reference to Figure 25) with lower electrode 27.Concrete the same with embodiment 1.
According to embodiment 4, use two connection contactor 61a, 61b and metal line 62 to be electrically connected source 3 and fuse upper electrode 7, therefore and compare when using of embodiment 1 to be connected contactor, do not use the distortion contactor, so have the advantage of easy manufacturing.
(embodiment 5)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 5.Figure 13 is the part schematic section of the formation of the memory cell in the Nonvolatile memory devices that relates to of expression embodiments of the invention 5.
In the Nonvolatile semiconductor memory device that embodiment 5 relates to, selecting transistor 8 is N channel-styles, go up the P trap 1a that forms at semiconductor substrate (not shown) and upward constitute, anti-fuse 9 is P channel-styles, goes up the N trap 1b that forms at semiconductor substrate (not shown) and goes up formation.Other structures are identical with embodiment 4.
And anti-fuse 9 preferably makes upper electrode 7 separate (with reference to Figure 26) with lower electrode 27.Concrete identical with embodiment 1.
In addition, memory cell shown in Figure 13 (group) is a structure of selecting transistor and the series connection of anti-fuse as shown in figure 14.Memory cell is arranged in ranks, the gate electrode of each memory cell of line direction is connected with word line WR1, WR2, the opposing party's of each memory cell of column direction source is connected with bit line BL1, BL2, and the other end of the anti-fuse of each memory cell is electrically connected with universal source polar curve SOURCE.Select the N trap 1b of transistor portion on line direction, to dispose along word line WR1, WR2.The P trap 1a of anti-fuse part is configured between the N trap 1b.Select each N trap 1b of transistor portion to be electrically connected jointly on the whole in cell array.Each P trap 1a of anti-fuse part is electrically connected on the whole jointly in cell array.Universal source polar curve SOURCE also is electrically connected on the whole jointly in cell array.
Follow the action of the Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 5.Figure 14 is the schematic circuit diagram of the formation of the Nonvolatile memory devices that relates to of expression embodiments of the invention 5.Figure 15 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 5.
In reading in action, making P trap 1a and N trap 1b is earthing potential, make universal source polar curve SOURCE be the negative current potential-VPP that writes, make that to select bit line BL1 and select word line WR1 be the positive current potential VPP that writes, thereby by write from fuse lower electrode diffusion layer (Figure 13 27) and fuse upper electrode (Figure 13 7) positive and negative current potential+/-VPP (potential difference), destroy the thin gate insulating film (Figure 13 5) of anti-fuse (Figure 13 9).
In reading action, making P trap 1a, N trap 1b, reaching universal source polar curve SOURCE is earthing potential, to selecting word line WR1 and selecting bit line BL1 to apply IO current potential VddIO and carry out.Then conducting when the thin gate insulating film of anti-fuse (Figure 13 9) (Figure 13 5) is destroyed as not destroyed just non-conduction, thereby can be read the data that have been written to memory cell.
In addition, the control of Electric potentials of each wiring is undertaken by not shown controller.
According to embodiment 5, with positive and negative write current potential+/-VPP is applied to anti-fuse and writes, therefore have to make to write the advantage of current potential for low absolute value current potential.
(embodiment 6)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 6.Figure 16 is the part schematic section of the formation of the memory cell in the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.
In the Nonvolatile semiconductor memory device that embodiment 6 relates to, selecting transistor 8 is P channel-styles, go up the N trap 1b that forms at semiconductor substrate (not shown) and upward constitute, anti-fuse 9 is N channel-styles, goes up the P trap 1a that forms at semiconductor substrate (not shown) and goes up formation.Other structures are identical with embodiment 4.
In addition, anti-fuse 9 preferably makes upper electrode 7 separate (with reference to Figure 27) with lower electrode 27.Concrete identical with embodiment 1.
In addition, memory cell shown in Figure 16 (group) is a structure of selecting transistor and the series connection of anti-fuse as shown in figure 17.Memory cell is arranged in ranks, the gate electrode of each memory cell of line direction is connected with word line WR1, WR2, the opposing party's of each memory cell of column direction source is connected with bit line BL1, BL2, and the other end of the anti-fuse of each memory cell is electrically connected with universal source polar curve SOURCE.Select the N trap 1b of transistor portion on line direction, to dispose along word line WR1, WR2.The P trap 1a of anti-fuse part is configured between the N trap 1b.Select each N trap 1b of transistor portion and each P trap 1a of anti-fuse part to be electrically connected jointly on the whole in cell array respectively, the universal source polar curve SOURCE that is electrically connected with fuse lower electrode (Figure 16 27) is also in cell array electrical connection jointly on the whole.
Follow the action of the Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 6.Figure 17 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.Figure 18 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 6.
In write activity, making P trap 1a and universal source polar curve SOURCE is earthing potential, make and select bit line BL1, select word line WR1, and N trap (1b of Figure 16) for to write current potential VPP (positive current potential), thereby destroy the thin gate insulating film (Figure 16 5) of anti-fuse (Figure 16 9).
In reading action, making P trap 1a and universal source polar curve SOURCE is earthing potential, to select word line WR1, select bit line BL1, and N trap 1b apply IO current potential VddIO and carry out.The destroyed then conducting of the thin gate insulating film of anti-fuse (Figure 16 9) (Figure 16 5), not destroyed then non-conduction, thus can read the data that have been written to memory cell.
In addition, the control of Electric potentials of each wiring is undertaken by not shown controller.
According to embodiment 6, select transistor 8 to be the P channel-style by making, can suppress to write the Vt decline (threshold potential decline) of current potential VPP, the current potential VPP that writes that is applied to drain electrode (select bit line BL) can be applied directly to fuse upper electrode 7, therefore have finally and can make the advantage that writes current potential VPP lower voltage.In addition, shown in embodiment 5, when selecting transistor (Figure 16 8) when be the N channel-style, be applied to fuse upper electrode (Figure 16 7) from the descended current potential of threshold size and the current potential that obtains of current potential VPP that write that is applied to drain electrode (selection bit line BL).
(embodiment 7)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 7.Figure 19 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 7.Figure 20 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 7.
The Nonvolatile semiconductor memory device that embodiment 7 relates to has increased memory cell on the column direction of embodiment 6 (with reference to Figure 17).
The Nonvolatile semiconductor memory device that embodiment 7 relates to is identical in the following areas with embodiment 6 (with reference to Figure 16): selecting transistor is the P channel-style, go up the N trap 1b that forms at semiconductor substrate (not shown) and go up formation, anti-fuse is the N channel-style, and semiconductor substrate (not shown) is gone up the P trap 1a that forms and gone up formation.By the memory cell (group) of selecting transistor and anti-fuse to constitute as shown in figure 19, be the structure of selecting transistor and the series connection of anti-fuse.Memory cell is arranged in ranks, and the gate electrode of each memory cell of line direction is connected with word line WR1, WR2, WR3, and a side's of each memory cell of column direction source (regions and source) is connected with bit line BL1, BL2.The fuse lower electrode of the 1st row and the 2nd capable memory cell (Figure 16 27) is electrically connected with source electrode line SOURCE (1,2).The fuse lower electrode of the 3rd row and the 4th capable memory cell (Figure 16 27) is electrically connected with source electrode line SOURCE (3,4).The fuse lower electrode of the capable and n+1 line storage unit of not shown n (Figure 16 27) is electrically connected with source electrode line SOURCE (n, n+1).Select the N trap 1b of transistor portion to be configured on the line direction along word line WR1, WR2.The P trap 1a of anti-fuse part is configured between the N trap 1b.Select each N trap 1b of transistor portion to be electrically connected jointly on the whole in cell array.Each P trap 1a of anti-fuse part is electrically connected on the whole jointly in cell array.
In write activity, making P trap 1a and source electrode line SOURCE (1,2) is earthing potential, make source electrode line SOURCE (3,4) swim (open), make select bit line BL1, non-selection word line WR2, WR3, and N trap 1b for writing current potential VPP (positive potential), thereby destroy the thin gate insulating film (Figure 16 5) of anti-fuse (Figure 16 9).
In reading action, making P trap 1a, source electrode line SOURCE (1,2), SOURCE (3,4) is earthing potential, to select bit line BL1, non-selection word line WR2, WR3, and N trap 1b apply IO current potential VddIO and carry out.The destroyed then conducting of the thin gate insulating film of anti-fuse (Figure 16 5), not destroyed then non-conduction, thus can read the data that have been written to memory cell.
In addition, the control of Electric potentials of each wiring is undertaken by not shown controller.
According to embodiment 7, with two word line separation source polar curves, write the fashionable source electrode line ground connection that is connected with selected cell that only makes, another source electrode line is a floating state, have source electrode be applied to floating state non-selected cell anti-fuse write the advantage that interference significantly relaxes.In addition, in embodiment 7, select transistorized N trap general in cell array, write fashionable, N trap to the whole unit of non-selection also applies VPP, therefore the node potential of the anti-fuse upper electrode of non-selected cell floats, and the current potential between the lower electrode of the general source electrode of ground connection can be subjected to being applied to the interference that writes of anti-fuse dielectric film.
(embodiment 8)
The Nonvolatile semiconductor memory device that relates to reference to description of drawings embodiments of the invention 8.Figure 21 is the schematic circuit diagram of the formation of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 8.Figure 22 is that the table fashionable and current potential when reading is write in each wiring of the Nonvolatile semiconductor memory device that relates to of expression embodiments of the invention 8.
The Nonvolatile semiconductor memory device that embodiment 8 relates to is different with embodiment 6 (with reference to Figure 16), is not the P trap 1a, the N trap 1b that extend on the line direction are disposed alternately, but the P trap 1a, the N trap 1b that extend on column direction are disposed alternately.
The Nonvolatile semiconductor memory device that embodiment 8 relates to is identical in the following areas with embodiment 6 (with reference to Figure 16): selecting transistor is the P channel-style, go up the N trap 1b that forms at semiconductor substrate (not shown) and go up formation, anti-fuse is the N channel-style, goes up the P trap 1a that forms at semiconductor substrate (not shown) and goes up formation.By the memory cell (group) of selecting transistor and anti-fuse to constitute as shown in figure 21, be the structure of selecting transistor and the series connection of anti-fuse.Memory cell is arranged in ranks, and the gate electrode of each memory cell of line direction is connected with word line WR1, WR2, and the opposing party's of each memory cell of column direction source is connected with bit line BL1, BL2.The fuse lower electrode of each memory cell (Figure 16 27) is electrically connected with the universal source polar curve SOURCE that extends on column direction.Select the N trap 1b of transistor portion to be configured on the column direction along bit line BL1, BL2.The P trap 1a of anti-fuse part is configured between the N trap 1b.Select N trap (1) 1b and N trap (2) the 1b difference Be Controlled current potential of transistor portion.Each P trap 1a of anti-fuse part is electrically connected on the whole jointly in cell array, and the universal source polar curve SOURCE that is electrically connected with fuse lower electrode (Figure 16 27) is also in cell array electrical connection jointly on the whole.
In write activity, making N trap (2) 1b, P trap 1a, reaching universal source polar curve SOURCE is earthing potential, make select bit line BL1, non-selection word line WR2, and N trap (1) 1b for writing current potential VPP (positive potential), thereby destroy the thin gate insulating film (Figure 16 5) of anti-fuse.
In reading action, make N trap (2) 1b, P trap 1a, and universal source polar curve SOURCE be earthing potential, to select bit line BL1, non-selection word line WR2, and N trap (1) 1b apply IO current potential VddIO and carry out.The destroyed then conducting of the thin gate insulating film of anti-fuse (Figure 16 5), not destroyed then non-conduction, thus can read the data that have been written to memory cell.
According to embodiment 8, for writing the fashionable problem that writes interference that applies in the anti-fuse of non-selected cell of being subjected to, according to each bit line N trap (1), N trap (2) are separated into the row configuration, only the N trap of the cell columns of writing fashionable selection is applied and write voltage VPP, therefore what be subjected to writing interference only is the unit of same row, has the advantage that significantly relaxes interference time.
Claims (38)
1. Nonvolatile semiconductor memory device is characterized in that having:
Select transistor, its passage both sides at semiconductor substrate have the diffusion layer that forms regions and source, and on above-mentioned passage, have gate electrode by the 1st gate insulating film;
The element separated region is formed on the above-mentioned semiconductor substrate with above-mentioned selection transistor adjacent areas;
Anti-fuse, has the lower electrode that on above-mentioned semiconductor substrate, forms, and adjacent, and on the above-mentioned semiconductor substrate in the zone between said elements separated region and the above-mentioned lower electrode, has upper electrode by the 2nd gate insulating film with the said elements separated region; And
Connect contactor, be electrically connected between the side and above-mentioned upper electrode in the above-mentioned regions and source, and contact with a side and above-mentioned upper electrode in the above-mentioned regions and source.
2. Nonvolatile semiconductor memory device according to claim 1, it is characterized in that, above-mentioned connection contactor is formed on the interlayer dielectric of film forming on above-mentioned selection transistor and the above-mentioned anti-fuse, and is formed in the peristome that the part of the part of the side in the above-mentioned regions and source and above-mentioned upper electrode is contained as wall portion.
3. Nonvolatile semiconductor memory device according to claim 1, it is characterized in that, above-mentioned connection contactor is made of following: the 1st connects contactor, it is formed on the interlayer dielectric of film forming on above-mentioned selection transistor and the above-mentioned anti-fuse, and is formed in the 1st peristome that the part of the side in the above-mentioned regions and source is contained as wall portion; The 2nd connects contactor, is formed on the above-mentioned interlayer dielectric, and is formed in the 2nd peristome of a part that contains above-mentioned upper electrode; And wiring, it is electrically connected above-mentioned the 1st connection contactor and is connected contactor with the above-mentioned the 2nd.
4. Nonvolatile semiconductor memory device according to claim 1 is characterized in that, the gate insulating film that above-mentioned the 1st gate insulating film and above-mentioned the 2nd gate insulating film are identical thickness.
5. Nonvolatile semiconductor memory device according to claim 1 is characterized in that, above-mentioned the 2nd gate insulating film is thinner than above-mentioned the 1st gate insulating film.
6. according to any described Nonvolatile semiconductor memory device of claim 1 to 5, it is characterized in that above-mentioned lower electrode is that to import the diffusion layer have with above-mentioned regions and source be the diffusion layer of the impurity of same conductivity.
7. according to any described Nonvolatile semiconductor memory device of claim 1 to 5, it is characterized in that above-mentioned lower electrode is the impurity with the different conductivity types of diffusion layer of above-mentioned regions and source.
8. want 7 described Nonvolatile semiconductor memory devices according to right, it is characterized in that, the above-mentioned relatively upper electrode of above-mentioned lower electrode, the horizontal level relation does not repeat.
9. according to any described Nonvolatile semiconductor memory device of claim 1 to 8, it is characterized in that the lower electrode that contains each memory cell of above-mentioned selection transistor and above-mentioned anti-fuse is electrically connected with general source electrode line.
10. according to any described Nonvolatile semiconductor memory device of claim 1 to 9, it is characterized in that above-mentioned selection transistor is the N channel-style.
11. any described Nonvolatile semiconductor memory device according to claim 1 to 9 is characterized in that above-mentioned selection transistor is the P channel-style.
12. any described Nonvolatile semiconductor memory device according to claim 1 to 11, it is characterized in that, has controller, it carries out following control: during write activity, making above-mentioned semiconductor substrate and above-mentioned lower electrode is positive potential, and making the opposing party of above-mentioned regions and source and above-mentioned gate electrode is earthing potential.
13. any described Nonvolatile semiconductor memory device according to claim 1 to 11, it is characterized in that, has controller, it carries out following control: during write activity, making above-mentioned semiconductor substrate and above-mentioned lower electrode is earthing potential, and making the opposing party of above-mentioned regions and source and above-mentioned gate electrode is positive potential.
14. any described Nonvolatile semiconductor memory device according to claim 1 to 9 is characterized in that,
Above-mentioned selection transistor is the N channel-style, is formed on the P trap that forms on the above-mentioned semiconductor substrate,
Above-mentioned anti-fuse is the P channel-style, is formed on the N trap that forms on the above-mentioned semiconductor substrate.
15. Nonvolatile semiconductor memory device according to claim 14, it is characterized in that, has controller, it carries out following control: during write activity, make the transistorized P trap of above-mentioned selection, and the N trap of above-mentioned anti-fuse be earthing potential, making the above-mentioned lower electrode of above-mentioned anti-fuse is negative potential, and making the opposing party of the transistorized above-mentioned regions and source of above-mentioned selection and above-mentioned gate electrode is positive potential.
16. any described Nonvolatile semiconductor memory device according to claim 1 to 9 is characterized in that,
Above-mentioned selection transistor is the P channel-style, is formed on the N trap that forms on the above-mentioned semiconductor substrate,
Above-mentioned anti-fuse is the N channel-style, is formed on the P trap that forms on the above-mentioned semiconductor substrate.
17. Nonvolatile semiconductor memory device according to claim 16, it is characterized in that, has controller, it carries out following control: during write activity, making the above-mentioned P trap and the above-mentioned lower electrode of above-mentioned anti-fuse is earthing potential, make the opposing party of transistorized above-mentioned N trap of above-mentioned selection and above-mentioned regions and source be positive potential, making above-mentioned gate electrode is earthing potential.
18. any described Nonvolatile semiconductor memory device according to claim 1 to 17 is characterized in that,
Top at above-mentioned anti-fuse has electric capacity, and this electric capacity begins successively from lower floor's one side that lamination capacitor lower electrode, capacitor insulating film, electric capacity upper electrode form,
Above-mentioned capacitor lower electrode is electrically connected with the above-mentioned contactor that is connected.
19. Nonvolatile semiconductor memory device according to claim 18 is characterized in that, contain above-mentioned selection transistor, above-mentioned anti-fuse, and the electric capacity upper electrode of each memory cell of above-mentioned electric capacity be electrically connected with general printed line.
20. according to claim 18 or 19 described Nonvolatile semiconductor memory devices, it is characterized in that, has controller, it carries out following control: during write activity, making above-mentioned semiconductor substrate and above-mentioned lower electrode is earthing potential, and apply positive potential to above-mentioned drain electrode, and apply the high positive potential of current potential that applies than the opposing party to above-mentioned gate electrode to above-mentioned regions and source, afterwards, reduce the opposing party of above-mentioned regions and source and the current potential of above-mentioned gate electrode, and apply positive potential to above-mentioned electric capacity upper electrode.
21. any described Nonvolatile semiconductor memory device according to claim 1 to 20 is characterized in that having:
Cell group has a plurality of memory cell that contain above-mentioned selection transistor and above-mentioned anti-fuse; And
Control circuit is according to the signal from each said memory cells of said memory cells group, the output of control store information.
22. Nonvolatile semiconductor memory device according to claim 21 is characterized in that, above-mentioned control circuit has imports the OR circuit that has from the signal of each said memory cells.
23. Nonvolatile semiconductor memory device according to claim 21 is characterized in that, above-mentioned control circuit has imports the AND circuit that has from the signal of each said memory cells.
24. Nonvolatile semiconductor memory device according to claim 21 is characterized in that, above-mentioned control circuit has: input has the AND circuit from the signal of each said memory cells; With input OR circuit from the signal of each said memory cells is arranged.
25. Nonvolatile semiconductor memory device according to claim 24 is characterized in that, has mode setting circuit, controls the pattern of above-mentioned control circuit.
26. Nonvolatile semiconductor memory device according to claim 25 is characterized in that,
Have: the 1st selects circuit, controls the switch of each wiring between each said memory cells and the above-mentioned AND circuit;
The 2nd selects circuit, controls the switch of each wiring between each said memory cells and the above-mentioned OR circuit;
The 3rd selects circuit, controls, select and output from the information of the side in AND circuit and the OR circuit,
Above-mentioned mode setting circuit is controlled the above-mentioned the 1st and is selected circuit, the above-mentioned the 2nd to select circuit and the above-mentioned the 3rd to select circuit.
27. Nonvolatile semiconductor memory device according to claim 26 is characterized in that, above-mentioned mode setting circuit carries out following control:
When having imported the 1st signal, making the above-mentioned the 1st, to select circuit be the ON state, and making the above-mentioned the 2nd, to select circuit be the OFF state, exports the above-mentioned the 3rd and select circuit to select the control signal of above-mentioned AND circuit one side;
When having imported the 2nd signal, making the above-mentioned the 1st, to select circuit be the OFF state, and making the above-mentioned the 2nd, to select circuit be the ON state, exports the above-mentioned the 3rd and select circuit to select the control signal of above-mentioned OR circuit one side.
28. a Nonvolatile semiconductor memory device is characterized in that having:
Anti-fuse;
Select transistor, be electrically connected with an end of above-mentioned anti-fuse; And
Controller, it carries out following control: when carrying out write activity, apply the current potential that can destroy above-mentioned anti-fuse from the above-mentioned end of the above-mentioned anti-fuse of above-mentioned selection transistor one side direction.
29. Nonvolatile semiconductor memory device according to claim 28 is characterized in that,
Have a plurality of groups that constitute by above-mentioned anti-fuse and above-mentioned selection transistor,
The other end of each each above-mentioned anti-fuse of above-mentioned group is electrically connected jointly.
30. a Nonvolatile semiconductor memory device is characterized in that having:
A plurality of memory cell are selected the upper electrode of transistorized source electrode and anti-fuse to connect by being connected contactor, and are become the configuration of ranks ground;
A plurality of word lines are electrically connected with the transistorized gate electrode of each above-mentioned selection of line direction;
A plurality of bit lines are electrically connected with each above-mentioned selection transistor drain of column direction; And
Source electrode line is electrically connected with the lower electrode of above-mentioned anti-fuse between adjacent unit at least.
31. Nonvolatile semiconductor memory device according to claim 30 is characterized in that, above-mentioned selection transistor and above-mentioned anti-fuse are respectively the N channel-styles, are formed on the P trap.
32. Nonvolatile semiconductor memory device according to claim 30 is characterized in that,
Above-mentioned selection transistor is the N channel-style, is formed on the P trap,
Above-mentioned anti-fuse is the P channel-style, is formed on the N trap.
33. Nonvolatile semiconductor memory device according to claim 30 is characterized in that,
Above-mentioned selection transistor is the P channel-style, is formed on the N trap,
Above-mentioned anti-fuse is the N channel-style, is formed on the P trap.
34. Nonvolatile semiconductor memory device according to claim 33 is characterized in that, above-mentioned N trap extends configuration along above-mentioned word line on line direction.
35. Nonvolatile semiconductor memory device according to claim 33 is characterized in that, above-mentioned N trap extends configuration along above-mentioned bit line on column direction.
36. any described Nonvolatile semiconductor memory device according to claim 33 to 35 is characterized in that above-mentioned source electrode line is a universal source polar curve general in memory cell array integral body.
37. any described Nonvolatile semiconductor memory device according to claim 33 to 35 is characterized in that above-mentioned source electrode line is configured between the above-mentioned word line, and with above-mentioned word line between each above-mentioned lower electrode of the above-mentioned anti-fuse that disposes be electrically connected.
38. any described Nonvolatile semiconductor memory device according to claim 30 to 37 is characterized in that, above-mentioned anti-fuse is MOS semitransistor structure or MOS transistor structure.
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| JP2008009509 | 2008-01-18 | ||
| JP2008009509 | 2008-01-18 | ||
| JP2008118638 | 2008-04-30 | ||
| JP2008314894 | 2008-12-10 |
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Application publication date: 20090722 |