TWI553777B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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TWI553777B
TWI553777B TW102129162A TW102129162A TWI553777B TW I553777 B TWI553777 B TW I553777B TW 102129162 A TW102129162 A TW 102129162A TW 102129162 A TW102129162 A TW 102129162A TW I553777 B TWI553777 B TW I553777B
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electrode pad
soft metal
bonding
probe
wire
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TW201438144A (en
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Hitoshi Ikei
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Toshiba Kk
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4845Details of ball bonds
    • H01L2224/48451Shape
    • H01L2224/48453Shape of the interface with the bonding area
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

半導體裝置之製造方法 Semiconductor device manufacturing method

本發明之實施形態係關於一種半導體裝置之製造方法。 Embodiments of the present invention relate to a method of fabricating a semiconductor device.

作為於基板形成有包含各種半導體元件之電路的半導體晶片,為保護其不受外部之機械、物理、化學性衝擊,將該半導體晶片封裝使用。此時,必須將半導體晶片之電路電性引出至外部,作為其技術,已知有利用接合線將形成於半導體晶片之電極焊墊與封裝體之外部電極連接的方法(打線接合法)。 As a semiconductor wafer in which a circuit including various semiconductor elements is formed on a substrate, the semiconductor wafer is packaged and used in order to protect it from external mechanical, physical, and chemical impact. At this time, it is necessary to electrically extract the circuit of the semiconductor wafer to the outside. As a technique thereof, a method of bonding the electrode pad formed on the semiconductor wafer to the external electrode of the package by a bonding wire is known (wire bonding method).

於該打線接合法中,普遍使用金線作為接合線,但於LSI(Large Scale Integration,大型積體電路)領域亦研究有使用容易獲得之銅線來代替金線。 In the wire bonding method, a gold wire is generally used as a bonding wire. However, in the field of LSI (Large Scale Integration), it is also known to use a copper wire which is easy to obtain in place of a gold wire.

然而,由於銅硬度高於金,故而電極焊墊與銅線有時會發生連接不良。尤其是,於在封裝之前所進行的半導體晶片之電特性之檢查時形成於電極焊墊表面之探針的凹凸痕較大之情形時,若為硬度較高之銅,則無法填埋此種探針痕跡,從而易於發生連接不良。即,半導體晶片之電極焊墊亦用作特性檢查時之電極。因此,每當檢查時探針均會與其表面接觸,根據探針之形狀、接觸方法等,有時會於表面產生較大之凹凸。 However, since the hardness of copper is higher than that of gold, the electrode pads and the copper wires sometimes have poor connection. In particular, in the case where the unevenness of the probe formed on the surface of the electrode pad is large at the time of inspection of the electrical characteristics of the semiconductor wafer performed before packaging, if the copper having a high hardness is used, the filling cannot be performed. Probe traces are prone to poor connection. That is, the electrode pad of the semiconductor wafer is also used as an electrode for the characteristic inspection. Therefore, the probe will come into contact with its surface every time it is inspected, and depending on the shape of the probe, the contact method, etc., a large unevenness may be generated on the surface.

本發明所欲解決之問題在於提供一種可降低半導體晶片之電性 檢查時的因探針而引起之電極焊墊表面之凹凸痕的影響,且可藉由銅線實現半導體晶片與外部電極之可靠性較高之連接的半導體裝置之製造方法。 The problem to be solved by the present invention is to provide a method for reducing the electrical properties of a semiconductor wafer. A method of manufacturing a semiconductor device in which a highly reliable connection between a semiconductor wafer and an external electrode can be realized by a copper wire due to the influence of the unevenness on the surface of the electrode pad due to the probe during inspection.

實施形態之半導體裝置之製造方法包括如下步驟:(a)將硬度低於銅之軟質金屬埋入至包含電極焊墊之半導體晶片的凹部,該電極焊墊於表面具有因探針之接觸而形成之上述凹部;以及(b)將銅線接合於埋入有上述軟質金屬之上述電極焊墊之表面。 A method of manufacturing a semiconductor device according to an embodiment includes the steps of: (a) embedding a soft metal having a hardness lower than that of copper into a recess of a semiconductor wafer including an electrode pad having a surface formed by contact of a probe; And the (b) bonding the copper wire to the surface of the electrode pad in which the soft metal is embedded.

10‧‧‧半導體晶片 10‧‧‧Semiconductor wafer

12‧‧‧基板 12‧‧‧Substrate

14‧‧‧電極焊墊 14‧‧‧Electrical pads

16‧‧‧探針痕跡 16‧‧‧ Probe traces

18‧‧‧鋁線 18‧‧‧Aluminum wire

20‧‧‧銅線 20‧‧‧ copper wire

圖1(a)~(c)係表示一實施形態之半導體裝置之製造步驟之概略剖面圖。 1(a) to 1(c) are schematic cross-sectional views showing the steps of manufacturing a semiconductor device according to an embodiment.

圖2A係圖1(a)所示之電極焊墊之概略平面圖。 Fig. 2A is a schematic plan view of the electrode pad shown in Fig. 1(a).

圖2B係圖1(b)所示之電極焊墊之概略平面圖。 Fig. 2B is a schematic plan view of the electrode pad shown in Fig. 1(b).

圖3係形成於電極焊墊表面的探針痕跡之利用光學顯微鏡所拍攝之照片。 Fig. 3 is a photograph taken by an optical microscope of a probe trace formed on the surface of an electrode pad.

圖4係形成於電極焊墊表面的探針痕跡之利用3D顯微鏡所拍攝之照片。 Fig. 4 is a photograph taken of a probe trace formed on the surface of an electrode pad by a 3D microscope.

圖5係表示於利用比較例之方法使銅線接合於電極焊墊之情形時的探針痕跡之開口面積與銅線之接合強度之關係的圖表。 Fig. 5 is a graph showing the relationship between the opening area of the probe trace and the bonding strength of the copper wire when the copper wire is bonded to the electrode pad by the method of the comparative example.

圖6係表示於利用比較例之方法使銅線接合於電極焊墊之情形時的探針痕跡之凹凸之高低差與銅線之接合強度之關係的圖表。 Fig. 6 is a graph showing the relationship between the difference in height of the unevenness of the probe trace and the bonding strength of the copper wire when the copper wire is bonded to the electrode pad by the method of the comparative example.

以下,參照圖式,對實施形態進行說明。再者,圖式係僅用於圖解而提供者,本發明並不受該等圖式的任何限定。又,於以下說明中,對具有相同或大致相同之功能及構成之構成要素標註相同符號,並省略重複說明。 Hereinafter, embodiments will be described with reference to the drawings. Furthermore, the drawings are for illustration only and the invention is not limited by the drawings. In the following description, components having the same or substantially the same functions and configurations are denoted by the same reference numerals, and the description thereof will not be repeated.

圖1、圖2A及圖2B係用以說明一實施形態之半導體裝置之製造方法之圖,圖1係依照步驟順序表示製造步驟之概略剖面圖,圖2A係與圖1(a)相對應之概略平面圖,圖2B係與圖1(b)相對應之概略平面圖。該等各圖均僅表示形成於半導體晶片之電極焊墊及其附近。 1, 2A and 2B are views for explaining a method of manufacturing a semiconductor device according to an embodiment, and Fig. 1 is a schematic cross-sectional view showing a manufacturing step in accordance with a step sequence, and Fig. 2A corresponds to Fig. 1(a). A schematic plan view, and Fig. 2B is a schematic plan view corresponding to Fig. 1(b). Each of these figures only shows the electrode pads formed on the semiconductor wafer and its vicinity.

於本實施形態中,如圖1(a)所示,首先,準備半導體晶片10。該半導體晶片10經過如下步驟而被判別為良品,即,於使用有矽、藍寶石、GaAs(砷化鎵)等半導體材料之基板12上形成電路、或各種半導體元件與電路之步驟(製造步驟);以及對該電路之動作、半導體元件之電特性進行檢查之步驟(晶粒分類(Die Sorting)步驟)。 In the present embodiment, as shown in FIG. 1(a), first, the semiconductor wafer 10 is prepared. The semiconductor wafer 10 is judged to be a good product by the following steps, that is, a step of forming a circuit or various semiconductor elements and circuits on a substrate 12 using a semiconductor material such as germanium, sapphire or GaAs (gallium arsenide) (manufacturing step) And a step of checking the operation of the circuit and the electrical characteristics of the semiconductor element (die sorting step).

於該半導體晶片10之表面,露出用以將電路電性引出至外部的使用有Al或AlSi等Al合金等之電極焊墊14。由於電極焊墊14亦用作為晶粒分類步驟中之電極,故而於其表面殘留有於檢查時因探針接觸而產生之凹凸痕(以下,亦稱為探針痕跡)16。圖3係表示藉由光學顯微鏡拍攝此種探針痕跡之一例所得之照片,可觀察到於電極焊墊之表面殘留有探針之5次接觸痕跡。又,圖4係探針痕跡之利用3D顯微鏡所拍攝之照片。 On the surface of the semiconductor wafer 10, an electrode pad 14 using an Al alloy such as Al or AlSi for electrically extracting the circuit to the outside is exposed. Since the electrode pad 14 is also used as an electrode in the grain sorting step, irregularities (hereinafter also referred to as probe traces) 16 which are generated by the probe contact at the time of inspection remain on the surface. Fig. 3 is a photograph showing an example of such a probe trace taken by an optical microscope, and it was observed that five contact marks of the probe remained on the surface of the electrode pad. Further, Fig. 4 is a photograph of a probe trace taken by a 3D microscope.

繼而,對此種電極焊墊14連接用以將形成於半導體晶片10之電路電性引出至外部的接合線。先前,該步驟中,不修復殘留於電極焊墊14表面之探針痕跡16,而利用金或銅等之接合線進行連接。於此情形時,當使用硬度較低之金線作為接合線之情形時,金線亦會充分地進入至探針痕跡16的較大之凹凸,而獲得良好之接合強度。若為銅線,則由於硬度較高,故而與使用金線之情形時相比,對於電極焊墊14難以獲得接合強度,有時會發生連接不良。尤其是,於探針痕跡之開口面積(以下,僅稱為「面積」)較大、且凹凸之高低差較大之情形時,接合強度之降低較為顯著。 Then, the electrode pad 14 is connected to a bonding wire for electrically extracting a circuit formed on the semiconductor wafer 10 to the outside. Previously, in this step, the probe traces 16 remaining on the surface of the electrode pad 14 were not repaired, and the bonding wires of gold or copper were used for bonding. In this case, when a gold wire having a lower hardness is used as the bonding wire, the gold wire also sufficiently enters the large unevenness of the probe trace 16 to obtain a good bonding strength. In the case of a copper wire, since the hardness is high, it is difficult to obtain the bonding strength with respect to the electrode pad 14 as compared with the case of using a gold wire, and connection failure may occur. In particular, when the opening area of the probe trace (hereinafter, simply referred to as "area") is large and the height difference of the unevenness is large, the decrease in the joint strength is remarkable.

即,圖5係表示為了調查於利用比較例之方法將銅線接合於電極 焊墊之情形時的探針痕跡之開口面積與銅線之接合強度(剪切強度)之關係而進行的實驗結果的圖表,橫軸表示探針痕跡面積,縱軸表示接合強度(剪切強度)。又,圖6係表示為了調查於利用比較例之方法將銅線接合於電極焊墊之情形時的探針痕跡之凹凸之高低差與銅線之接合強度(剪切強度)之關係而進行的實驗結果的圖表,橫軸表示探針痕跡之凹凸之高低差,縱軸表示接合強度(剪切強度)。此處,所謂比較例之方法,係指不修復殘留於電極焊墊14表面之探針痕跡16,而利用接合線進行連接的方法。實驗均使用3種類型不同之探針而進行,用於接合之銅線之外徑或接合條件等其他條件均相同。再者,探針痕跡面積、探針痕跡之凹凸之高低差、及接合強度均以相對值而表示。自圖5及圖6明確可知,探針痕跡之面積越大,又,探針痕跡之凹凸之高低差越大,接合強度越為降低。 That is, FIG. 5 shows that in order to investigate the method of using a comparative example, a copper wire is bonded to an electrode. A graph showing the experimental results of the relationship between the opening area of the probe trace and the bonding strength (shear strength) of the copper wire in the case of the pad, the horizontal axis represents the probe trace area, and the vertical axis represents the joint strength (shear strength). ). Moreover, FIG. 6 shows the relationship between the height difference of the unevenness of the probe trace and the bonding strength (shear strength) of the copper wire when the copper wire is bonded to the electrode pad by the method of the comparative example. In the graph of the experimental results, the horizontal axis represents the height difference of the unevenness of the probe trace, and the vertical axis represents the joint strength (shear strength). Here, the method of the comparative example refers to a method of connecting by the bonding wires without repairing the probe traces 16 remaining on the surface of the electrode pad 14. The experiments were carried out using three types of probes, and the other conditions such as the outer diameter of the copper wire used for bonding or the bonding conditions were the same. Further, the probe trace area, the height difference of the probe traces, and the joint strength are all expressed as relative values. As is clear from Fig. 5 and Fig. 6, the larger the area of the probe trace, the larger the difference in the unevenness of the probe trace, and the lower the joint strength.

並且,近年來,隨著半導體元件之高積體化或電路之微細化等,電極焊墊尺寸有不斷小型化之傾向。於此種經小型化之電極焊墊中,上述探針痕跡面積占電極焊墊表面之比例亦變大,從而利用銅線之接合變得越發困難。 In addition, in recent years, with the increase in the size of semiconductor elements or the miniaturization of circuits, the size of electrode pads has been continuously reduced. In such a miniaturized electrode pad, the ratio of the probe trace area to the surface of the electrode pad is also increased, and the bonding by the copper wire becomes more difficult.

如此,於比較例之方法中,有時無法充分獲得銅線相對於電極焊墊之接合強度,更且,近年來電極焊墊之小型化不斷進展。因此,於本實施形態中,於將銅線連接於電極焊墊之前,如圖1(b)所示,使用鋁線18,以填埋其凹部、並且使其凹凸平坦化之方式針腳式接合(stitch bonding)於探針痕跡16。即,一面將鋁線18加熱一面將其壓抵於探針痕跡16,並埋入至凹部。圖2A所示之概略平面圖表示鋁線18針腳式接合於電極焊墊14之前的電極焊墊14之表面,圖2B表示鋁線18針腳式接合之後的電極焊墊14之表面。 As described above, in the method of the comparative example, the bonding strength of the copper wire to the electrode pad may not be sufficiently obtained, and in recent years, the miniaturization of the electrode pad is progressing. Therefore, in the present embodiment, before the copper wire is connected to the electrode pad, as shown in FIG. 1(b), the aluminum wire 18 is used, and the concave portion is filled and the unevenness is flattened. (stitch bonding) to the probe trace 16. That is, the aluminum wire 18 is pressed against the probe trace 16 while being heated, and is buried in the concave portion. The schematic plan view shown in Fig. 2A shows the surface of the electrode pad 14 before the aluminum wire 18 is stitched to the electrode pad 14, and Fig. 2B shows the surface of the electrode pad 14 after the 18-pin bonding of the aluminum wire.

於該步驟中,如圖2B所示,鋁線18無需覆蓋探針痕跡16整體,又,如圖1(b)所示,亦無需埋入至凹部表面為止。只要在下述之將銅 線進行打線接合時,將鋁線18埋入至可獲得所需之接合強度之程度即可。只要可獲得所需之接合強度,視情況亦可自凹部表面突出。具體而言,較佳為埋入探針痕跡16之至少1/2左右之面積,更佳為至少2/3左右。又,較佳為自所埋入之鋁線18表面至電極焊墊14表面為100nm左右以內。 In this step, as shown in FIG. 2B, the aluminum wire 18 does not need to cover the entire probe trace 16 and, as shown in FIG. 1(b), does not need to be buried in the surface of the recess. As long as the copper will be as follows When the wire is wire bonded, the aluminum wire 18 is buried to such an extent that the desired joint strength can be obtained. As long as the required joint strength is obtained, it may be protruded from the surface of the recess as the case may be. Specifically, it is preferable to embed at least about 1/2 of the probe trace 16 and more preferably at least about 2/3. Further, it is preferably from the surface of the embedded aluminum wire 18 to the surface of the electrode pad 14 within about 100 nm.

就獲得較高接合強度之觀點而言,較佳為所埋入之鋁線18之表面平坦,更佳為表面平坦、且埋入至與電極焊墊14之表面大致相同高度為止,亦即以使所埋入之鋁之表面與電極焊墊14之表面成為大致同一平面之方式埋入。藉由調節於針腳式接合時施加至鋁線18之荷重或加熱條件等,可提高所埋入之鋁表面之平坦性。進而,藉由調節所使用之鋁線之外徑,可調節鋁線18之埋入量,使鋁之表面與電極焊墊14之表面成為大致同一平面。於將鋁線18進行針腳式接合時,不僅對鋁線18加熱或施加荷重,亦可施加超音波。亦可藉由調整該超音波之輸出,而提高所埋入之鋁表面之平坦性。 From the viewpoint of obtaining a high bonding strength, it is preferable that the surface of the embedded aluminum wire 18 is flat, more preferably the surface is flat, and is buried to substantially the same height as the surface of the electrode pad 14, that is, The surface of the embedded aluminum is embedded in such a manner that the surface of the electrode pad 14 is substantially flush with the surface. The flatness of the embedded aluminum surface can be improved by adjusting the load applied to the aluminum wire 18 at the time of stitch bonding or heating conditions and the like. Further, by adjusting the outer diameter of the aluminum wire to be used, the amount of the aluminum wire 18 can be adjusted so that the surface of the aluminum and the surface of the electrode pad 14 are substantially flush with each other. When the aluminum wire 18 is stitch-bonded, not only the aluminum wire 18 is heated or a load is applied, but also ultrasonic waves can be applied. The flatness of the embedded aluminum surface can also be improved by adjusting the output of the ultrasonic wave.

再者,於本實施形態中,鋁對探針痕跡16之埋入係使用針腳式接合,但亦可使用例如金線之凸塊接合等方法。然而,就埋入之穩定性、生產性、成本等觀點而言,較佳為針腳式接合。 Further, in the present embodiment, the aluminum is used for the embedding of the probe traces 16 by stitch bonding, but a method such as bump bonding of gold wires may be used. However, from the viewpoints of stability, productivity, cost, and the like of embedding, stitch bonding is preferred.

又,於本實施形態中,係使用鋁作為埋入至探針痕跡16之材料,但只要為軟質金屬,即,硬度低於銅且可藉由加熱等容易地變形而埋入至探針痕跡16之金屬,並且為污染性較低且不會對半導體晶片之特性造成不良影響之金屬,便無特別限制而可使用。就埋入之容易性或獲得之容易性等觀點而言,較佳為使用鋁,於電極焊墊14包含Al或AlSi等Al合金之情形時,特佳為鋁。於本說明書中而使用時,所謂「鋁」之用語,不僅包含Al,亦包含以Al為主體之合金。 Further, in the present embodiment, aluminum is used as the material embedded in the probe trace 16. However, if it is a soft metal, that is, the hardness is lower than that of copper and can be easily deformed by heating or the like, it is buried in the probe trace. The metal of 16 is a metal which is less polluting and does not adversely affect the characteristics of the semiconductor wafer, and can be used without particular limitation. From the viewpoint of easiness of embedding or easiness of obtaining, it is preferable to use aluminum, and in the case where the electrode pad 14 contains an Al alloy such as Al or AlSi, aluminum is particularly preferable. When used in this specification, the term "aluminum" includes not only Al but also an alloy mainly composed of Al.

其後,如圖1(c)所示,藉由球形接合將銅線20連接於在探針痕跡16內埋入有鋁之電極焊墊14之表面。即,於第1接合側,藉由短路放 電於銅線之前端形成球,對該球加熱及施加荷重使其擠壓且連接於電極焊墊14上。此時,亦可對電極焊墊14施加超音波。 Thereafter, as shown in FIG. 1(c), the copper wire 20 is joined to the surface of the electrode pad 14 in which the aluminum is buried in the probe trace 16 by ball bonding. That is, on the first joint side, by short circuit A ball is formed on the front end of the copper wire, and the ball is heated and applied with a load to be pressed and attached to the electrode pad 14. At this time, ultrasonic waves can also be applied to the electrode pads 14.

於本實施形態中,由於在電極焊墊14表面之探針痕跡16內埋入有鋁,故而即便為硬度較高之銅線20,即使不增大接合時所施加之荷重、或不提高施加至電極焊墊14之超音波之輸出,亦能夠以較高之接合強度進行接合,從而可抑制連接不良之發生。又,由於不太需要增大接合時之荷重或提高超音波之輸出,故而可防止電極焊墊14之剝離、基板斷裂等,從而可提高銅線與電極焊墊之連接之可靠性。 In the present embodiment, since aluminum is embedded in the probe trace 16 on the surface of the electrode pad 14, even if the copper wire 20 having a high hardness is not increased in load or increased in application. The output of the ultrasonic wave to the electrode pad 14 can also be joined with a high bonding strength, thereby suppressing occurrence of connection failure. Further, since it is not necessary to increase the load at the time of bonding or increase the output of the ultrasonic wave, peeling of the electrode pad 14 and breakage of the substrate can be prevented, and the reliability of the connection between the copper wire and the electrode pad can be improved.

再者,於半導體晶片之厚度較薄為例如40~60μm左右之情形時,特別容易引起如上所述之電極焊墊之剝離或基板斷裂等。於本實施形態中,即便為此種薄型之半導體晶片,亦可進行不易引起電極焊墊14之剝離或基板斷裂等且可靠性較高之連接。 Further, when the thickness of the semiconductor wafer is as small as, for example, about 40 to 60 μm, peeling of the electrode pad or substrate breakage as described above is particularly likely to occur. In the present embodiment, even in the case of such a thin semiconductor wafer, it is possible to perform connection with high reliability, which is less likely to cause peeling of the electrode pad 14, or breakage of the substrate.

以上,對本發明之實施形態進行了說明,但實施形態係作為示例而提示者,而並非意欲限定發明之範圍。該新穎之實施形態能夠以其他各種形態實施,可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。實施形態或其變形包含於發明之範圍或主旨內,並且包含於申請專利之範圍所記載之發明及其均等之範圍內。 The embodiments of the present invention have been described above, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The invention and its modifications are intended to be included within the scope and spirit of the invention and are intended to be

10‧‧‧半導體晶片 10‧‧‧Semiconductor wafer

12‧‧‧基板 12‧‧‧Substrate

14‧‧‧電極焊墊 14‧‧‧Electrical pads

16‧‧‧探針痕跡 16‧‧‧ Probe traces

18‧‧‧鋁線 18‧‧‧Aluminum wire

Claims (5)

一種半導體裝置之製造方法,其特徵在於包括如下步驟:(a)將硬度低於銅之軟質金屬埋入至包含電極焊墊之半導體晶片的凹部,該電極焊墊於表面具有因探針之接觸而形成之上述凹部且包含鋁;及(b)將銅線接合於埋入有上述軟質金屬之上述電極焊墊之表面;且於上述步驟(a)中,上述軟質金屬向上述凹部之埋入係藉由包含上述軟質金屬之線之針腳式接合而進行,將上述軟質金屬埋入至上述凹部之開口面積之至少1/2,使埋入至上述凹部之軟質金屬表面與上述電極焊墊表面接近同一平面;上述軟質金屬為鋁。 A method of fabricating a semiconductor device, comprising the steps of: (a) embedding a soft metal having a hardness lower than that of copper into a recess of a semiconductor wafer including an electrode pad having a contact with a probe on a surface thereof And forming the recessed portion to include aluminum; and (b) bonding the copper wire to the surface of the electrode pad in which the soft metal is embedded; and in the step (a), embedding the soft metal into the recessed portion Performing a stitch bonding including a line of the soft metal, embedding the soft metal in at least 1/2 of an opening area of the concave portion, and embedding the soft metal surface embedded in the concave portion with the surface of the electrode pad Near the same plane; the soft metal is aluminum. 一種半導體裝置之製造方法,其特徵在於包括如下步驟:(a)將硬度低於銅之軟質金屬埋入至包含電極焊墊之半導體晶片的凹部,該電極焊墊於表面具有因探針之接觸而形成之上述凹部且包含鋁;及(b)將銅線接合於埋入有上述軟質金屬之上述電極焊墊之表面;且上述軟質金屬為鋁。 A method of fabricating a semiconductor device, comprising the steps of: (a) embedding a soft metal having a hardness lower than that of copper into a recess of a semiconductor wafer including an electrode pad having a contact with a probe on a surface thereof And forming the recessed portion to include aluminum; and (b) bonding the copper wire to the surface of the electrode pad in which the soft metal is embedded; and the soft metal is aluminum. 如請求項2之半導體裝置之製造方法,其中於上述步驟(a)中,上述軟質金屬向上述凹部之埋入係藉由包含上述軟質金屬之線之針腳式接合而進行。 The method of manufacturing a semiconductor device according to claim 2, wherein in the step (a), the embedding of the soft metal into the concave portion is performed by stitch bonding including a line of the soft metal. 如請求項2或3之半導體裝置之製造方法,其中於上述步驟(a)中,將上述軟質金屬埋入至上述凹部之開口面積之至少1/2。 The method of manufacturing a semiconductor device according to claim 2 or 3, wherein in the step (a), the soft metal is buried in at least 1/2 of an opening area of the concave portion. 如請求項2或3之半導體裝置之製造方法,其中於上述步驟(a) 中,使埋入至上述凹部之軟質金屬表面與上述電極焊墊表面接近同一平面。 The method of manufacturing a semiconductor device according to claim 2 or 3, wherein in the above step (a) In the middle, the surface of the soft metal embedded in the concave portion is close to the same plane as the surface of the electrode pad.
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