KR101680458B1 - Wafer level semiconductor package - Google Patents

Wafer level semiconductor package Download PDF

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Publication number
KR101680458B1
KR101680458B1 KR1020150040456A KR20150040456A KR101680458B1 KR 101680458 B1 KR101680458 B1 KR 101680458B1 KR 1020150040456 A KR1020150040456 A KR 1020150040456A KR 20150040456 A KR20150040456 A KR 20150040456A KR 101680458 B1 KR101680458 B1 KR 101680458B1
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South Korea
Prior art keywords
metal layer
under bump
bump metal
input
output terminal
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KR1020150040456A
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Korean (ko)
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KR20160114750A (en
Inventor
심재범
김병진
유지연
소광섭
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020150040456A priority Critical patent/KR101680458B1/en
Publication of KR20160114750A publication Critical patent/KR20160114750A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to a wafer level semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a wafer level chip size / package structure in which an under bump metal structure, in which input / output terminals are fused, Scale semiconductor package and a method of manufacturing the same.
That is, the present invention improves the under bump metal layer formed on the bonding pads of the semiconductor chip to a structure capable of dispersing and removing external stress, and plating the solder as the input / output terminal on the under bump metal layer, A bonding force between an input / output terminal and a bonding strength of an under bump metal layer to a bonding pad of a semiconductor chip, and a manufacturing method thereof.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer level semiconductor package,

The present invention relates to a wafer level semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a wafer level chip size / package structure in which an under bump metal structure, in which input / output terminals are fused, Scale semiconductor package and a method of manufacturing the same.

2. Description of the Related Art [0002] With the trend toward higher performance and miniaturization of electronic products, semiconductor packages mounted on motherboards of electronic products are also manufactured with a structure with miniaturization and high performance.

As an example of a semiconductor package satisfying miniaturization, a wafer level chip scale package can be mentioned. The wafer level is a state in which each semiconductor chip is packaged in a state in which individual semiconductor chips are not separated from the wafer, .

Here, the structure and manufacturing process of the conventional wafer level chip scale package will be described.

1 is a cross-sectional view illustrating a wafer level chip scale package according to a conventional example.

A designed circuit is integrated in the semiconductor chip 10 in a wafer state, and a bonding pad 12 is formed at a portion which becomes an electric input / output path of the circuit.

A die passivation layer 14 for protecting the integrated circuit is formed on the entire surface of each semiconductor chip 10 in the wafer state and a die passivation layer 14 is formed on the bonding pad 12 for electrical input / 14) is not coated.

Subsequently, an under bump metal layer (16: UBM, Under Bump), which is an electrode terminal of a metal material, is formed as a place where input / output terminals such as conductive bumps or solder balls are fused to the bonding pads 12 of the semiconductor chip 10 by a general plating process. Matal) is formed.

At this time, the under bump metal layer 16 is formed of nickel or gold material, which is easily metal-bonded to input / output terminals such as a solder ball, or a method of thickly plating copper.

Next, a die passivation layer 14 (not shown) is formed to protect the joint portion between the input / output terminal 18 and the under bump metal layer 16 while maintaining the coupling force of the input / output terminal 18 to the under bump metal layer 16 The molding compound resin 20 is molded at a smaller height than the input / output terminals 18 over the surface of the molding resin 20.

However, since the external stress introduced during each manufacturing process and the external stress introduced in the process of mounting on the electronic device after completion of packaging are directly transferred to the under bump metal layer 16 through the input / output terminal 18, And the under bump metal layer 16 is also detached from the bonding pad of the semiconductor chip due to the concentration of external stress. .

2, the plating thickness of the under bump metal layer 16 is increased so as to have robustness against the external stress, but the wafer level is increased to the same level as the height of the molding compound resin 20 Chip scale package.

However, since the external stress introduced during each manufacturing process and the external stress introduced in the process of mounting on the electronic device after the completion of packaging can be transmitted directly to the under bump metal layer 16 through the input / output terminal 18 The interface bonding force between the input / output terminal 18 and the under bump metal layer 16 is weakened or the interface bonding strength between the under bump metal layer 16 and the bonding pad of the semiconductor chip is weakened.

Since the interface between the under bump metal layer 16 and the molding compound resin 20 forms a straight surface, the bonding force between the under bump metal layer 16 and the molding compound resin 20 is weakened as the external stress is concentrated. There is a possibility.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to improve an under bump metal layer formed on a bonding pad of a semiconductor chip to a structure capable of removing external stress, Level semiconductor package and a method for manufacturing the same, which can improve the bonding force between the under bump metal layer and the input / output terminal and the bonding force of the under bump metal layer to the bonding pads of the semiconductor chip, .

Another object of the present invention is to provide an under bump metal layer formed on a bonding pad of a semiconductor chip and forming a solder having a larger area on the under bump metal layer so that external stress transmitted from the solder to the under bump metal layer Level semiconductor package and a method of manufacturing the semiconductor package.

According to an aspect of the present invention, there is provided a wafer level semiconductor package comprising: an under bump metal layer plated on a bonding pad of a wafer level semiconductor chip; An input / output terminal formed on the under bump metal layer; And an under bump metal layer joined to the input / output terminal is formed to have a larger cross-sectional area than a lower portion of the under bump metal layer. The lower portion of the under bump metal layer is formed to have a narrow cross- .

Preferably, the under bump metal layer is composed of a flat horizontal plate joined to the input / output terminals, and a vertical bar integrally formed with the bottom central portion of the horizontal plate and bonded to the bonding pads, wherein the horizontal plate and the vertical bar are & Sectional shape.

Also, a molding compound resin that covers the periphery of the under bump metal layer while being exposed to form an input / output terminal is molded to a predetermined thickness on the upper surface of the semiconductor chip.

According to an aspect of the present invention, there is provided a wafer level semiconductor package manufacturing method comprising: providing a wafer; Attaching a photoresist having an exposure hole on the wafer and exposing a bonding pad of each semiconductor chip to the outside through an exposure hole; And forming an under bump metal layer on the bonding pad of the semiconductor chip using a plating process, wherein the under bump metal layer is formed by a first plating process in the exposure hole and a second plating process on the outer peripheral portion of the upper surface of the exposure hole, ; ≪ / RTI > After the photoresist is removed, overmolding the molding compound resin over the upper surface of the semiconductor chip so that the entire surface of the under bump metal layer is covered; The upper portion of the molding compound resin and the upper portion of the under bump metal layer are flattened so that the upper portion of the under bump metal layer is formed as a flat horizontal plate and the lower portion is formed as a vertical bar having a smaller cross sectional area at the bottom central portion of the horizontal plate ; Forming an input / output terminal on a horizontal plate of an under bump metal layer exposed to the outside through the molding compound resin; And a control unit.

According to another aspect of the present invention, there is provided a wafer level semiconductor package comprising: an under bump metal layer plated on a bonding pad of a wafer level semiconductor chip; An input / output terminal formed on the under bump metal layer; And an input / output terminal having a larger cross-sectional area than the under bump metal layer is formed on the upper surface of the under bump metal layer by a plating process.

Preferably, the input / output terminal and the under bump metal layer have an umbrella-shaped cross-sectional structure and are stacked on each other.

The molding compound resin is molded to a predetermined thickness on the semiconductor chip so as to surround the under bump metal layer and the lower end of the input / output terminal.

According to another aspect of the present invention, there is provided a wafer level semiconductor package manufacturing method comprising: providing a wafer; Attaching a photoresist having an exposure hole on the wafer and exposing a bonding pad of each semiconductor chip to the outside through an exposure hole; Forming an under bump metal layer on a bonding pad of the semiconductor chip through plating in the exposure hole; Forming an input / output terminal and an under bump metal layer on the upper surface of the under bump metal layer and the upper surface of the upper surface of the exposed hole with an input / output terminal having a larger cross sectional area than the under bump metal layer, Overmolding the molding compound resin over the upper surface of the semiconductor chip so that the entire surface of the under bump metal layer and the lower end of the input / output terminals are wrapped after the photoresist is removed; And a control unit.

According to another aspect of the present invention, there is provided a wafer level semiconductor package comprising: an under bump metal layer plated on a bonding pad of a wafer level semiconductor chip; An input / output terminal formed on the under bump metal layer; And an input / output terminal having a narrow cross-sectional area on the upper surface and a wide cross-sectional area on the upper surface of the under bump metal layer is formed by a plating process.

Preferably, the input / output terminal includes a column portion joined to the under bump metal layer, and a head portion integrally formed with a larger cross-sectional area on the column portion, and is formed into an umbrella-shaped cross-sectional structure.

Also, the molding compound resin is molded to a predetermined thickness on the semiconductor chip so as to surround the under bump metal layer and the periphery of the lower end of the head portion of the input / output terminal.

According to another aspect of the present invention, there is provided a wafer level semiconductor package manufacturing method comprising: providing a wafer; Attaching a photoresist having an exposure hole on the wafer and exposing a bonding pad of each semiconductor chip to the outside through an exposure hole; Forming an under bump metal layer on a bonding pad of the semiconductor chip through a process of plating on a bottom side of the exposure hole; A step of forming a column portion to be connected to the upper surface of the under bump metal layer by primary plating in the exposure hole and a process of forming a head portion having a larger cross- An input / output terminal plating step in which the input / output terminals are formed into an elliptic cross section; Overmolding the molding compound resin over the upper surface of the semiconductor chip so that the entire surface of the under bump metal layer and the periphery of the lower end of the head portion of the input / output terminal are wrapped after the photoresist is removed; And a control unit.

Through the above-mentioned means for solving the problems, the present invention provides the following effects.

First, when fabricating a wafer level chip scale semiconductor package, the under bump metal layer or the input / output terminal formed on the bonding pad of the semiconductor chip is newly improved to have a structure composed of a wide area flat plate and a narrow area vertical rod, (The path from the horizontal plate to the vertical rods), so that the external stress can be dispersed and removed.

Second, the under bump metal layer or the input / output terminal is improved to have a structure composed of a wide area flat plate and a narrow area vertical rod to disperse and remove external stress, so that the bonding force between the under bump metal layer and the input / The bonding strength of the under bump metal layer to the metal layer can be improved.

1 and 2 are sectional views showing a conventional wafer level chip scale package,
FIGS. 3A through 3E are cross-sectional views illustrating a wafer-level chip scale package according to an embodiment of the present invention,
FIGS. 4A to 4D are cross-sectional views illustrating a wafer-level chip scale package according to another embodiment of the present invention,
5A to 5D are cross-sectional views illustrating a wafer-level chip scale package according to another embodiment of the present invention in the order of manufacturing steps.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

3A to 3E are cross-sectional views illustrating a wafer level chip scale package according to a first embodiment of the present invention in the order of manufacturing steps.

3A to 3E, reference numeral 10 denotes a semiconductor chip in a wafer state.

First, in a state where the wafer is provided, a photoresist 30 having an exposure hole 32 is attached to the wafer (see FIG. 3A).

At this time, the bonding pads 12 of the semiconductor chip 10 are exposed to the outside through the exposure holes 32 of the photoresist 30.

Next, a step of forming an under bump metal layer 16 on the bonding pad 12 of the semiconductor chip 10 using a plating process is performed.

For this, a metal (for example, copper or nickel) for the under bump metal layer is filled in the exposure hole 32 by a conventional plating process, and the first plating And the metal for the under bump metal layer is secondarily plated in a semicircular shape to the outer peripheral portion of the upper surface of the exposure hole 32 while being connected to the plating layer in the exposure hole 32 (see FIG. 3B).

At this time, the under bump metal layer 16 has a semicircular upper end portion having a wider cross-sectional area than the lower end portion of the vertical bar shape due to the primary and secondary plating as described above.

After the photoresist 30 is removed by an etching process or the like, the molding compound resin 20 is over-molded on the upper surface of the semiconductor chip 10 so that the entire surface of the under bump metal layer 16 is covered. (See FIG. 3C).

Subsequently, the upper part of the molding compound resin 20 and the upper part of the under bump metal layer 16, that is, the upper part of the semicircular part, are flattened so that the surface of the molding compound resin 20, The upper surfaces of the bump metal layers 16 are flush with each other (see FIG. 3D).

At this time, the upper end portion of the under bump metal layer 16 is formed as a flat horizontal plate 22 in a semicircular shape, and the lower end portion is formed as a vertical bar 24 having a smaller cross sectional area at the bottom central portion of the horizontal plate 22 .

The under bump metal layer 16 is integrally formed on the bottom surface of the bottom plate of the horizontal plate 22 and bonded to the input / output terminal 18 by a bonding pad 12, and the horizontal plate 22 and the vertical bar 24 have a "T" -shaped cross-sectional shape.

That is, the upper end portion of the under bump metal layer 16 is located at a position where the portion of the horizontal plate 22 to which the input / output terminal 18 is bonded is larger than the portion of the vertical bar 24 to which the bonding pad 12 of the semiconductor chip 10 is bonded Section so that the horizontal plate 22 and the vertical bar 24 have a "T" -shaped cross-sectional shape.

Finally, the input / output terminals 18 of the solder material are formed by using the ball drop process on the horizontal plate 22 of the under bump metal layer 16 exposed to the outside through the molding compound resin 20, A wafer level chip scale package according to the first embodiment of the present invention is completed (see FIG. 3E).

As described above, the under bump metal layer 16 formed on the bonding pad 12 of the semiconductor chip 10 is composed of the horizontal plate 22 having a large area and the vertical bar 24 having a small area, Output terminal 18 is formed on the upper surface of the horizontal plate 22 so that the transmission path of the external stress forms a long path bent from the conventional one (a path from the horizontal plate to the vertical bar) (24), and can be easily dispersed and removed when passing.

The external stress is easily dispersed and removed so that the interface bonding force between the under bump metal layer 16 and the input / output terminal 18 and the interface between the bonding pad 12 of the semiconductor chip 10 and the under bump metal layer 16 The bonding force can be improved.

Since the anchor groove structure in which the molding compound resin 20 is filled between the bottom surface of the horizontal plate 22 of the under bump metal layer 16 and the peripheral surface of the vertical bar 24 is formed, The bonding force between the molding compound resin 16 and the molding compound resin 20 can also be improved.

Second Embodiment

4A to 4D are cross-sectional views illustrating a wafer level chip scale package according to a second embodiment of the present invention.

4A to 4D, reference numeral 10 denotes a semiconductor chip in a wafer state.

First, in a state where the wafer is provided, a photoresist 30 having an exposure hole 32 is attached to the wafer (see FIG. 4A).

At this time, the bonding pads 12 of the semiconductor chip 10 are exposed to the outside through the exposure holes 32 of the photoresist 30.

Next, a step of forming an under bump metal layer 16 on the bonding pad 12 of the semiconductor chip 10 using a plating process is performed.

A metal (e.g., copper or nickel) for the under bump metal layer is filled in the exposure hole 32 by a conventional plating process so that an under bump metal layer 16 is formed on the bonding pad 12 Where the under bump metal layer 16 is flush with the photoresist 30 (see FIG. 4B).

Output terminal 18 is formed on the surface of the under bump metal layer 16 using a conventional plating process. At this time, the input / output terminal 18 extends to the outer peripheral portion of the upper surface of the exposure hole 32 And plated in semicircular cross-sectional shape at the same time (see Fig. 4C).

The under bump metal layer 16 has a columnar shape in the form of a vertical bar and the input / output terminal 18 has a wider cross-sectional area than the under bump metal layer 16 and forms a semicircular head.

That is, the input / output terminal 18 and the under bump metal layer 16 have an umbrella-shaped cross-sectional structure and are stacked on each other.

After the photoresist 30 is removed by an etching process or the like, a molding compound resin (not shown) is formed on the upper surface of the semiconductor chip 10 so as to surround the lower end portions of the under bump metal layer 16 and the input / The semiconductor wafer 20 is overmolded to a predetermined thickness to complete the wafer level chip scale semiconductor package according to the second embodiment of the present invention (see FIG. 4D).

At this time, the upper end (convex portion) of the input / output terminal 18 is left for mounting on the motherboard of the electronic device, and the molding compound resin 20 is overmolded to a height at which the lower end thereof is wrapped.

As described above, the under bump metal layer 16 formed on the bonding pad 12 of the semiconductor chip 10 is plated with a narrow cross-sectional area as compared with the input / output terminal 18, and then the input / output By plating the terminal 18, the external stress transmission path forms a long path (a path that is transmitted from the input / output terminal of a wide cross-sectional area to the under bump metal layer of a narrow cross-sectional area) It can be easily dispersed and removed when it passes through the under bump metal layer.

The external stress is easily dispersed and removed so that the interface bonding force between the under bump metal layer 16 and the input / output terminal 18 and the interface between the bonding pad 12 of the semiconductor chip 10 and the under bump metal layer 16 The bonding force can be improved.

The anchor groove structure in which the molding compound resin 20 is filled is formed between the bottom surface of the input / output terminal 18 and the circumferential surface of the under bump metal layer 16, The lower end of the semicircular shape of the input / output terminal 18 is wrapped and locked by the molding compound resin 20 to prevent separation of the input / output terminal 18 The bonding holding force can be improved.

Third Embodiment

5A to 5D are cross-sectional views illustrating a wafer level chip scale package according to a third embodiment of the present invention.

First, in the state where the wafer is provided, a photoresist 30 having an exposure hole 32 is attached on the wafer (see FIG. 5A).

At this time, the bonding pads 12 of the semiconductor chip 10 are exposed to the outside through the exposure holes 32 of the photoresist 30.

Next, a step of forming an under bump metal layer 16 on the bonding pad 12 of the semiconductor chip 10 using a plating process is performed.

A metal (for example, copper or nickel) for the under bump metal layer is filled in the bottom surface of the exposure hole 32 by a conventional plating process so that an under bump metal layer The under bump metal layer 16 is not completely filled in the exposure hole 32 but is plated on the bottom side of the exposure hole 32 (see FIG. 5B).

Output terminal 18 is formed on the surface of the under bump metal layer 16 using a conventional plating process. At this time, the input / output terminal 18 extends to the outer peripheral portion of the upper surface of the exposure hole 32 Thereby forming an umbrella-shaped cross-sectional structure (see FIG. 5C).

That is, the input / output terminal 18 includes a vertical bar-shaped column portion 26 joined to the under bump metal layer 16, and a semi-circular head portion 28, and is formed into an umbrella-shaped cross-sectional structure.

After the photoresist 30 is removed by an etching process or the like, the lower end portions of the column portion 26 and the head portion 28 of the input / output terminal 18 as well as the under bump metal layer 16 are surrounded The semiconductor chip 10 is overmolded with a molding compound resin 20 over the upper surface of the semiconductor chip 10 to complete the wafer level chip scale semiconductor package according to the third embodiment of the present invention (see FIG. 5D).

At this time, the upper end portion (convex portion) of the head portion 28 of the input / output terminal 18 is left for the motherboard mounting of the electronic device, and the molding compound resin 20 ).

As described above, the under bump metal layer 16 formed on the bonding pad 12 of the semiconductor chip 10 is plated with a narrow cross-sectional area as compared with the input / output terminal 18, and then the column portion 26 and the head portion Output terminal 18 having a larger cross-sectional area and made of a material having a larger cross-sectional area than that of the input / output terminal 18 having a larger cross- The external stress can be easily dispersed and removed when the external stress is introduced into the column from the head portion of the input / output terminal.

The external stress is easily dispersed and removed so that the interface bonding force between the under bump metal layer 16 and the input / output terminal 18 and the interface between the bonding pad 12 of the semiconductor chip 10 and the under bump metal layer 16 The bonding force can be improved.

The anchor groove structure in which the molding compound resin 20 is filled between the bottom surface of the head portion 28 of the input / output terminal 18 and the circumferential surface of the column portion 26 is formed, The coupling force between the compound resin 20 can be improved and the head portion 28 of the input / output terminal 18 is wrapped and locked by the molding compound resin 20 to prevent separation of the input / Can be improved.

10: Semiconductor chip
12: bonding pad
14: die passivation layer
16: under bump metal layer
18: I / O terminal
20: Molding compound resin
22: Vertical plate
24: vertical bar
26:
28: head
30: Photoresist
32: Exposure hole

Claims (12)

delete delete delete A wafer providing step;
Attaching a photoresist having an exposure hole on the wafer and exposing a bonding pad of each semiconductor chip to the outside through an exposure hole;
And forming an under bump metal layer on the bonding pad of the semiconductor chip using a plating process, wherein the under bump metal layer is formed by a first plating process in the exposure hole and a second plating process on the outer peripheral portion of the upper surface of the exposure hole, ; ≪ / RTI >
After the photoresist is removed, overmolding the molding compound resin over the upper surface of the semiconductor chip so that the entire surface of the under bump metal layer is covered;
The upper portion of the molding compound resin and the upper portion of the under bump metal layer are flattened so that the upper portion of the under bump metal layer is formed as a flat horizontal plate and the lower portion is formed as a vertical bar having a smaller cross sectional area at the bottom central portion of the horizontal plate ;
Forming an input / output terminal on a horizontal plate of an under bump metal layer exposed to the outside through the molding compound resin;
≪ / RTI > wherein the semiconductor wafer is a semiconductor wafer.
An under bump metal layer plated on a bonding pad of a wafer level semiconductor chip;
An input / output terminal formed on the under bump metal layer;
, ≪ / RTI &
An input / output terminal having a larger cross-sectional area than the under bump metal layer is formed on the upper surface of the under bump metal layer by a plating process,
The input / output terminal and the under bump metal layer are laminated to form an umbrella-shaped cross-sectional structure,
The molding compound resin is molded to have a predetermined thickness on the semiconductor chip so as to surround the under bump metal layer and the lower end of the input / output terminal so that the lower end of the semicircular shape of the input / output terminal 18 is wrapped by the molding compound resin 20, Wherein the semiconductor wafer is a semiconductor wafer.
delete delete A wafer providing step;
Attaching a photoresist having an exposure hole on the wafer and exposing a bonding pad of each semiconductor chip to the outside through an exposure hole;
Forming an under bump metal layer on a bonding pad of the semiconductor chip through plating in the exposure hole;
Forming an input / output terminal and an under bump metal layer on the upper surface of the under bump metal layer and the upper surface of the upper surface of the exposed hole with an input / output terminal having a larger cross sectional area than the under bump metal layer,
Overmolding the molding compound resin over the upper surface of the semiconductor chip so that the entire surface of the under bump metal layer and the lower end of the input / output terminals are wrapped after the photoresist is removed;
≪ / RTI > wherein the semiconductor wafer is a semiconductor wafer.
An under bump metal layer plated on a bonding pad of a wafer level semiconductor chip;
An input / output terminal formed on the under bump metal layer;
, ≪ / RTI &
Output terminals having a narrow cross-sectional area on the upper surface of the under bump metal layer and a wide cross-sectional area on the upper portion are formed by a plating process,
The input / output terminal is composed of a column portion to be joined to the under bump metal layer and a semicircular head portion having a larger cross sectional area on the column portion and integral therewith,
The molding compound resin is molded to a predetermined thickness on the semiconductor chip such that the under bump metal layer and the periphery of the lower end of the head portion of the input / output terminal are wrapped around the head portion of the input / output terminal by the molding compound resin. Semiconductor package.
delete delete A wafer providing step;
Attaching a photoresist having an exposure hole on the wafer and exposing a bonding pad of each semiconductor chip to the outside through an exposure hole;
Forming an under bump metal layer on a bonding pad of the semiconductor chip through a process of plating on a bottom side of the exposure hole;
A step of forming a column portion to be connected to the upper surface of the under bump metal layer by primary plating in the exposure hole and a process of forming a head portion having a larger cross- An input / output terminal plating step in which the input / output terminals are formed into an elliptic cross section;
Overmolding the molding compound resin over the upper surface of the semiconductor chip so that the entire surface of the under bump metal layer and the periphery of the lower end of the head portion of the input / output terminal are wrapped after the photoresist is removed;
≪ / RTI > wherein the semiconductor wafer is a semiconductor wafer.
KR1020150040456A 2015-03-24 2015-03-24 Wafer level semiconductor package KR101680458B1 (en)

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CN117393523B (en) * 2023-12-07 2024-03-08 浙江集迈科微电子有限公司 Multilayer wiring adapter plate for mounting and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294761A (en) * 2005-04-07 2006-10-26 Sharp Corp Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device
JP2007081325A (en) * 2005-09-16 2007-03-29 Murata Mfg Co Ltd Thin film capacitor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294761A (en) * 2005-04-07 2006-10-26 Sharp Corp Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device
JP2007081325A (en) * 2005-09-16 2007-03-29 Murata Mfg Co Ltd Thin film capacitor

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