TWI552159B - Address generating method - Google Patents

Description

Method of generating an address

The present invention is directed to a method of generating an address, and more particularly to a method of reducing the time at which an address is generated.

The data of the memory in the electronic device is usually randomly accessible, so the random write/read test must be performed when testing the memory. Before the memory chip tapout, the test platform (eg verilog testbench) will execute about tens of thousands (for example, 60,000) of test patterns, and each test program will use several randomly generated ones. Row/column addresses. In the memory test, the randomly selected memory address (Address) is selected as short as possible, and the randomly generated memory address should be kept as far as possible, thereby reducing the test time (test cost is tested) The machine's operation test time increased.

If the random address used by each test program is different under the premise of not affecting the overall run time as much as possible, it will help to improve the coverage of the verification.

Embodiments of the present invention provide a method for randomly generating an address to shorten the time for randomly generating an address.

An embodiment of the present invention provides a method for randomly generating an address, including the following steps: (a) sorting a plurality of addresses in high order bits and low order bits, high order bits. Forming a plurality of high-order addresses, low-order bit shapes a plurality of low-order addresses; (b) randomly generating the address having high-order bits and low-order bits, wherein when all low-order addresses corresponding to one of the plurality of high-order addresses are generated And masking the corresponding higher order address; and (c) repeating step (b) until all the addresses represented by the high order bit and the low order bit are generated.

In summary, the embodiments of the present invention provide a method for generating an address by defining an address in a high-order bit and a low-order bit, and in all low-order corresponding to one of the plurality of high-order addresses. When the address is generated, the corresponding high-order address is masked, thereby saving the time for randomly generating the address.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

(a), (b), S310, S320, S330, S340‧‧

FIG. 1 is a flowchart of a method for generating an address according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a manner of representing a plurality of addresses according to an embodiment of the present invention.

FIG. 3 is a flowchart of a method for generating an address according to an embodiment of the present invention applied to a memory test.

[Embodiment of Method of Generating Address]

Please refer to FIG. 1. FIG. 1 is a flowchart of a method for generating an address according to an embodiment of the present invention. This embodiment provides a method for randomly generating an address, including the following steps: (a) sorting a plurality of addresses in high order bits and low order bits, and forming high order bits. a plurality of high-order addresses, the low-order bits forming a plurality of low-order addresses; (b) randomly generating the addresses having high-order bits and low-order bits, wherein one of the plurality of high-order addresses corresponds to When all low-order addresses are generated, the corresponding higher-order addresses are masked; and (c) repeating step (b) until All addresses represented by high order bits and low order bits are generated. The method can be used to test a memory, the address being a plurality of memory addresses of the memory, but the invention is not limited thereby. The method can be applied to any hardware and software circuit that requires random generation of an address.

In step (a), each address includes a plurality of bits, each of which is represented by a binary. The present invention does not limit the total number of bits that the address has, nor the number of bits that the high order bit and the lower order bit respectively have. For example, consider a 12-bit address, taking one of the 12-bit addresses 101010101111 as an example. When defining the first eight bits (8 bits) are high-order bits, the first bit, the third one. The bit, the fifth bit, and the seventh bit are "1", and the second bit, the fourth bit, the sixth bit, and the eighth bit are "0", then 10101010 is High-order address. And the next four bits (4 bits) are low-order bits, then 1111 is a low-order address. Since step (a) defines the address, each high-order address in the high-order bit may correspond to all low-order addresses of the low-order bit (eg, any high-order address of eight bits is located corresponding to Sixteen (2 ⁴ ) low-order addresses: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111). Accordingly, the high-order address and the low-order address form a complete 12-bit address.

The above step (b) can randomly generate an address (including a high-order address and a low-order address) and record the generated address. And step (b) further determines whether all low-order addresses corresponding to a certain high-order address have been generated. When the determination is yes, the corresponding high-order address is masked, and the lower-order bits are randomly generated next time. The address is such that the lower-order address corresponds to a different high-order address. For example, taking a 12-bit address as an example, when the first eight bits in the definition are high-order bits, and the next four bits are defined as low-order bits, when the randomly generated address is in the address Sixteen low-order addresses corresponding to the high-order address (00000001) (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) If it is generated again, then when step (b) is performed again, in order to not generate the same address, the high-order address (00000001) can be directly masked and other high-orders that have not been masked are randomly generated. The address is such that the randomly generated low order bits correspond to other high order addresses.

It is worth mentioning that after each step (b), the write/read test program can be performed on the memory address generated by the random. After the test program is completed, the step (b) is performed again in the connection. In other words, each time a random address is generated, a test is performed on the address. However, the present invention does not therefore limit the software or hardware procedures to be performed each time step (b) is performed.

In an embodiment, please refer to FIG. 2. FIG. 2 is a schematic diagram showing a manner of indicating a plurality of addresses according to an embodiment of the present invention. For example, FIG. 2 is an example of an address representation of a 12-bit address, but the present invention is not limited thereto. In the example shown in FIG. 2, a 12-bit address can be represented by an arrangement of high-order bits having eight bits and low-order bits having four bits. The high-order bits can be divided into a plurality of sub-high-order bits. As shown in FIG. 2, the high-order bits are divided into two sub-high-order bits, which are the above: 4 bits, and the middle: 4 bits. The lower order bits of Figure 2 are as follows: 4bit representation. The definitions of the high order bits and the low order bits may be changed according to actual needs, and the present invention is not limited thereto. The address representation of Figure 2 is for illustrative purposes only, and will help to illustrate the subsequent embodiment of Figure 3, which is not intended to limit the invention.

The following is a description of the actual application mode of the memory test in the step (b) of FIG. 1. Referring to FIG. 3, FIG. 3 is a flowchart of a method for generating an address according to an embodiment of the present invention. In actual implementation, step (b) of FIG. 1 can be implemented by steps S310, S320, S330, S340 of FIG. In detail, first, in step S310, one of the addresses represented by the high-order bit and the low-order bit is randomly generated, for example, the two sub-high-order bits of FIG. 2 (upper: 4 bit, and medium: 4 bit), and Low order bit (bottom: 4bit).

Next, in step S320, it is judged whether or not the randomly generated address has been generated. In actual implementation, according to step (b) of FIG. 1 , step S320 further includes: after randomly generating the address, the randomly generated address may be recorded and stored in a register, to be 2 12-bit address as an example, the scratchpad storage is randomly generated The octet high-order address, and 4096 corresponding low-order addresses, and each bit of the high-order address (upper: 4bit, and medium: 4bit each bit) can be set as a flag For example, each of the eight bits can be set to correspond to a flag. That is, corresponding to the randomly generated address, the register stores a flag corresponding to the high-order address (8-bit flag) and a lower-order address (4-bit lower-order address). The flag of the high-order address can be used to change the flag to be masked after the subsequent determination of the corresponding lower-order address has been generated, thereby saving the time for randomly generating the address.

When the randomly generated address has not been generated in step S320, the process is temporarily left to perform a write/read test procedure for the address.

Further, in the process of determining whether the address is generated in step S320, it is further determined whether all of the plurality of low-order addresses corresponding to a certain high-order address have been generated, when one of the plurality of high-order addresses is corresponding. When all low-order addresses are generated, the corresponding high-order address is masked, that is, the flag of the high-order address is changed. The masked high-order address is excluded in the process of randomly generating the address. Accordingly, the next time step 330 is performed, the address with the masked high-order address can be excluded to avoid duplicate addresses. For example, when the high-order address (00000001) corresponds to the sixteen low-order addresses (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) has been generated, then mask this high-order address (00000001).

When the randomly generated address has been generated, step S330 is performed to randomly generate another address that has not been generated. Then, in step S340, it is determined whether all the addresses have been generated. When all the addresses have not been generated, the process returns to the foregoing step S320 after the end of step S340 to determine again whether all the corresponding multiple high-order addresses are corresponding. Low-order addresses have been generated to determine whether to mask a higher-order address, and then leave the process to write/read test procedures for this newly generated address. On the other hand, when all the addresses have been generated, all the addresses recorded in step S320 are cleared, and a test of the memory block of the memory is completed. Then, when another memory block is tested, the above-described step flow S310, S320, S330, S340 can be executed again. Depending on the size of the memory required for the test, the test procedure of Figure 3 may need to be repeated multiple times to test the full memory.

Regarding the definition of high-order bits and low-order bits, in the example of FIG. 2, when the number of bits of the high-order bit (8 bits) and the number of bits of the low-order bits (4 bits) are a multiple of 3 ( That is, the number of bits of the address is 8+4=12 bits. In this embodiment, the high-order bits are divided into two sub-high-order bits (upper: 4bit, and medium: 4bit), and each sub-high-order bit The number of bits (4 bits) is the same as the number of bits (4 bits) of the lower order bits (bottom: 4 bits). It can be inferred that in a similar embodiment, when the sum of the number of bits of the high order bits and the number of bits of the low order bits is a multiple of m (ie, the total number of bits of the address is a multiple of m), the high order bits are distinguished. It is m-1 sub-high order bits, and the number of bits of each sub-high order bit is the same as the number of low-order bits, where m is a positive integer greater than or equal to 2. However, the present invention does not thus limit the manner in which high order bits and low order bits are divided. When the number of bits of the lower-order address is larger, the time required to randomly generate the lower-order address may increase. Conversely, the higher the number of bits in the high-order address, the larger the scratchpad space that needs to be utilized. In practical applications, the division of high-order addresses, and the allocation of the number of bits of high-order and low-order bits can be changed according to requirements, and is a tradeoff at the time of engineering design, and the present invention is not limited thereto. In this embodiment, when the number of bits of the high-order bit and the number of bits of the low-order bit are N, and N/m is a positive integer, the process of randomly generating all addresses according to step (b) The time at which the last address is generated can be expressed as m2 ^N/m . Then, the total time from the generation of the first address to the generation of the last address can be expressed as

In contrast, in the conventional method of randomly generating an address, when the total number of bits of the address is also N, the time at which the last address is generated in the process of randomly generating all addresses can be expressed as 2 ^N , and the utilization is utilized. The traditional random address generation method can be expressed as the total time from the generation of the first address to the generation of the last address.

In the case of an 18-bit (18-bit) address, the total time required for the method of the present embodiment is 907, and the time required for the conventional method is 524,286, and the difference is about 577 times. Therefore, it can be seen that the time taken to randomly generate the address by using the method of the embodiment is short, and when the number of bits of the address is larger (when N is larger), the method of the present embodiment and the conventional method are utilized. The difference in time spent is greater.

[Possible effects of the examples]

In summary, the method for generating an address provided by the embodiment of the present invention is defined by using the high-order bit and the low-order bit as the address, and when all of the corresponding high-order addresses are low. When the order address is generated, the corresponding high-order address is masked, thereby saving the time for randomly generating the address. The method for generating an address can be used for generating a memory address in a memory test program, any software program that needs to randomly generate an address, or can be applied to a related application such as a non-repetitive digital generator in a hardware implementation.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

(a), (b) ‧ ‧ step process

Claims (8)

A method for generating an address, comprising: (a) sorting a plurality of addresses by a high order bits and a low order bits, the high order bits forming a plurality of high order bits Address, the low order bit forms a plurality of low order addresses; (b) randomly generating the addresses having the high order bit and the low order bit, wherein when corresponding to the higher order address And (c) repeating step (b) until the high-order bit and the low-order bit are represented by the high-order address corresponding to one of the low-order addresses of the one of the lower-order addresses; All of these addresses are generated. The method of generating an address according to item 1 of the claim, wherein the method is for testing a memory, the addresses being a plurality of memory addresses of the memory. The method of generating an address according to item 2 of the claim, wherein after the step (b), the write/read test procedure is performed on the memory address generated by the random. The method of generating an address according to item 1 of the claim, wherein the high order bit is divided into a plurality of sub-high order bits. The method for generating an address according to Item 1 of the claim, wherein when the sum of the number of bits of the high order bit and the number of bits of the low order bit is a multiple of m, the high order bit is divided into m-1 a high-order bit, and the number of bits of each of the sub-high-order bits is the same as the number of bits of the low-order bit, where m is a positive integer greater than or equal to 2. According to the method of generating an address of item 1 of the claim, wherein in step (b), the randomly generated addresses are recorded, and the step (b) performed again after the step (c) comprises: determining the randomly generated Whether all of the low-order addresses corresponding to one of the high-order addresses have been generated; when the randomly generated address has been generated, the other one is randomly generated again. The address of this. The method for generating an address according to Item 6 of the claim, wherein in the step (b), the method further includes: when all of the addresses are generated, clearing all of the recorded addresses. According to the method for generating an address according to Item 1, wherein the sum of the number of bits of the high order bit and the number of bits of the low order bit is N, and N/m is a positive integer, then step (b) is random. The time at which the last address is generated in the process of generating the addresses is expressed as m2 ^N/m .