TWI725306B - Memory repair method - Google Patents

Abstract

The present invention provides a method for repairing a memory, providing a group of multiple memory bytes with M bits, and each additional repair byte has N repair bits for repair, providing a Group and memory plus repair bytes with the same or greater than the total number of non-volatile control memory bytes, and detect all memory bytes, repair bytes and control memory bytes in the memory Whether there is a bad bit in the middle to complete the repair. Or provide a control memory address byte with Q bits for each memory byte and repair byte to mark the bad bit addresses in the memory byte and repair byte, and Check whether there are bad bits in all memory bytes, repair bytes, and control memory address bytes in the memory to complete the repair.

Description

Memory repair method

The present invention provides a method for repairing memory, especially a method for repairing memory bit level.

Nowadays, memory can be divided into volatile or non-volatile memory. Volatile memory, such as Random Access Memory (RAM), is related to the central processing unit (Central Processing Unit, CPU) The memory that directly exchanges data can also be called the main memory. It can be read and written at any time and is very fast. It is usually used as a temporary data storage medium for the operating system or other running programs. RAM can be further divided into two categories: Static Random-Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). SRAM has the advantage of fast access. The disadvantage is that the production cost is relatively expensive, and the main application is cache. Because DRAM has a lower price per unit capacity, it is mainly used in the main memory of the system. It also includes some emerging memories such as Phase-Change Memory, Resistive Random Access Memory, Magnetoresistive Random Access Memory and so on.

Because of its fast operating speed, SRAM is often used as a buffer device between CPU and DRAM in computer devices. For example, Cache Memory can increase the operating speed of the system without being affected by the output bits, and the number of output bits is high. SRAM as the design target. However, after the manufacture of high-capacity memory products is completed, as the capacity increases and the density of the memory bit array increases, various non-ideal factors existing in the IC manufacturing process can easily cause defects in the memory and reduce the memory. The yield rate of the body may further prevent the normal operation of the memory product.

In general memory, because it is prone to defects during manufacturing, when the memory is initially designed, part of the internal space is used as a redundant memory bit area. When the memory product is tested and found to have defects or poor memory positions At the same time, redundant memory bits can be provided to replace these poor memory bits to exert repair performance and effectively improve the manufacturing yield of memory products.

At present, most of the conventional volatile memory is designed with a redundant row (Row Redundancy) auxiliary circuit to replace the damaged memory array in the memory, because the structure is simple and does not cause the chip size to be large. The amplitude increases, but the general redundant row structure is quite complicated. If the redundant rows are added to the redundant memory bits of the memory, the area will increase greatly. Therefore, generally, the redundant rows will not be added during the design. In the memory, once the output of the row array is damaged, it cannot be repaired. In addition, the operation of detecting bits of conventional memory is used in fast memory through inspection one by one. It is easy to slow down the overall speed and reduce the manufacturing yield when the memory bits are damaged. Therefore, in order to ensure the yield rate, the conventional memory is prone to produce a larger area.

Therefore, in the trend of gradual reduction in the volume of various electronic products, various volatile memories will inevitably need to reduce their own size. However, in how to ensure the contradiction of manufacturing yield, operating speed and size, find the best way to deal with it. It is a difficult problem to solve.

In view of this, in order to solve the problem of conventional memory bit restoration, the present invention specifically proposes a memory restoration method to solve the lack of memory bit restoration in the memory.

The main purpose of the present invention is to provide a memory repair method, which is used to increase the repair speed of the memory and increase the manufacturing yield of the memory. The finally manufactured memory chip is smaller than the conventional memory chip. , Suitable for all kinds of reduced volume electronic products.

Another object of the present invention is to provide a method for repairing memory. In order to avoid manufacturing defects and cause partial bit defects when manufacturing the memory, using this repair method, the repair bit can be used to replace what needs to be repaired. Data bits, or use the control memory location byte to make the bad bits Meta tags are then tested and repaired so that this memory can operate smoothly.

In order to achieve the above objective, the present invention provides a memory repair method, which includes the following steps. First, a set of memory has a plurality of memory bytes and M bits, M is a positive integer, relative to each A repair byte is added to the memory byte, and there are N repair bits for repair. N is a positive integer and N is less than M, and a set is the same as or greater than the memory plus the repair byte The non-volatile control memory byte group of the total number of bits is used to detect whether there are bad bits in all memory bytes, repair bytes and control memory bytes in the memory. If not, stop the memory Repair, if it is, the memory byte with any bad bit and the repair byte will correspond to the number of bad bits in the memory byte, and the equivalent number of non-bad bytes in the self-repairing byte will be repaired The bit substitutes all the bad bits of the memory byte to complete the repair of each memory byte in the memory and the mark of the bad bit in the repair byte.

In the present invention, the control memory byte sets are non-volatile memory, one-time programmable memory, multiple-time programmable memory, and NOR flash memory.

In the present invention, the control memory byte sets are phase change memory, resistive random access memory, and magnetoresistive random access memory.

In the present invention, first mark the control memory bit corresponding to the bad bit of the memory byte and the repair byte, and mark the bad bit in the control memory byte. When the bit and the repair bit are detected as non-bad bits, but if the corresponding memory bit is a bad bit, the bits of the memory byte group and the repair bit are still regarded as bad bits. The marking method is to write the bits in the control memory byte group corresponding to the bad bits and the bad bits of the control memory byte group to a memory state different from the non-bad bits of the control memory.

In the present invention, each memory byte, repair byte and this set of control memory system use internal reading, writing and disturbance, as well as external temperature, magnetic field, and electric field disturbances to detect whether there are bad bits.

In the present invention, after this group of memories is repaired, each bit and each repair bit are rearranged.

In the present invention, the repaired memory byte and each repaired byte are used for data bits, and can also be used for check bits used for correction bits, so as to improve reliability during use.

In the present invention, each memory byte, each repair byte, and each control memory byte can be used in combination with the bit line and word line repair methods to repair the bit line level and word line level defects, In order to achieve excellent repair efficiency.

M+N，接著檢測記憶體中所有記憶體位元組、修復位元組與對照記憶體位址位元組中是否具有不佳位元，若否，結束記憶體的修復，若是，將具有任一不佳位元的記憶體位元組，以自修復位元組中的一個非不佳的修復位元替補至記憶體位元組的不佳位元，以完成記憶體中每一記憶體位元組的任一不佳位元修復和修復位元組中之不佳位元的標記。 In order to achieve the above-mentioned object, the present invention provides a memory repair method, which includes the following steps. First, a group of memory has a plurality of memory bytes and M bits, M is a positive integer, relative to each A memory byte is appended with a repair byte, which has N repair bits for repair. N is a positive integer, and N is less than M. A comparison memory is provided for each memory byte and repair byte. Body address byte, which has Q bits for marking the bad bit address in the memory byte and repairing the byte, and 2 ^Q

M+N, then check whether there are bad bits in all memory bytes, repair bytes, and control memory address bytes in the memory, if not, end the memory repair, if so, it will have any The memory byte of the bad bit is replaced by a non-bad repair bit in the self-repairing byte to the bad bit of the memory byte to complete each memory byte in the memory Any bad bit repairs and repairs the mark of the bad bit in the byte group.

In the present invention, the reference memory address byte is non-volatile memory, one-time programmable memory, multiple-time programmable memory, and NOR flash memory.

In the present invention, the reference memory address byte sets are phase change memory, resistive random access memory, and magnetoresistive random access memory.

In the present invention, first mark the bad bits of the memory byte and repair byte in the corresponding control memory address byte, and write the bit address of the bad bit to the corresponding control memory location In the address byte group, if there is no bad bit in the memory byte and repair byte, the corresponding comparison will be recorded. The memory address byte is written into the byte address of the non-memory byte.

In the present invention, the repaired memory byte and each repaired byte are used for data bits, and can also be used for check bits used for correction bits, so as to improve reliability during use.

In the present invention, each memory byte group, each repair byte group, and each control memory address byte group can be used in combination with bit line and word line repair methods to repair the bit line level and the word line level Defects in order to achieve excellent repair efficiency.

In the present invention, each memory byte, repair byte and this set of control memory address byte are detected by internal read, write and disturbance, and external temperature, magnetic field, and electric field disturbance to detect whether there is a bad bit. yuan.

The following detailed descriptions are combined with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, characteristics and effects of the present invention.

10‧‧‧Memory

12‧‧‧Memory byte

122‧‧‧bit

14‧‧‧Repair byte

142‧‧‧Repair bit

16‧‧‧Compare memory byte

20‧‧‧Memory

22‧‧‧Memory Bytes

222‧‧‧bit

24‧‧‧Repair byte

242‧‧‧Repair bit

26‧‧‧Compare memory address byte

262‧‧‧bit

The first figure is a simplified schematic diagram of the memory and its memory byte and repair byte in the present invention.

The second figure is a flowchart of the first embodiment of the memory repair method in the present invention.

The third figure a to the third figure c are schematic diagrams of the steps of the memory repair method of the present invention.

The fourth figure is a flowchart of the steps of the second embodiment of the memory repair method of the present invention.

The present invention discloses different conventional memory repair methods to achieve the technical characteristics of small size, high yield and fast repair speed, and is more suitable for use in reduced-volume electronic products to save space.

First of all, please refer to the first figure of the present invention. A group of memory 10 includes a plurality of memory bytes 12 including M bits 122, M is a positive integer, and a complex repair bit is added to each memory byte 12 Tuple 14, which has N repair bits 142 for repair, N is also a positive integer, and N is small In M, this embodiment first takes the 128-bit memory byte 12 and the 32-bit repair byte 14 as an example, that is, there are 128 bits 122 and 32 repair bits 142. In addition, a set of non-volatile control memory byte groups 16 having the same or greater number of total bits as the memory 10 is provided, and also has M control bits and N control repair bits, which means these M control bits The number of bits is the same as that of bit 122, for example, they are all 128 bits, and the bit arrangement positions are also the same, and the number of N comparison repair bits is the same as that of repair bits 142, for example, they are all 32 bits, and The element arrangement position is also the same, and the number of these bits is not a limitation of the invention in the present invention. In this embodiment, the non-volatile control memory byte 16 is a non-volatile memory (Non-Volatile Memory), but the present invention is not limited to this, and the control memory byte 16 can also be a one-time Programmable memory (OTP), multiple programmable memory (MTP), NOR flash memory (NOR Flash) or phase-change memory (Phase-Change Memory), resistive random access memory ( Resistive Random Access Memory, Magnetoresistive Random Access Memory.

Next, please refer to the second figure of the present invention, and also refer to figures 3 a to 3 d, to explain in detail how the memory 10 is repaired in the present invention. First, as shown in step S10 and referring to the third figure a, a set of memory 10 is provided, including a plurality of memory bytes 12, which have 128-bit bits 122. As shown in step S12, and referring to the third figure b, with respect to each memory byte group 12, a repair byte group 14 is added, which has 32 repair bits 142 for repair. As shown in step S14, and referring to Figure 3c, a set of non-volatile control memory byte groups 16 that are the same as or greater than the total number of bits of the memory 10 plus repair byte 14 are provided. As shown in step S16, check whether all the memory byte 12 and repair byte 14 in the memory 10 and the control memory byte 16 have bad bits. If bad bits are detected, enter Next step. As shown in step S18, the memory byte 12 and the repair byte 14 with any bad bit are corresponding to the bad bit number of the memory byte 12, and the same number of the memory byte 12 is self-repaired. The non-bad repair bit 142 is substituted for all bad bits of the memory byte 12 to complete the repair of each memory byte 12 in the memory 10, and the repair bit The mark of the bad bit in the tuple 14, in this embodiment, the internal read, write, disturbance and disturbance of the external temperature, magnetic field, and electric field are used as each memory byte 12 and repair byte 14 And check whether the memory byte 16 has a bad bit, for example, first mark the check memory bit corresponding to the bad bit of the memory byte 12 and repair byte 14, and mark the check memory bit The bad bit in the tuple 16, if the bit 122 of the memory byte 12 and the repair bit are detected as non-bad bits, but if the corresponding memory bit is a bad bit, the memory bit is still considered The bit 122 and the repair bit 142 of the tuple 12 are bad bits. The marking method is to write the bits in the control memory byte group 16 corresponding to the bad bits and the bad bits of the control memory byte 16 to a memory state that is different from the non-bad bits of the control memory. Regardless of whether it is the repair of the memory 10 or the control memory 16, after the repair, each bit 122 and each repair bit 142 therein will be rearranged. If no bad bit is detected in step S16, the process proceeds to step S20, and the repair of the memory 10 is ended.

The above-mentioned repaired memory bytes and each repaired byte can provide data bits for use, and can also provide parity bits for correction bits (Error-Correction Code, ECC) to improve Reliability in use. Each memory byte, each repair byte and each control memory byte can be used in combination with bit line and word line repair methods to repair bit line and word line level defects, so as to achieve Excellent repair efficiency.

M+N，本實施例的對照記憶體位址位元組26係可為一次性可程式記憶體(OTP)、多次性可程式記憶體(MTP)、NOR快閃記憶體(NOR Flash)或是為相變化記憶體(Phase-Change Memory)、電阻式隨機存取記憶體(Resistive Random Access Memory)、磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory)，本發明不以此為限制。如步驟S36所示，檢測記憶體20中所有記憶體位元組22和修復位元組24與對照記憶體位址位元組26中是否具有不佳位元，若檢測出具有不佳位元時，則進入下一步驟。如步驟S38所示，將具有任一不佳位元的記憶體位元組22以自修復位元組24的一個非不佳的修復位元替補至記憶體位元組22的不佳位元，以完成記憶體20中每一記憶體位元組22的任一不佳位元之修復，以及修復位元組24中不佳位元的標記，在本實施例中係以內部讀、寫與擾動(disturb)以及外部溫度、磁場、電場之擾動做每一記憶體位元組22、修復位元組24及對照記憶體位址位元組26是否具有不佳位元的檢測，例如，先將記憶體位元組22和修復元組24的不佳位元標記在對應的對照記憶體位址位元組26，將不佳位元的位元位址寫到對應的對照記憶體位址位元組26中，若記憶體位元組22和修復位元組24沒有不佳位元，則將對應的對照記憶體位址位元組26寫入非記憶體位元組22的位元位址。若在步驟36中沒有檢測到不佳位元，則進入到步驟S40，結束記憶體20的修復。 In addition to the above-mentioned repair method, the present invention also provides a method for repairing the memory 20. Please also refer to the fourth figure to explain in detail how the present invention performs the repair of the memory 20. First, as shown in step S30, a set of memory 20 is provided, including a plurality of memory byte groups 22, which have M bits 222, such as 128-bit bits 222. As shown in step S32, for each memory byte group 22, a repair byte group 24 is added, which has N repair bits 242, for example, 32 repair bits 242 for repair, and the number of repair bits 242 is Less than the number of bits 222. As shown in step S34, for each memory byte 22 and repair byte 24, a set of control memory address byte 26 is provided, which has Q bits 262 for marking the memory byte 22 and repairing Bad bit address in byte 24, and 2 ^Q

M+N, the control memory address byte 26 of this embodiment can be one-time programmable memory (OTP), multiple-time programmable memory (MTP), NOR flash memory (NOR Flash) or They are Phase-Change Memory, Resistive Random Access Memory, and Magnetoresistive Random Access Memory, and the present invention is not limited thereto. As shown in step S36, it is checked whether all the memory byte 22 and repair byte 24 in the memory 20 and the control memory address byte 26 have bad bits. If bad bits are detected, Then go to the next step. As shown in step S38, the memory byte 22 with any bad bit is replaced by a non-bad repair bit from the self-repair byte 24 to the bad bit of the memory byte 22 to The repair of any bad bit in each memory byte group 22 in the memory 20 is completed, and the mark of the bad bit in the repair byte 24 is completed. In this embodiment, internal read, write, and disturbance ( disturb) and the disturbance of external temperature, magnetic field, and electric field to check whether each memory byte 22, repair byte 24, and control memory address byte 26 have bad bits. For example, first set the memory bit The bad bits of group 22 and repair tuple 24 are marked in the corresponding control memory address byte group 26, and the bit address of the bad bit is written into the corresponding control memory address byte 26, if If the memory byte 22 and the repair byte 24 have no bad bits, the corresponding control memory address byte 26 is written into the non-memory byte 22 bit address. If no bad bit is detected in step 36, the process proceeds to step S40 to end the repair of the memory 20.

The above-mentioned repaired memory byte and each repaired byte can also be used as data bits, and at the same time, it can also be used to provide check bits for correction bits to improve reliability during use. Each memory byte, each repair byte, and each control memory address byte can be used in combination with bit line and word line repair methods to repair bit line and word line defects, thereby simultaneously Can achieve excellent repair efficiency.

The present invention provides two different memory repair methods, which can improve the speed and accuracy of memory repair, and provide users with more innovative memory repair methods, no matter where they are applied in the future. Among these products, it will be more competitive.

The above-mentioned embodiments are only to illustrate the technical ideas and features of the present invention, and their purpose is to enable those who are familiar with the art to understand the content of the present invention and implement them accordingly. When they cannot be used to limit the patent scope of the present invention, That is, all equal changes or modifications made in accordance with the spirit of the present invention should still be covered by the patent scope of the present invention.

Claims (13)

A method for repairing a memory includes the following steps: providing a set of memory, where there are a plurality of memory byte groups with M bits, and M is a positive integer; for each memory byte, a repair bit is added Tuple, which has N repair bits for repair, N is a positive integer, and N is less than M; provide a set of comparisons that have the same or greater number of bits as the memory plus the repair byte Memory byte, the control memory byte is non-volatile memory (Non-Volatile Memory); and detecting all the memory bytes, the repair byte and the control memory byte in the memory Whether there is a bad bit in the memory: if not, the repair of the memory is ended; and if so, the memory byte and the repair byte that have any of the bad bits will correspond to the memory byte The number of the bad bits is replaced by the equivalent number of non-bad repair bits in the repair byte to all the bad bits in the memory byte to complete each A repair of the memory byte and a mark of the bad bit in the repair byte; wherein, first the memory byte and the control memory bit corresponding to the bad bit of the repair byte Mark, and mark the bad bit in the control memory byte. If the bit of the memory byte and the repair bit are detected as non-bad, but if the control memory bit If the bit is a bad bit, the bit of the memory byte and the repair bit are still regarded as bad bits. The marking method is the bit in the control memory byte corresponding to the bad bit. Yuan and the bad bit of the control memory byte group are written to a different memory state than the non-bad bit of the control memory. The memory repair method according to claim 1, wherein the control memory byte is one-time programmable memory (OTP), multi-time programmable memory (MTP) or NOR flash memory (NOR Flash). The memory repair method according to claim 1, wherein the control memory byte is a phase-change memory (Phase-Change Memory), a resistive random access memory (Resistive Random Access Memory) or a magnetoresistive type Random Access Memory (Magnetoresistive Random Access Memory). The method for repairing memory according to claim 1, wherein each of the memory byte, the repair byte and the set of control memory system is read, written, and disturbed by internal reading, writing, and disturbance, as well as external temperature, magnetic field, The disturbance of the electric field is used to detect whether there is the bad bit. The memory repair method according to claim 1, wherein after the repair of the group of memories, each bit and each repair bit are rearranged. The method for repairing memory as described in claim 1, wherein the repaired memory byte and each repaired byte are used for data bits, and can also be used for correction bits (Error-Correction Code, The parity bit used by ECC) is used to improve the reliability in use. The method for repairing memory as described in claim 1, wherein each of the memory byte, each of the repaired byte and each of the control memory byte can be repaired by using bit lines and word lines in combination The method repairs bit line level and word line level defects. A method for repairing a memory includes the following steps: providing a set of memory, where there are a plurality of memory byte groups with M bits, and M is a positive integer; for each memory byte, a repair bit is added A tuple, which has N repair bits for repair, N is a positive integer, and N is less than M; for each of the memory byte and the repair byte, a control memory address byte is provided, The control memory address byte is a non-volatile memory (Non-Volatile Memory), which has Q bits for marking the bad bit in the memory byte and the repair byte Address, and 2 ^Q

M+N; and detecting whether all the memory bytes, the repair bytes, and the control memory address bytes in the memory have bad bits: if not, the repair of the memory is ended; And if so, replace the memory byte with any one of the bad bits with a non-bad repair bit in the repair byte to the bad bit of the memory byte , In order to complete the repair of any one of the bad bits in each of the memory bytes in the memory and the mark of the bad bit in the repair bytes; wherein, first the memory byte and the The bad bit of the repair byte is marked in the corresponding control memory address byte, and the bit address of the bad bit is written into the corresponding control memory address byte. If the If there is no bad bit in the memory byte and the repair byte, then the corresponding control memory address byte is written into the non-memory byte address. The memory repair method according to claim 8, wherein the reference memory address byte is one-time programmable memory (OTP), multiple-time programmable memory (MTP) or NOR flash memory (NOR Flash). The memory repair method according to claim 8, wherein the control memory address byte is a phase-change memory (Phase-Change Memory), a resistive random access memory (Resistive Random Access Memory) or a magnetic Resistive Random Access Memory (Magnetoresistive Random Access Memory). The method for repairing memory according to claim 8, wherein the repaired memory byte And each repair bit group is used for data bits, and can also be used for parity bits (Error-Correction Code, ECC) used to improve reliability in use Sex. The memory repair method according to claim 8, wherein each of the memory bytes, each of the repair bytes, and each of the control memory address bytes can be used in combination with bit lines and characters The line repair method repairs bit line level and word line level defects. The method for repairing a memory according to claim 8, wherein each of the memory byte, the repair byte and the set of the control memory address byte is performed by internal reading, writing and disturbance (disturb) and The disturbance of external temperature, magnetic field or electric field is used to detect whether there is such a bad bit.

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