TWI622779B - Testing device and waveform generating method - Google Patents

Abstract

A test device is used to output N test waveforms. Each test waveform has M time intervals. The test device includes a processing circuit, a first memory, a second memory, and a waveform generating circuit. The processing circuit outputs a control signal according to the demand instruction. The first memory stores a waveform lookup table. The waveform lookup table contains K1 waveform groups, each waveform group containing N unit waveforms. N, M, and K1 are positive integers and K1 is less than M. The second memory stores a first timing lookup table. The first timing lookup table includes K2 timing groups, and each timing group includes N unit timings. K2 is a positive integer and K2 is less than M. The waveform generation circuit generates the N test waveforms based on the waveform information and the timing information.

Description

Test device and waveform generation method

The content of the embodiments described in the present disclosure relates to a testing technique, and in particular to a testing apparatus and a waveform generating method.

In the testing of integrated circuits (ICs), the test device (device under-test; DUT) is usually tested. In the prior art, the test device can have a plurality of test pins to simultaneously test a plurality of devices under test. As the number of test pins increases, the test set will require more hardware resources to store the corresponding test signals (eg, test waveforms). It can be seen that the prior art obviously has inconveniences and defects, and needs to be improved.

In view of this, the present disclosure proposes a test apparatus and a waveform generation method for solving the problems described in the prior art.

One embodiment of the present disclosure is directed to a test device. The test device is used to simultaneously output N test waveforms. Each test waveform has M timing intervals. The test device includes a processing circuit, a first memory a body, a second memory, and a waveform generating circuit. The processing circuit is configured to output a control signal according to a demand instruction. The first memory is used to store a waveform lookup table. The waveform lookup table contains K1 waveform groups. Each waveform group contains N unit waveforms. N, M, and K1 are positive integers and K1 is less than M. The second memory is used to store a first timing lookup table. The first timing lookup table contains K2 timing groups. Each timing group contains N unit timings. K2 is a positive integer and K2 is less than M. The waveform generating circuit is configured to generate the test waveforms based on a waveform information and a timing information. Waveform information and timing information are generated based on the control signal call waveform lookup table and the first timing lookup table, respectively.

One embodiment of the present disclosure is directed to a waveform generating method. The method for generating a waveform includes: outputting a control signal according to a demand command by a processing circuit of a test device; storing a waveform lookup table by a first memory of the test device; and storing a second memory by the test device a first timing lookup table; and a waveform generation circuit by the test device generates N test waveforms based on a waveform information and a timing information. Waveform information and timing information are generated based on the control signal call waveform lookup table and the first timing lookup table, respectively. The waveform lookup table contains K1 waveform groups. Each waveform group contains N unit waveforms. The first timing lookup table contains K2 timing groups. Each timing group contains N unit timings. Each test waveform has M timing intervals. N, M, K1, and K2 are positive integers, and K1 and K2 are smaller than M.

In summary, one or more lookup tables are created in the test device to generate a plurality of test waveforms using the one or more lookup tables. This saves storage space and improves test efficiency.

100, 800‧‧‧ test system

120, 820‧‧‧ test equipment

121, 821‧‧‧ processing circuit

122, 123, 124, 125, 126, 821, 822, 823, 824, 825, 826, 827, 828‧‧‧ memory

829‧‧‧Sequence Merging Circuit

130, 830‧‧‧ waveform generation circuit

140‧‧‧Device under test

D1‧‧‧ Demand Directive

C1‧‧‧ control signal

V1, V2, V3, V4, V5, V6‧‧‧ pointing signals

WP‧‧‧ Waveform Group Information

TP‧‧‧ Timing Group Arrangement Information

ETP‧‧‧Edge group arrangement information

RTP‧‧‧cycle group arrangement information

WLUT‧‧‧ Waveform Lookup Table

TLUT‧‧‧Timing Lookup Table

ETLUT‧‧‧Edge Lookup Table

RLUT‧‧‧ cycle lookup table

WF‧‧‧ waveform collection

TF‧‧‧ timing set

ETF‧‧‧Edge Set

RTF‧‧‧ cycle collection

WO‧‧‧ Waveform Information

TO‧‧‧ Timing Information

ET‧‧‧ Edge Information

RT‧‧‧cycle information

OUT, OUT[1], OUT[2]‧‧‧ test waveforms

RAT‧‧ cycle

RTWC[1], RTWC[2], RTWC[3], RTWC[4]‧‧‧ unit waveforms

600‧‧‧ Waveform generation method

700‧‧‧ Waveform lookup table generation method

S602, S604, S606, S608, S702, S704, S706, S708, S710‧‧ steps

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a test system according to some embodiments of the present disclosure; 2 is a schematic diagram of two test waveforms according to some embodiments of the present disclosure; FIG. 3 is a schematic diagram of a waveform set and a timing set according to some embodiments of the present disclosure; FIG. 4 is a schematic diagram according to the disclosure. FIG. 5 is a schematic diagram of a waveform lookup table according to some embodiments of the present disclosure; FIG. 6 is a waveform generation method according to some embodiments of the present disclosure. FIG. 7 is a flowchart of a method for generating a waveform table according to some embodiments of the present disclosure; and FIG. 8 is a schematic diagram of a test system according to some embodiments of the present disclosure.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the disclosure The description is not intended to limit the order in which it is performed, and any device that is re-combined by the elements that produces equal functionality is within the scope of the disclosure. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For the sake of understanding, the same or similar elements in the following description will be denoted by the same reference numerals.

Please refer to Figure 1. 1 is a schematic diagram of a test system 100 in accordance with some embodiments of the present disclosure. In some embodiments, test system 100 includes test device 120 and a plurality of devices 140 to be tested. The testing device 120 is used to test the devices 140 to be tested.

In some embodiments, test device 120 has N test pins. The test device 120 simultaneously outputs N test waveforms OUT through N test pins to test N test devices 140. As in the example of Figure 1, the test device 120 has two test pins. Each test pin is coupled to a device 140 to be tested. The test device 120 simultaneously outputs the test waveforms OUT[1] and OUT[2]. The test waveform OUT[1] is output to the first device under test 140 through the first test pin, and the test waveform OUT[2] is output to the second device under test 140 through the second test pin.

In some embodiments, each device under test 140 includes at least one circuit to be tested. Various circuits for implementing the circuit under test are within the scope of the present disclosure.

In some embodiments, test device 120 includes processing circuitry 121, memory 122, 123, 124, 125, and 126, and waveform generation circuitry 130. The processing circuit 121 is coupled to the memory 122. The memory 122 is coupled to the memory 123 and the memory 125. The memory 123 is coupled to the memory 124. Remember The memory 125 is coupled to the memory 126. The memory 124 and the memory 126 are coupled to the waveform generating circuit 130. The waveform generating circuit 130 is coupled to the devices 140 to be tested.

In some embodiments, processing circuit 121 is a central processing unit (CPU). Various components that enable processing circuitry 121 are within the scope of the present disclosure. In some embodiments, the processing circuit 121 is configured to receive the demand instruction D1 and generate the control signal C1 according to the demand instruction D1. In some embodiments, demand instruction D1 includes the number of test waveforms required, the waveform requirements of the test waveform, or various other requirements associated with the test waveform.

In some embodiments, the memory 122 is a control pattern memory (CPM). The memory 122 is configured to store the waveform group arrangement information WP and the timing group arrangement information TP. In some embodiments, the memory 122 is configured to receive the control signal C1, and execute the waveform group arrangement information WP according to the control signal C1 and output the first pointing signal V1. The memory 122 is further configured to execute the timing group arrangement information TP according to the control signal C1 and output the third pointing signal V3. Details of the waveform group arrangement information WP and the timing group arrangement information TP will be described in detail later.

In some embodiments, the memory 123 is used to store the waveform lookup table WLUT, and the memory 125 is used to store the timing lookup table TLUT. Details of the waveform lookup table WLUT and the timing lookup table TLUT will be described in detail later.

In some embodiments, the memory 123 is configured to output the second pointing signal V2 according to the first pointing signal V1 and the waveform lookup table WLUT. In some embodiments, the memory 125 is configured to output the fourth pointing signal V4 according to the third pointing signal V3 and the timing lookup table TLUT.

In some embodiments, memory 124 is a real-time waveform control (RTWC) memory. The memory 124 is used to store the waveform set WF. In some embodiments, the memory 124 is configured to receive the second pointing signal V2 and output the waveform information WO according to the second pointing signal V2 and the waveform set WF. In some embodiments, the waveform information WO is used to record a plurality of logical values of each test waveform.

In some embodiments, memory 126 is a real-time timing control (RTTC) memory. The memory 126 is used to store the timing set TF. In some embodiments, the memory 126 is configured to receive the fourth pointing signal V4, and output the timing information TO according to the fourth pointing signal V4 and the timing set TF. In some embodiments, the timing information TO is used to record a plurality of rising/falling edges in each test waveform. In some embodiments, the timing information TO is used to record the strobe time of each bit in a test waveform.

In some embodiments, the waveform generating circuit 130 is configured to receive the waveform information WO and the timing information TO, and generate the test waveforms OUT[1] and OUT[2] according to the waveform information WO and the timing information TO. As described above, the waveform information WO includes the logic values of the respective test waveforms, and the timing information TO includes the rising/falling edges of the test waveforms, the comparison times, and the period RATs. Accordingly, the waveform generation circuit 130 can establish the waveforms to be tested according to the waveform information WO and the timing information TO. Then, the waveform generating circuit 130 outputs the test waveforms OUT[1] and OUT[2] to the test devices 140 through the test pins of the test device 120.

The implementation of the above test device 120 is for example purposes only. Various implementations of the test device 120 are within the scope of the present disclosure.

Please refer to Figure 2 and Figure 3. 2 is a schematic diagram of two test waveforms OUT[1] and OUT[2] according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram of a waveform set WF and a timing set TF according to some embodiments of the present disclosure.

In the example of Figure 2, the test waveform OUT[1] or OUT[2] has four time intervals. Each time interval corresponds to a unit waveform. For example, the four timing intervals of the test waveform OUT[1] correspond to the unit waveform RTWC[1], the unit waveform RTWC[2], the unit waveform RTWC[2], and the unit waveform RTWC[2], respectively. The four timing intervals of the test waveform OUT[2] correspond to the unit waveform RTWC[3], the unit waveform RTWC[4], the unit waveform RTWC[3], and the unit waveform RTWC[4], respectively.

In some embodiments, the unit waveform RTWC[1] corresponds to a logical value of "1" and the rising/falling edge of the unit waveform RTWC[1] is located at 5 nanoseconds and 65 nanoseconds. In some embodiments, the unit waveform RTWC[2] corresponds to "0". In some embodiments, the unit waveform RTWC[3] corresponds to a logical value of "1" and the alignment time of the unit waveform RTWC[3] is at 50 nanoseconds. In some embodiments, the unit waveform RTWC[4] corresponds to "0".

In some embodiments, the logic values of the test waveforms OUT[1] and OUT[2] are recorded in the waveform set WF of FIG. In some embodiments, the period RAT, rising/falling edge, and comparison time of the test waveforms OUT[1] and OUT[2] are recorded in the timing set TF.

Implementation of the above waveform set WF and timing set TF For the purposes of example only, various implementations that implement waveform set WF and timing set TF are within the scope of the present disclosure.

Please refer to Figure 4. FIG. 4 is a schematic diagram of waveform group arrangement information WP according to some embodiments of the present disclosure.

Assuming that the test device 120 has N (eg, 512) test pins, each test waveform has M (eg, 32 Mega) time intervals, and the test device 120 can generate a K1 group (eg, 4096 groups) waveform group (eg, :LUT[1]~LUT[4096]). In some embodiments, N, M, K1 are positive integers. In some embodiments, K1 is less than M.

As shown in FIG. 4, the waveform group arrangement information WP is used to record M waveform groups corresponding to M time intervals of the N test waveforms. For example, the waveform group arrangement information WP includes a waveform group LUT[1], a waveform group LUT[8], a waveform group LUT[2], a waveform group LUT[4096], and a waveform group LUT[15]. The waveform group LUT[1] corresponds to the first time interval of the N test waveforms, the waveform group LUT[8] corresponds to the second time interval of the N test waveforms, and so on. The waveform group LUT[15] corresponds to the Mth time interval of the N test waveforms. In some embodiments, the waveform group arrangement information WP is stored in the memory 122 according to user requirements. In other words, the user can set the test device 120 according to the requirements to generate the demand command D1. The processing circuit 121 outputs the control signal C1 according to the demand command D1, so that the memory 122 executes the waveform group arrangement information WP and the timing group arrangement information TP.

Please refer to Figure 5. FIG. 5 is a schematic diagram of a waveform lookup table WLUT, in accordance with some embodiments of the present disclosure. In some embodiments, each waveform group includes N unit waveforms. In the example of Figure 5, the waveform group LUT[1] contains N (for example: 512) unit waveforms, which are unit waveform RTWC[20], unit waveform RTWC[5], unit waveform RTWC[32]...unit waveform RTWC[19] . The above N unit waveforms respectively correspond to N test pins of the test device 120. That is to say, the first timing interval of the test waveform output by the first test pin is the waveform group RTWC[20], and the first timing interval of the test waveform output by the second test pin is the waveform group RTWC. [5], and so on. The first time interval of the test waveform output by the 512th test pin is the waveform group RTWC[19].

As described above, the memory 122 will execute the waveform group arrangement information WP (for example, FIG. 4) according to the control signal C1 and output the first pointing signal V1. In some embodiments, the first pointing signal V1 carries the waveform group arrangement information WP to call the waveform lookup table WLUT of FIG. 5 and sequentially points to the waveform group LUT[1] and the waveform group LUT[8] in the waveform lookup table WLUT. ], waveform group LUT[2]... waveform group LUT[4096] and waveform group LUT[15]. Then, the memory 123 outputs the second pointing signal V2 according to the first pointing signal V1 and the waveform lookup table WLUT. In some embodiments, the second pointing signal V2 carries the set of waveforms to which the above is directed. Next, the memory 124 searches the waveform set WF (for example, FIG. 3) according to the second pointing signal V2 to output the waveform information WO of the corresponding waveform group arrangement information WP to the waveform generating circuit 130.

In some embodiments, the periodic RAT, rise/fall edges, and alignment time of the test waveforms can also be implemented by similar concepts. For example, the memory 122 executes the timing group arrangement information TP according to the control signal C1 and outputs the third pointing signal V3. In some embodiments, the third pointing The number V3 carries the timing group arrangement information TP to call the timing lookup table TLUT and sequentially points to the timing group in the timing lookup table TLUT. In some embodiments, the timing lookup table TLUT includes K2 timing groups, and each timing group includes N unit timings. In some embodiments, K2 is a positive integer and less than M.

Then, the memory 125 outputs the fourth pointing signal V4 according to the third pointing signal V3 and the timing lookup table TLUT. In some embodiments, the fourth pointing signal V4 carries the timing group to which the above is directed. Next, the memory 126 searches the timing set TF according to the fourth pointing signal V4 to output the timing information TO of the corresponding timing group arrangement information TP to the waveform generating circuit 130. Thus, the waveform generating circuit 130 can generate the N test waveforms according to the waveform information WO and the timing information TO.

By establishing the waveform lookup table WLUT, the same waveform group can be prevented from being repeatedly stored. According to this, the effect of saving storage space can be achieved. In some embodiments, the required memory space can be greatly reduced by the waveform lookup table WLUT and the timing lookup table TLUT. For example, assume that each waveform group requires 12 bits for storage, and each unit waveform requires 5 bits for storage. In conventional practice, the storage space requires at least about 80G (32M x 512 x 5) bits. The waveform lookup table WLUT and the waveform group arrangement information WP only need about 400M (4096 × 512 × 5 + 32M × 12) bits.

In some embodiments, the waveform lookup table WLUT can be built using multiple sub-waveform lookup tables (sub-WLUTs). For example, a waveform lookup table WLUT having a width of 8 bits is cut into a first waveform lookup table and a second waveform lookup table having a width of 4 bits, respectively. Compared to using only one set of waveforms When the lookup table WLUT encounters a new waveform requirement, it needs to rewrite the 8-bit data. In this embodiment, when the waveform change is concentrated on the first waveform lookup table, only the first waveform lookup table needs to be written, and the reuse is repeated. The second waveform lookup table. This saves storage space and increases flexibility.

Please refer to Figure 6. FIG. 6 is a flow diagram of a waveform generation method 600, in accordance with some embodiments of the present disclosure. In some embodiments, waveform generation method 600 includes step S602, step S604, step S606, and step S608.

In some embodiments, waveform generation method 600 is applied to test device 120 of FIG. In order to understand the disclosure in a preferred manner, the waveform generation method 600 will be discussed in conjunction with the test apparatus 120 of FIG. 1, but the disclosure is not limited thereto.

In step S602, the processing circuit 121 of the testing device 120 outputs the control signal C1 according to the demand command D1. In some embodiments, the demand instruction D1 contains various requirements for the test waveform (eg, the number of waveforms). In some embodiments, the memory 122 performs the waveform group arrangement information WP and the timing group arrangement information TP according to the control signal C1, and outputs the first pointing signal V1 and the third pointing signal V3.

In step S604, the test device 120 generates waveform information WO. In some embodiments, the memory 123 outputs the second pointing signal V2 according to the first pointing signal V1 and the waveform lookup table WLUT. In some embodiments, the memory 124 outputs the waveform information WO according to the second pointing signal V2 and the waveform set WF.

In step S606, the testing device 120 generates timing information. TO. In some embodiments, the memory 125 outputs the fourth pointing signal V4 according to the third pointing signal V3 and the timing lookup table TLUT. In some embodiments, the memory 126 outputs the timing information TO according to the fourth pointing signal V4 and the timing set TF.

In step S608, the waveform generation circuit 130 of the test apparatus 120 generates the complex test waveform OUT based on the waveform information WO and the timing information TO. In some embodiments, the waveform information WO and the timing information TO are generated based on the control signal C1 call waveform lookup table WLUT and the timing lookup table TLUT, respectively.

The description of the waveform generation method 600 described above includes exemplary operations, but the operations of the waveform generation method 600 need not be performed in the order shown. The order of the operations of the waveform generation method 600 can be changed, or the operations can be performed simultaneously, partially simultaneously, or partially omitted, as appropriate, within the spirit and scope of the embodiments of the present disclosure.

Please refer to Figure 7. FIG. 7 is a flow diagram of a waveform lookup table generation method 700, in accordance with some embodiments of the present disclosure. In some embodiments, waveform lookup table generation method 700 includes step S702, step S704, step S706, step S708, and step S710. In some embodiments, the steps described above are performed by processing circuitry 121 or other various control elements.

In step S702, the processing circuit 121 combines the N unit waveforms corresponding to the N test pins to form a waveform group. In the example of FIG. 5, the processing circuit 121 combines the unit waveform RTWC[20], the unit waveform RTWC[5], the unit waveform RTWC[32], the unit waveform RTWC[19] into one waveform group. .

In step S704, the processing circuit 121 determines whether or not the waveform group combined by step S702 exists in the waveform lookup table WLUT in the memory 123. In the example of Fig. 5, the waveform group (for example, LUT[1]) exists in the waveform lookup table WLUT. Therefore, the process proceeds to step S706.

In step S706, the processing circuit 121 finds the location of the waveform group in the waveform lookup table WLUT. In the example of Figure 5, the position of the waveform group is [1].

In step S708, the processing circuit 121 returns the value of the position of the waveform group. In the example of Fig. 5, the position of the waveform group has a value of 1.

Returning to step S704, if the processing circuit 121 determines that the waveform group combined by step S702 does not exist in the waveform lookup table WLUT in the memory 123, the flow proceeds to step S710.

In step S710, the processing circuit 121 adds the waveform group combined by step S702 to the waveform lookup table WLUT. Next, proceeding to step S708, the processing circuit 121 returns the value of the position of the waveform group. As such, the waveform lookup table WLUT can be created. In some embodiments, the timing lookup table TLUT can be generated by a method similar to the waveform lookup table generation method 700.

The description of the waveform lookup table generation method 700 described above includes exemplary operations, but the operations of the waveform lookup table generation method 700 need not be performed in the order shown. The order of the operations of the waveform lookup table generation method 700 can be changed, or the operations can be performed simultaneously, partially simultaneously, or partially omitted, where appropriate, in the practice of the disclosed embodiments. God and scope.

Compared to the conventional method, when the test device wants to generate a new test waveform and the new test waveform is not previously stored in the test device, it takes time to load information of the new test waveform into the test device. This will lengthen the time the waveform is generated. With the waveform lookup table generation method 700, all waveform groups can be stored in the waveform lookup table WLUT in advance (as previously described, the storage space required for the waveform lookup table WLUT is smaller than conventional methods). As such, when the test device 120 is to generate a new test waveform, the test device 120 can find a corresponding waveform group from the waveform lookup table WLUT. That is to say, the test device 120 does not need to reload the information of the new test waveform. According to this, the waveform generation time of the test apparatus 120 can be shortened and the test efficiency of the test apparatus 120 can be improved.

Please refer to Figure 8. FIG. 8 is a schematic diagram of a test system 800 in accordance with some embodiments of the present disclosure. For the purpose of easy understanding, elements in Fig. 8 that are similar to those in Fig. 1 will be assigned the same reference numerals.

For the sake of simplicity, the following description will only be made regarding the difference between the test system 800 of FIG. 8 and the test system 100 of FIG. For the rest, please refer to the foregoing embodiment, and details are not described herein again.

Compared to the test apparatus 120 of FIG. 1, the test apparatus 820 of FIG. 8 includes a processing circuit 821, memories 822, 823, 824, 825, 826, 827, and 838, a timing combining circuit 829, and a waveform generating circuit 830.

In some embodiments, the processing circuit 821 is configured to receive the demand instruction D1 and generate the control signal C1 according to the demand instruction D1. In some embodiments, the memory 822 is used to store the waveform group arrangement information WP and the edge group row. Column information ETP and cycle group arrangement information RTP.

In some embodiments, the timing group arrangement information TP of FIG. 1 can be divided into an edge group arrangement information ETP and a periodic group arrangement information RTP. The edge group arrangement information ETP corresponds to the rising/falling edge of the plurality of test waveforms and the comparison time. The periodic group arrangement information RTP corresponds to a period RAT of a plurality of test waveforms.

In some embodiments, the memory 822 is configured to receive the control signal C1, and execute the waveform group arrangement information WP according to the control signal C1 and output the first pointing signal V1. In some embodiments, the first pointing signal V1 carries the waveform group arrangement information WP to call the waveform lookup table WLUT and sequentially points to the waveform group in the waveform lookup table WLUT. Next, the memory 823 outputs the second pointing signal V2 according to the first pointing signal V1 and the waveform lookup table WLUT. In some embodiments, the second pointing signal V2 carries the set of waveforms to which the above is directed. Next, the memory 824 searches the waveform set WF according to the second pointing signal V2 to output the waveform information WO of the corresponding waveform group arrangement information WP to the waveform generating circuit 830.

In some embodiments, the memory 822 is further configured to execute the edge group arrangement information ETP according to the control signal C1 and output the third pointing signal V3. In some embodiments, the third pointing signal V3 carries the edge group arrangement information ETP to call the edge lookup table ETLUT (first timing lookup table) and sequentially points to the edge group in the edge lookup table ETLUT. In some embodiments, the edge lookup table ETLUT contains K2 edge groups, and each edge group includes N unit edges. In some embodiments, K2 is a positive integer and less than M. Next, the memory 825 is based on the third pointing signal V3 and the edge lookup table. The ETLUT outputs a fourth pointing signal V4. In some embodiments, the fourth pointing signal V4 carries the edge group to which the above is directed. Next, the memory 826 searches the edge set ETF according to the fourth pointing signal V4 to output the edge information ET of the corresponding edge group arrangement information ETP to the timing combining circuit 829.

In some embodiments, the memory 822 is further configured to execute the periodic group arrangement information RTP according to the control signal C1 and output the fifth pointing signal V5. In some embodiments, the fifth pointing signal V5 carries the periodic group arrangement information RTP to the call cycle lookup table RTLUT (second timing lookup table) and sequentially points to the periodic group in the periodic lookup table RTLUT. In some embodiments, the periodic lookup table RTLUT contains K3 period groups, and each period group includes N unit periods. In some embodiments, K3 is a positive integer and less than M. Next, the memory 827 outputs the sixth pointing signal V6 according to the fifth pointing signal V5 and the periodic lookup table RTLUT. In some embodiments, the sixth pointing signal V6 carries the periodic group to which the above is directed. Then, the memory 828 searches the periodic set RTF according to the sixth pointing signal V6 to output the periodic information RT of the corresponding periodic group arrangement information RTP to the timing combining circuit 829.

In some embodiments, the edge lookup table ETLUT and the periodic lookup table RTLUT may be generated by a method similar to the waveform lookup table generation method 700.

In some embodiments, the timing combining circuit 829 generates the timing information TO based on the edge information ET and the period information RT. For example, the edge information ET includes the rising/falling edges of the respective test waveforms and the comparison times. The period information RT contains the period RATs of the respective test waveforms. Accordingly, the timing information TO includes the rising/falling edges of each test waveform, The comparison times and the period RATs.

In some embodiments, the waveform information WO includes the logic values or voltage levels of the respective test waveforms. Accordingly, the waveform generation circuit 830 can establish the waveforms to be tested according to the waveform information WO and the timing information TO. Then, the waveform generating circuit 830 outputs the test waveforms OUT[1] and OUT[2] to the test devices 140 through the test pins of the test device 820.

The implementation of the test device 820 described above is for illustrative purposes only, and various implementations of the test device 820 are within the scope of the present disclosure.

In summary, one or more lookup tables are created in the test device to generate a plurality of test waveforms using the one or more lookup tables. This saves storage space and improves test efficiency.

The present disclosure has been disclosed in the above embodiments, and is not intended to limit the present disclosure. Any one of ordinary skill in the art can make various changes and refinements without departing from the spirit and scope of the present disclosure. The scope of protection is subject to the definition of the scope of the patent application.

Claims (10)

a test device for simultaneously outputting N test waveforms, each of the N test waveforms having M time intervals, the test device comprising: a processing circuit for outputting a control signal according to a demand command; a memory for storing a waveform lookup table, wherein the waveform lookup table comprises K1 waveform groups, each waveform group comprising N unit waveforms, wherein N, M, K1 are positive integers and K1 is less than M; a second memory a first timing lookup table, wherein the first timing lookup table includes K2 timing groups, each timing group includes N unit timings, where K2 is a positive integer and K2 is less than M; and a waveform is generated The circuit is configured to generate the N test waveforms based on a waveform information and a timing information, wherein the waveform information and the timing information are generated based on the control signal calling the waveform lookup table and the first timing lookup table, respectively. The test device of claim 1, further comprising: a third memory for outputting a first pointing signal according to the control signal, so that the first memory outputs a second pointing based on the first pointing signal And a fourth memory for outputting the waveform information according to the second pointing signal. The test device of claim 2, wherein the third memory is configured to store a waveform group arrangement information, and the waveform group arranges the information packet There are M waveform groups, and the M waveform groups respectively correspond to M time intervals. The test device of claim 1, further comprising: a third memory for outputting a third pointing signal according to the control signal, so that the second memory outputs a fourth pointing based on the third pointing signal And a fourth memory for outputting the timing information according to the fourth pointing signal. The test device of claim 1, further comprising: a third memory for outputting a first pointing signal, a third pointing signal, and a fifth pointing signal according to the control signal, so that the first memory The body outputs a second pointing signal based on the first pointing signal; a fourth memory for outputting the waveform information according to the second pointing signal; a fifth memory, wherein the second memory is used according to the first The third pointing signal outputs a fourth pointing signal, so that the fifth memory outputs an edge information based on the fourth pointing signal; and a sixth memory for outputting a sixth pointing signal according to the fifth pointing signal; a seventh memory for outputting a period of information period information according to the sixth pointing signal; and a timing combining circuit for outputting the timing information according to the edge information and the period information, The sixth memory is configured to store a second timing lookup table, where the second timing lookup table includes K3 timing groups, each timing group includes N unit timings, where K3 is a positive integer and K3 is less than M, where The edge information and the periodic information are generated based on the control signal calling the first timing lookup table and the second timing lookup table, respectively. A waveform generating method includes: outputting, by a processing circuit of a testing device, a control signal according to a demand command; wherein a first memory of the testing device stores a waveform lookup table, wherein the waveform lookup table includes K1 a waveform group, each waveform group includes N unit waveforms; a second memory of the testing device stores a first timing lookup table, wherein the first timing lookup table includes K2 timing groups, and each timing group includes N unit timings; and a waveform generating circuit of the testing device generates N test waveforms based on a waveform information and a timing information, wherein each of the N test waveforms has M time intervals, N, M, K1 and K2 are positive integers, and K1 and K2 are smaller than M, wherein the waveform information and the timing information are generated based on the control signal calling the waveform lookup table and the first timing lookup table, respectively. The method of generating a waveform according to claim 6, further comprising: outputting, by the third memory of the testing device, a first pointing signal according to the control signal, so that the first memory is based on the first pointing signal And outputting a second pointing signal; and outputting the waveform information according to the second pointing signal by a fourth memory of the testing device. The waveform generating method of claim 7, further comprising: storing, by the third memory, a waveform group arrangement information, wherein the waveform group arrangement information comprises M waveform groups, and the M waveform groups respectively correspond to M Time interval. The method of generating a waveform according to claim 6, further comprising: outputting, by the third memory of the test device, a third pointing signal according to the control signal, so that the second memory is output based on the third pointing signal a fourth pointing signal; and a fourth memory of the testing device outputs the timing information according to the fourth pointing signal. The method of generating a waveform according to claim 6, further comprising: outputting, by the third memory of the test device, a first pointing signal, a third pointing signal, and a fifth pointing signal according to the control signal, so that The first memory outputs a second pointing signal based on the first pointing signal; the fourth memory of the testing device outputs the waveform information according to the second pointing signal; and the second memory is according to the second memory Three-point signal output, a fourth finger a signal to enable a fifth memory of the test device to output an edge information based on the fourth pointing signal; and a sixth memory of the testing device outputs a sixth pointing signal according to the fifth pointing signal to And outputting, by the timing combining circuit of the testing device, the timing information according to the edge information and the periodic information, wherein the sixth memory is outputted by the seventh memory of the testing device; The second timing lookup table includes K3 timing groups, each timing group includes N unit timings, where K3 is a positive integer and K3 is less than M, wherein the edge information and the period The information is generated based on the control signal calling the first timing lookup table and the second timing lookup table respectively.