JP2004020503A - Semiconductor testing device, inspection method of semiconductor device or manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To materialize miniaturization and a low cost of a semiconductor testing device by small capacity programmable scrambler reducing the capacity of a scramble memory by enabling address conversion into an arbitrary address. <P>SOLUTION: In the semiconductor testing device, an algorithmic pattern generator has an address generation part and a scrambler, which has a plurality of the scramble memory. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor test apparatus, an inspection method of a semiconductor device, and a manufacturing method.
[0002]
[Prior art]
2. Description of the Related Art In recent years, high-speed and high-integration memories such as DRAMs have been developed, and SDRAMs (synchronous DRAMs), which perform a write / read operation to and from a memory in synchronization with a clock, have become mainstream. Recently, there is a DDR (Double Data Rate) SDRAM that outputs data in synchronization with both a rising edge and a falling edge of a clock. As a result, the data transfer rate is doubled without increasing the frequency of the clock, and higher-speed operation than the current 266 Mbps is possible.
[0003]
In high integration, large-capacity memories of 256 Mbytes, 512 Mbits to gigabits are becoming mainstream due to the characteristics of DRAMs using only a single transistor for a memory array.
[0004]
Another important factor in addition to high speed and high integration is the low cost of the memory. The market competition for memory is in a state of dead heat, and each company is focusing on lowering the price of memory.
[0005]
In a semiconductor test apparatus for testing these memories, there is a demand for a high-speed and high-integration memory and a reduction in test price. In order to reduce the test price, it is essential to reduce the price of semiconductor test equipment for testing memory. For the low cost of test equipment, it is most necessary to increase the integration of the LSI that constitutes the memory test equipment and reduce the size of the test equipment. It is valid.
[0006]
In testing a memory such as a DRAM, write "1" or "0" data to an arbitrary address in the memory, read the data from that address, and compare it with the written data to check if the memory is normal I do.
[0007]
At this time, as shown in FIG. 14 (as apparent from comparing the hexadecimal row address of the input address table of FIG. 14 with the hexadecimal row address of the output address), the semiconductor device is incorporated in a memory, for example, a memory. Row addresses (row addresses created by a memory circuit designer) are often not arranged in order from the top of the memory. This is because the memory circuit designer designs the memory according to the function arrangement and the like.
[0008]
For example, in FIG. 14, in order to inspect the address of the third row of a 4-bit memory (having 0 to 15 rows (F rows)), the semiconductor inspection (test) apparatus is required to execute 3 (0011 in the 4-bit binary system). ), And the test program at the address of the third row is given to the memory, the program of the tenth row (the A-th row) corresponds to the third row of the memory to be tested. Can not be inspected.
[0009]
Therefore, it is necessary to make the row address input at the time of inspection correspond to the row address stored in the memory (this is called address conversion). This address conversion is indispensable because the circuit design differs for each memory if the memory type or product is different. Since a semiconductor test device for testing a memory needs to test a wide variety of memories, scrambling, which is address conversion (conversion of a common logical address described in a test pattern into a physical address for each product) of the semiconductor test device, is performed. A functioning pattern generator is required.
[0010]
In this specification, a row address actually assigned from the upper stage of the memory is called a logical address. Therefore, the logical address is common to all the semiconductor devices (memory). On the other hand, the row address built in the memory is called a physical address. Therefore, a physical address (physical address) has a unique address for each memory maker and each memory product depending on the arrangement of memory cells in memory development.
[0011]
2. Description of the Related Art As a conventional pattern generator, there is a pattern generator described in Japanese Patent Application Laid-Open Publication No. 8-94723, “Memory Semiconductor Test Apparatus”. Hereinafter, this technique will be described.
[0012]
FIG. 12 shows a conventional pattern generator having a scramble function. In a conventional pattern generator, address conversion is performed using a scrambled memory. The pattern generator shown in FIG. 12 includes an algorithmic pattern generator (ALPG) 15 for generating a regular logical address according to the test order, test data to be written in a memory to be tested, and a control signal. , A scramble memory (SCRAM: Scramble Random Access Memory) 40 for performing address conversion, and a memory controller 12 for controlling writing / reading of the scramble memory 40.
[0013]
In the algorithmic pattern generator 15, a logical address common to the memories is output from the address generator 14 and input to the scrambler 13. The scrambler 13 inputs n bits of the logical address input by the memory controller 12 to a scramble memory (SCRAM) 40 as a memory address. Before starting the test, the physical address of the memory to be tested is written in advance in the data of the scramble memory 40, and the data of the memory address corresponding to the logical address is read. To a different physical address. The converted physical address is input to the device under test 16 to be tested and is tested. Therefore, by rewriting the data of the scramble memory 40 for each memory to be tested, various memories can be tested, and various kinds of memories can be supported by software without changing hardware.
[0014]
In addition, as shown in FIG. 13, there is a conventional example in which the scramble memory 40 is not used and only the scramble logic is used. In this case, there is an advantage that the hardware scale of the scrambler can be reduced.
[Problem to be solved]
However, in the prior art disclosed in Japanese Patent Application No. 8-94723, a scramble memory is provided outside the pattern generator, and pins for interfacing with the external scramble memory are required. Therefore, there is a problem that a mounting area for an external scramble memory or the like is required, and the semiconductor test apparatus cannot be miniaturized.
[0015]
Further, with the recent increase in memory capacity, the number of addresses of the memory to be tested has increased, and the capacity of the scramble memory (SCRAM) 40 has to be increased. For example, when testing a memory having an address of n = 16 bits, in order to convert a 16-bit address into an arbitrary address, a scrambling memory 40 of 64 k (2 ＾ 16 = 65536 depth) × 16-bit width is used. is necessary.
[0016]
As described above, when the capacity of the scramble memory is increased, the price of the semiconductor test apparatus rises due to the rise in the price of parts (scramble memory and the like). This leads to an increase in the price of the semiconductor device due to an increase in the test cost.
[0017]
Furthermore, the increase in the capacity (depth) of the scrambled memory causes a problem that the time for writing into the scrambled memory before the test starts increases.
[0018]
Further, the conventional technique shown in FIG. 13 has an advantage that the hardware scale of the scrambler is small, but conversely, since a scramble logic for performing a unique scramble operation is provided for each memory product, it is compatible with various types of memories. Can not. Further, since it is necessary to change the hardware for each product of the memory to be the device under test, there is a problem that the number of steps of hardware development and operation confirmation increases. This leads to an increase in the manufacturing cost of the semiconductor device.
[0019]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor inspection apparatus capable of inspecting a memory under test using a small capacity or a scramble memory whose capacity is not as large as the memory under test.
[0020]
It is another object of the present invention to provide a semiconductor test apparatus in which a scramble memory is built in a pattern generator.
[0021]
Another object of the present invention is to provide a low-cost semiconductor device and a method for manufacturing the same, which reduce the inspection cost of the semiconductor device.
[Means to solve the problem]
In order to achieve at least one of the above objects, an outline of a representative one of the inventions disclosed in the present application will be briefly described as follows.
(1) A master clock, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a timing generation circuit that receives the test pattern data and generates a test waveform, and tests the test waveform under test. A semiconductor test apparatus having a driver applied to a semiconductor device, a comparison circuit for determining a response waveform from a semiconductor device under test, and a fail memory for storing a determined result, wherein the algorithmic pattern generation is performed. A semiconductor testing apparatus, comprising: an address generator and a scrambler, wherein the scrambler has a plurality of scramble memories.
(2) a step of forming circuit elements on the semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements and external connection terminals on the semiconductor wafer, and forming a protective film on the semiconductor wafer A method of manufacturing a semiconductor device, comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a state of the semiconductor wafer, wherein the inspection step includes a master clock and information about a test waveform. An algorithmic pattern generator for generating test pattern data, a timing generation circuit for receiving the test pattern data and generating the test waveform, a driver for applying the test waveform to the semiconductor device under test, and a device under test Semiconductor test apparatus having comparison circuit for determining response waveform from semiconductor device and fail memory for storing the determined result A semiconductor device is inspected by applying a test signal output from the semiconductor device to a semiconductor device to be tested.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment of the present invention according to the present invention will be described with reference to FIGS.
[0023]
FIG. 1 shows a configuration of a small capacity programmable scrambler according to one embodiment of the present invention. The small-capacity programmable scrambler according to the present embodiment is capable of converting a common logical address of a memory as a device under test into a unique physical address different for each memory product, and reducing the capacity of the scrambled memory. It is. Hereinafter, this configuration will be described.
[0024]
When the device under test 16 is tested, an algorithmic pattern generator (ALPG) 15 that generates a regular logical address according to the test order, test data to be written in a memory to be tested, and a control signal is used. Is applied to the device under test.
[0025]
At this time, a physical address, which is a physical address, has a unique address for each memory maker and each memory product depending on the arrangement of the memory cells in memory development with respect to a common logical address in the memory. That is, the physical address has a different address for each product with respect to the logical address.
[0026]
Therefore, a semiconductor test apparatus, particularly a semiconductor test apparatus that needs to test a wide variety of memories, requires a scrambler 13 that converts a common logical address described in a test pattern into a physical address for each product.
[0027]
The scrambler 13 inputs n bits of the logical address common to the memory output from the address generator 14 in the algorithmic pattern generator 15 to the memory controller 12, and the memory controller 12 converts the input logical address into the scrambled memory 10 Data is read from the scramble memories 10-1 to 10-k as memory read addresses of -1 to 10-k.
[0028]
Here, an m-bit memory address obtained by dividing the input n-bit logical address by k is input to the scrambler.
[0029]
Each of the scramble memories 10-1 to 10-k has the same bit width as the address n bits input from the address generator (similar to the address of the memory as the device under test) and the address n bits from the address generator. A memory having a depth of 2 m raised to m address bits after the k division is provided. Prior to the start of the test, the product-specific physical address value of the memory to be tested is stored in each scramble memory as memory data of the scramble memories 10-1 to 10-k.
[0030]
At this time, each scramble memory has data for outputting the contents of the address conversion table for its own system corresponding to m bits of the read memory address input to the scramble memory, and m bits for the read memory address input to the other scramble memories. The contents of the address conversion table corresponding to the other system are stored.
[0031]
Here, the own system is an address conversion table for a memory address of the own memory, and the other system is an address conversion table for a memory address of another memory.
[0032]
The data read from the scramble memories 10-1 to 10-k is input to a logic circuit, for example, EOR logics 11-1 to 11-k for performing an exclusive logical operation. In the EOR logics 11-1 to 11-k, the read data from the scramble memories 10-1 to 10-k are subjected to exclusive logical operation for each bit and output. The values output from the EOR logics 11-1 to 11-k are converted from logical addresses common to memories to physical addresses unique to each memory product, and input to the device under test 16 as an output of the scrambler 13. .
[0033]
With the above configuration, when the test is started, n bits of the logical address common to the memories are sequentially output from the address generator 14 of the algorithmic pattern generator 15 in accordance with the test order. The scrambler 13 converts the logical address into a physical address by the scramble memories 10-1 to 10-k and the EOR logics 11-1 to 11-k, applies the address to the device under test, and makes the device under test 16 normal. Test whether
[0034]
By using a plurality of scramble memories for the scrambler, the capacity of the scramble memory can be reduced. This also allows the scramble memory to be built in the scrambler.
[0035]
Further, by using a scramble memory having a small capacity, the number of semiconductor test devices can be reduced, and therefore, the cost for testing and manufacturing semiconductors can be reduced.
[0036]
FIG. 14 shows a specific example in which the address of the memory as the device under test is 4 bits. FIG. 14 shows a configuration diagram of the scrambler when the address of the device under test is 4 bits, the number of divisions of the scramble memory k = 2, and the number of divided address bits m = 2 bits. FIG. 15 shows, as a comparative example, a configuration of a scrambler in which four bits of an address are externally provided.
[0037]
As described above, the address input to the scrambler is a logical address common to the memory, and needs to be converted into a physical address unique to the memory product by the scrambler.
[0038]
The memory controller 12 divides the input 4-bit logical address (X3 to X0) into upper 2 bits (X3 to X2) and lower 2 bits (X1 to X0), and the upper 2 bits (X3 to X2) The lower two bits (X1 to X0) of the memory read address of the scramble memory 10-1 are output as the memory read address of the scramble memory 10-2.
[0039]
The scramble memories 10-1 and 10-2 have a data width of 4 bits and a depth of 4 (2 2 = 4).
[0040]
As shown in FIG. 14, the scramble memory 10-1 stores an address conversion table corresponding to an upper 2-bit address (own system) and an address conversion table corresponding to a lower 2-bit address (other system). Keep it. Similarly, the scramble memory 10-2 stores an address conversion table corresponding to the lower 2-bit address (own system) and an address conversion table corresponding to the upper 2-bit address (other system).
[0041]
Read data outputs from the scramble memories 10-1 and 10-2 are input to EORs 11-1 and 11-2 for performing exclusive logical operation, and the output subjected to the EOR operation becomes a physical address and is applied to a device under test. FIG. 14 also shows the output result of the address conversion by the scramble memories 10-1 and 10-2 and the EORs 11-1 and 11-2.
[0042]
FIG. 16 shows that the scramble memory 10-1 has only an address conversion table corresponding to the upper two-bit address (own system), and the scramble memory 10-2 similarly supports the lower 2-bit address (own system). Address conversion in the case where only the converted address conversion table is provided.
[0043]
As is clear from FIG. 16, when there is no other system, it can be understood that address conversion from a logical address to a physical address cannot be performed.
[0044]
Here, when converting a 4-bit address with the conventional configuration, one scrambling memory having a depth of 2 4 = 16 × 4 bits is required to convert a 4-bit address to an arbitrary address. It is. In the scrambling method of this embodiment, x2 scramble memories of 16 bits (4 depths x 4 bits width) are required. Therefore, in the present embodiment, the capacity of the scramble memory can be reduced to half of the capacity of the conventional memory of 64 bits (16 × 4).
[0045]
With the above configuration, the small address scrambling method of the present invention can convert a logical address into an arbitrary physical address, and can test the device under test 16 with a reduced capacity of the scramble memory.
[0046]
Further, this makes it possible to reduce the size and cost of the semiconductor test apparatus. Further, test costs and manufacturing costs of the semiconductor device can be reduced.
[0047]
Next, FIG. 2 shows an example in which the address of the memory as the device under test is 16 bits. FIG. 2 shows a configuration diagram of the scrambler when the address of the device under test is 16 bits, the number of divisions of the scramble memory k = 2, and the number of divided address bits m = 8 bits. The address input as described above is a logical address common to memories, and needs to be converted into a physical address unique to a memory product by a scrambler. The memory controller 12 converts the input 16-bit logical address (X15 to X0) into the upper 8 bits.
(X15 to X8) and lower 8 bits (X7 to X0), the upper 8 bits (X15 to X8) are the memory read address of the scramble memory 10-1, and the lower 8 bits (X7 to X0) are the scramble memory 10 -2 as a memory read address. The scramble memories 10-1 and 10-2 have a data width of 16 bits and a depth of 256 (2 8 = 256).
[0048]
The scramble memory 10-1 stores an address conversion table corresponding to an upper 8-bit address (own system) and an address conversion table corresponding to a lower 8-bit address (other system). Similarly, the scramble memory 10-2 stores an address conversion table corresponding to the lower 8-bit address (own system) and an address conversion table corresponding to the upper 8-bit address (other system).
[0049]
Read data outputs from the scramble memories 10-1 and 10-2 are input to EORs 11-1 and 11-2 for performing exclusive logical operation, and the output subjected to the EOR operation becomes a physical address and is applied to a device under test.
[0050]
Here, when a 16-bit address is converted in the conventional configuration, a scrambling memory of 64k (2 @ 16 = 65536 depth) × 16-bit width is used to convert a 16-bit address to an arbitrary address. is necessary. Accordingly, since the scrambling method of the present invention has 8192 bits (16 × 256 × 2) compared to the capacity of the conventional memory of 1048576 bits (16 × 65536), the scrambling memory capacity is reduced to 1/128.
[0051]
According to the present embodiment, as can be seen from a comparison of the case where the address of the device under test is 4 bits and 16 bits, when the number of bits of the address of the device under test is large, the capacity of the scramble memory is further increased. Can be reduced.
[0052]
FIG. 3 shows an example of a scramble calculation in the scramble configuration of FIG. 2 when the memory as the device under test has 16 bits.
[0053]
Specific address conversion (scramble) by hardware is performed by the following two processes.
1) Arbitrary bits of the address bits are rearranged into arbitrary bits.
2) Exclusive logical (EOR) operation is performed on an arbitrary bit of the address bit and the other bit.
[0054]
As shown in FIG. 3, in the address conversion process, the rearrangement of the bits and the exclusive OR (EOR) operation between the bits are performed on the 16-bit addresses (X15 to X0).
[0055]
In response to the address inputs X15 to X0, the scrambled memory 10-1 (SCRAM1) and the scrambled memory 10-2 (SCRAM2) store data on which scramble calculation has been performed before the start of the test. For example, when rearranging an arbitrary bit of the upper 8 bits into an arbitrary bit of the lower 8 bits, the value of the upper arbitrary bit is added to other system data of the scramble memory 10-1 in which the upper bit is input as a memory read address. The logical value "0" is stored in the self-system data of the scramble memory 10-2 in which the lower bits are input as the read address.
[0056]
Similarly, in the case of performing the EOR operation, for example, when rearranging the result of the EOR operation between the upper 8 bits into an arbitrary lower 8 bits, the scramble memory 10-1 in which the upper bits are input as a memory read address The value of the result of the EOR operation between any upper bits in the other system data is stored, and the own system data of the scramble memory 10-2 in which the lower bits are input as a read address stores a logical value '0'. Keep it.
[0057]
Also, for example, when performing an EOR operation on an arbitrary bit of an upper bit and an arbitrary bit of a lower bit and rearranging the bit to an arbitrary bit of the lower bit, the scramble memory 10-1 in which the upper bit is input as a memory read address The value of an arbitrary high-order bit is stored in the other-system data, and the value of any low-order bit is stored in the own-system data of the scramble memory 10-2 in which the low-order bit is input as a read address.
[0058]
By reading the stored value from the scrambled memory of 16 bits × 256 depth corresponding to the input address of 16 bits and performing EOR operation, it is possible to convert the address of 16 bits into an arbitrary address. .
[0059]
FIG. 4 shows an example in which the number of divisions of the scramble memory is divided into four for an example in which the memory address is 16 bits. FIG. 3 is a configuration diagram of a scrambler when the number of divisions of the scramble memory is k = 4 and the number of divided address bits is m = 4 bits. The address input as described above is a logical address common to memories, and needs to be converted into a physical address unique to a memory product by a scrambler. The memory controller 12 divides the input 16-bit logical address (X15 to X0) into four bits (X15 to X12, X11 to X8, X7 to X4, X3 to X0), respectively, and , 17-2, 17-3, and 17-4 are output as 4 bits. The scramble memories 17-1, 17-2, 17-3, and 17-4 have a data width of 16 bits and a depth of 16 (2 to the fourth power = 16). Similarly, when the address bits are divided into four by the scrambling method according to the present invention, while the capacity of the scramble memory is 1048576 bits (16 × 65536) when the 16-bit address is converted in the conventional configuration, 1024 bits (16 × 16 16 × 4), the scramble memory capacity is reduced to 1/1024. Therefore, the scramble memory can be further reduced by increasing the number of divided memory addresses.
[0060]
FIG. 5 shows an example in which the small capacity programmable scrambler of the present invention is applied to a plurality of addresses and data in addition to a single address. For example, in the case of a DRAM memory having an X (ROW) address of 16 bits, a Y (Cloud) address of 16 bits, and data of 16 bits, scrambling memories 19-1 and 19- having a depth of 48 bits × 256 for scrambling the X address of 16 bits. 2. Scrambling memories 20-1 and 20-2 of 32 bits × 256 depth for scrambling of 16 bits of Y address, and scrambling memories 21-1.21-2 of 16 bits × 256 depth for scrambling of 16 bits of data. In order to apply a test pattern in the order of the X address, the Y address, and the data to the memory to be the device under test, in addition to the X address 16 bit address conversion, the X address 16 bit scramble operation result is converted to the Y address. X-address 16 bits And it is possible to reflect the Y address 16 bits of the scramble operation on 16-bit data.
[0061]
So far, the scramble memory has been described. Next, an algorithmic pattern generator using the above-described scramble memory will be described.
[0062]
FIG. 7 shows a configuration of an algorithmic pattern generator to which the small capacity programmable scrambling method described above is applied. The outline of the algorithmic pattern generator will be described below.
[0063]
The algorithmic pattern generator 15 constitutes a part of a semiconductor test apparatus as shown in FIG. 10 (the semiconductor test apparatus will be described in detail later), and stores control and values for performing a test. An X-address generation unit 27 and a Y-address generation unit 28 for outputting a logical address common to the memories based on a signal from the instruction memory 25, and data generation for generating data to be written to a memory as a device under test A command generator 26 for generating a command for controlling writing / reading to / from a memory which is a device under test; an X address scrambler 42 for scrambling an X address; a Y address scrambler for scrambling a Y address 43, Data scramble for data scramble Consisting of assembler 44.
[0064]
Each address and data scrambler is provided with the small-capacity scramble memories 19, 20, and 21 of the above embodiment and EOR logics 22, 23, and 24 for performing exclusive logical operations.
[0065]
Conventionally, a large-capacity scrambling memory is required to test a large-capacity memory, and therefore, it is necessary to have a scrambling memory outside the algorithmic pattern generator. For this reason, pins for interfacing with the external memory are required, and there has been a problem of an increase in the mounting area and the price of the LSI due to an increase in the package and an increase in the mounting area and the component price of the external memory. The capacity-programmable scrambler allows the scrambler 13 to be built in the algorithmic pattern generator.
[0066]
FIG. 8 is a configuration diagram of an ALPG chip (semiconductor chip) in which the above algorithmic pattern generator is integrated into one chip. The ALPG chip includes an instruction memory 25, an address, data, a command generator 32, a scramble memory 33, an EOR logic 11, a memory controller 12, a controller 30, and input / output pads. By applying the small-capacity programmable scrambler of the above embodiment, the capacity of the scramble memory 33 can be reduced, and the scramble memory 33 can be built in the chip. This eliminates the need to have an external scramble memory, so that the mounting area can be reduced. Further, since the interface between the algorithmic pattern generator and the external scramble memory is unnecessary, the number of pads of the input / output pads 48 of the ALPG chip and the number of pins of the LSI can be reduced, so that the ALPG-LSI package can be downsized. .
[0067]
FIG. 9 is a diagram showing a configuration in which a plurality of devices under test are tested simultaneously using a plurality of the above ALPG-LSIs. An external scramble memory is not required, and the package can be miniaturized by reducing the number of pins of the ALPG-LSI, so that the mounting area is reduced. Therefore, a plurality of ALPG-LSIs can be mounted on the substrate, and a large number of devices under test can be tested at the same time.
[0068]
FIG. 10 is a configuration diagram of a semiconductor test apparatus for testing a memory as a device under test. The outline of the semiconductor test apparatus will be described below.
[0069]
The semiconductor test apparatus 45 adjusts the time for outputting the test pattern from the algorithmic pattern generator 15 by the timing generation circuit 35 by the timing generation circuit 35, and provides the same to the device under test 16 from the driver 36 in the pin electronics 46. The response signal from the device under test 16 is recognized as a digital signal of “1” or “0” by the comparator 37 and is input to the logical comparator 47. The logic comparator 47 compares the expected value from the algorithmic pattern generator 15 with the response waveform from the device under test 16 to test whether the device under test 16 is operating normally. If the determination result is a mismatch, the mismatched address is stored in the fail memory 39 in the fail storage unit 38.
[0070]
Here, the small-capacity programmable scramble of the above embodiment is applied to the algorithmic pattern generator 15 that outputs the test pattern and the expected value, and the capacity of the scramble memory 33 is reduced. A scramble memory 33 can be incorporated.
[0071]
FIG. 11 is an external view of the semiconductor test apparatus shown in FIG. As described above, by applying the small-capacity programmable scrambler of the present invention, the size of the LSI can be reduced, so that the test circuit can be mounted on the test board 51 with high density, and the device can be reduced in size.
[0072]
With the configuration described above, conventionally, it is necessary to provide a scramble memory outside the LSI due to the need for increasing the capacity of the scramble memory by increasing the capacity of the memory, and the high integration of the test circuit has been a bottleneck. However, the small-capacity programmable scrambler of the present invention makes it possible to incorporate a scramble memory in an LSI. This eliminates the need for an external scramble memory, and makes it possible to reduce the size and cost of the device by increasing the integration of the test circuit, reducing the number of LSI pins, reducing the size of the LSI package, and reducing the number of LSIs used in the device. It is.
[0073]
Subsequently, a method of testing (testing) a semiconductor device using the semiconductor test device having the scramble memory described above and a method of manufacturing the semiconductor device will be described. FIG. 6 is a diagram showing the position of a semiconductor test apparatus in a semiconductor manufacturing process.
[0074]
The manufacturing process of the semiconductor device includes a wafer processing step, a wafer inspection step, an assembly step, and a product inspection step, as shown in FIG.
[0075]
The test of a semiconductor device (wafer) using the above-described semiconductor test apparatus can be first used in a wafer inspection process on a wafer formed in a wafer processing process. At this time, by connecting the contact terminal formed on the wafer probe to a semiconductor chip (semiconductor element) on the wafer, a test such as a function test and a function selection of the semiconductor element on the wafer is performed by a semiconductor test apparatus (P Inspection).
[0076]
Next, the chip determined to be normal in the P test is subjected to dicing, die bonding, wire bonding, molding, and assembly in an assembling process, and becomes a package on which a semiconductor chip is mounted. The assembled LSI undergoes a burn-in, DC test, function (function) test, and timing (AC) test in a product inspection process, and only a normal LSI is shipped. The inspection by the semiconductor test apparatus according to the present embodiment can be used for inspection of a semiconductor package (semiconductor device) in a product inspection process.
[0077]
Note that the manufacturing process of the semiconductor device is not limited to that shown in FIG. 6, and a so-called wafer-level CSP is used to form a surface protection layer made of an insulating layer on a semiconductor element of a wafer and to form an electrode of the semiconductor element at the wafer level. Needless to say, a semiconductor device may be formed by laying out wiring and forming external connection terminals (bumps) and then dicing the wafer.
[0078]
By using the small-capacity programmable scrambler described in the above embodiment, the inspection cost of the semiconductor chip (semiconductor package) and the manufacturing cost of the semiconductor device can be reduced. In addition, the latest semiconductor chip (semiconductor package) having a large capacity can be inspected and manufactured using a semiconductor chip (scramble memory) having a smaller capacity than the latest semiconductor chip.
[0079]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the invention is not limited to the above embodiment, and it can be variously modified without departing from the gist of the invention. Not even.
[0080]
The representative aspects disclosed in the above embodiments are as follows.
(1) A master clock, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a timing generation circuit that receives the test pattern data and generates a test waveform, and tests the test waveform under test. A semiconductor test apparatus having a driver applied to a semiconductor device, a comparison circuit that determines a response waveform from the semiconductor device under test, and a fail memory that stores a determined result,
The semiconductor test apparatus, wherein the algorithmic pattern generator has an address generator and a scrambler, and the scrambler has a plurality of scramble memories.
(2) The semiconductor test apparatus according to (1), wherein the capacity of the scramble memory is smaller than the capacity of the semiconductor device to be tested.
(3) In the semiconductor test apparatus according to the above (1) or (2), the scrambler divides an address output from the address generator into a plurality of addresses, and a first part of the divided addresses. And a second scramble memory to which a second part of the divided address is inputted.
(4) In the semiconductor test apparatus according to the above (3), the first and second scramble memories may include a first part or a second part of the divided address and the address generation unit. A portion used when converting the generated address into a predetermined address of the semiconductor device to be tested.
(5) In the semiconductor test apparatus according to any one of (1) to (3), each of the scramble memories stores address data input to the scramble memory and data different from the address data. A semiconductor test apparatus having an address conversion table including:
(6) The semiconductor test apparatus according to any one of (1) to (5), wherein the algorithmic pattern generator is arranged between the scramble memory and an output terminal of the algorithmic pattern generator. A semiconductor test apparatus having a plurality of logic circuits connected to the scramble memory, respectively.
(7) The semiconductor test apparatus according to (6), wherein the logic circuit is an EOR logic circuit.
(8) The semiconductor test device according to (6), wherein the logic circuit converts an address output from each of the scramble memories into a predetermined address of the semiconductor device to be tested. Semiconductor test equipment.
(9) A semiconductor test device for testing a semiconductor device to be tested, wherein the semiconductor test device includes an algorithmic pattern generator for generating a test pattern, an address generator and an address generator. A scrambler for converting the generated logical address into a physical address of the semiconductor device; the scrambler controls the scramble memory using the address n bits input from the address conversion unit to the scrambler as a memory address; An exclusive OR of a memory controller, a plurality of scramble memories for outputting a constant conversion table content according to a memory address from the memory controller, and output data from the scramble memory output according to a memory address from the memory controller EOR logic for calculating The scramble memory has an n-bit width similar to the n-bit address of the semiconductor device, and 2 m-th power when the n-bit address of the device under test is m bits divided according to the number of the scramble memories. A semiconductor test apparatus having a depth and each scramble memory has data for outputting the contents of an address conversion table for its own system and contents of an address conversion table for another system.
[0081]
In the semiconductor device described in (9), a test pattern is further provided from the pattern generator to the device under test, and a response waveform from the device under test and an expected value pattern from the pattern generator are compared with each other by a logical comparator. And when the mismatch is detected, fail data may be written to the same address of the memory under test where the mismatch occurred in the fail memory.
(10) A semiconductor device is inspected by applying a test signal output from the semiconductor test device according to any one of (1) to (9) to the semiconductor device to be tested. For testing semiconductor devices.
(11) a step of forming a circuit element on a semiconductor wafer, a step of forming a wiring for electrically connecting an electrode of the circuit element and an external connection terminal on the semiconductor wafer, and forming a protective film on the semiconductor wafer A semiconductor device manufacturing method comprising the steps of: dicing the semiconductor wafer; and inspecting the semiconductor device in the semiconductor wafer state,
In the inspection step, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a master clock, a timing generation circuit that receives the test pattern data and generates the test waveform, To a semiconductor device under test, a comparison circuit for determining a response waveform from the semiconductor device under test, and a test signal output from a semiconductor test device having a fail memory for storing the determined result. A method for manufacturing a semiconductor device, comprising: applying a test to a semiconductor device to be tested to inspect the semiconductor device.
(12) a step of forming circuit elements on a semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements to external connection terminals on the semiconductor wafer, and forming a protective film on the semiconductor wafer A semiconductor device manufacturing method comprising the steps of: dicing the semiconductor wafer; and inspecting the semiconductor device in the semiconductor wafer state,
In the test step, a test signal formed by using a plurality of scramble memories having a smaller capacity than that of the semiconductor device under test is applied to the semiconductor device under test. Device manufacturing method.
(13) A step of forming a circuit element on a semiconductor wafer, a step of forming a wiring on the semiconductor wafer for electrically connecting an electrode of the circuit element to an external connection terminal, and forming a protective film on the semiconductor wafer. A semiconductor device manufacturing method comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a diced and individualized state.
In the inspection step, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a master clock, a timing generation circuit that receives the test pattern data and generates the test waveform, To a semiconductor device under test, a comparison circuit for determining a response waveform from the semiconductor device under test, and a test signal output from a semiconductor test device having a fail memory for storing the determined result. A method for manufacturing a semiconductor device, comprising: applying a test to a semiconductor device to be tested to inspect the semiconductor device.
(14) A step of forming circuit elements on a semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements to external connection terminals on the semiconductor wafer, and forming a protective film on the semiconductor wafer. A semiconductor device manufacturing method comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a diced and individualized state.
In the test step, a test signal formed by using a plurality of scramble memories having a smaller capacity than that of the semiconductor device under test is applied to the semiconductor device under test. Device manufacturing method.
[0082]
【The invention's effect】
According to the representative inventions disclosed in the present application, at least one of the following effects can be obtained.
[0083]
(1) Even when testing a large-capacity memory, an arbitrary logical address can be converted into various kinds of physical addresses that differ for each memory product, and the capacity of the scramble memory can be reduced.
[0084]
(2) Thereby, the scramble memory can be built in the LSI (ALPG).
[0085]
(3) This makes it possible to reduce the size and cost of the semiconductor test apparatus.
[0086]
(4) The test price can be reduced by reducing the price of the semiconductor test apparatus, and the product price of the memory as the device under test can be reduced.
[0087]
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a small capacity programmable scrambler according to an embodiment of the present invention.
FIG. 2 is a configuration diagram showing an example of a small-capacity programmable scrambler according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining an operation of the small-capacity programmable scrambler according to the embodiment of the present invention;
FIG. 4 is a configuration diagram showing an example of a small-capacity programmable scrambler according to an embodiment of the present invention.
FIG. 5 is a configuration diagram showing an example of a small-capacity programmable scrambler according to an embodiment of the present invention.
FIG. 6 is a diagram showing the positioning of a small-capacity programmable scrambler in a semiconductor manufacturing process according to an embodiment of the present invention.
FIG. 7 is a configuration diagram of an algorithmic pattern generator to which a small-capacity programmable scrambler according to an embodiment of the present invention is applied.
FIG. 8 is a configuration diagram of an ALPG chip according to an embodiment of the present invention.
FIG. 9 is a configuration diagram of a test using the multi-ALPG according to the embodiment of the present invention.
FIG. 10 is a configuration diagram of a semiconductor test apparatus to which a small-capacity programmable scrambler according to an embodiment of the present invention is applied.
FIG. 11 is an external view of a semiconductor test apparatus to which the small capacity programmable scrambler according to the embodiment of the present invention is applied.
FIG. 12 is a configuration diagram illustrating an example of a conventional scrambler.
FIG. 13 is a configuration diagram illustrating an example of a conventional scrambler.
FIG. 14 is a configuration diagram showing an example when an address is 4 bits according to the embodiment of the present invention.
FIG. 15 is a configuration diagram showing an example of a conventional case when an address is 4 bits.
FIG. 16 is a configuration diagram showing an example when there is no other system at the time of 4-bit address according to the embodiment of the present invention;
[Explanation of symbols]
10, 17, 19, 20, 21, 33, 40 ... scramble memory, 11, 18, 22, 23, 24 ... EOR logic, 12 ... memory controller, 13, 34 ... scrambler, 14 ... address generator, 15 ... Algorithmic pattern generator, 16 ... Device under test, 25 ... Instruction memory, 26 ... Command generator, 27 ... X address generator, 28 ... Y address generator, 29 ... Data generator, 30 ... Controller, 31 ... Y operation unit, 32 ... address, data, command generation unit, 35 ... timing generator, 36 ... driver, 37 ... comparator, 38 ... fail storage unit, 39 ... fail memory, 41 ... scramble logic unit, 42 ... X address scramble Bra, 43 ... Y address scrambler, 44 ... Data scrambler, 45 ... Semiconductor test equipment 46 ... pin electronics, 47 ... comparator, 48 ... input-output pads, 49 ... ALPG chip, 50 ... control computer, 51 ... test substrate

Claims (14)

A master clock, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a timing generation circuit that receives the test pattern data and generates a test waveform, and transmits the test waveform to a semiconductor device under test. A semiconductor test apparatus having a driver to be applied, a comparison circuit for determining a response waveform from the semiconductor device under test, and a fail memory for storing the determined result,
The semiconductor test apparatus, wherein the algorithmic pattern generator has an address generator and a scrambler, and the scrambler has a plurality of scramble memories. The semiconductor test apparatus according to claim 1, wherein:
A semiconductor test apparatus, wherein the capacity of the scramble memory is smaller than the capacity of the semiconductor device to be tested. The semiconductor test apparatus according to claim 1 or 2,
The scrambler divides the address output from the address generator into a plurality of parts, a first scramble memory into which a first part of the divided address is input, and a second part of the divided address. And a second scramble memory to which the portion (1) is input. The semiconductor test apparatus according to claim 3, wherein
The first and second scramble memories include a first part or a second part of the divided address, and an address generated by the address generation unit, a predetermined address of the semiconductor device under test. And a portion used when converting to a semiconductor test device. The semiconductor test apparatus according to claim 1, wherein:
A semiconductor test apparatus, wherein each of the scramble memories has an address conversion table including address data input to the scramble memory and data different from the address data. The semiconductor test apparatus according to claim 1, wherein:
A semiconductor test apparatus, wherein the algorithmic pattern generator includes a plurality of logic circuits connected to the scramble memory between the scramble memory and an output terminal of the algorithmic pattern generator. The semiconductor test apparatus according to claim 6, wherein
A semiconductor test apparatus, wherein the logic circuit is an EOR logic circuit. The semiconductor test apparatus according to claim 6, wherein
A semiconductor test apparatus, wherein the logic circuit converts an address output from each of the scramble memories into a predetermined address of the semiconductor device under test. A semiconductor test apparatus for testing a semiconductor device under test,
The semiconductor test apparatus includes, in an algorithmic pattern generator that generates a test pattern, an address generator and a scrambler that converts a logical address generated by the address generator into a physical address of the semiconductor device,
A memory controller that controls a scramble memory using the address n bits input to the scrambler from the address conversion unit as a memory address;
A plurality of scramble memories that output a constant conversion table content according to a memory address from the memory controller;
EOR logic for performing an exclusive OR operation on output data from the scramble memory output according to a memory address from the memory controller,
The scrambled memory has an n-bit width similar to the n-bit address of the semiconductor device, and 2 m raised to the m-th power when the n-bit address of the device under test is m bits divided according to the number of the scrambled memories. With a depth of
Further, each of the scramble memories has data for outputting the contents of an address conversion table for the own system and contents of the address conversion table for another system. 10. A semiconductor device, comprising: testing a semiconductor device by applying a test signal output from the semiconductor test device according to claim 1 to the semiconductor device to be tested. Inspection methods. A step of forming circuit elements on a semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements and external connection terminals on the semiconductor wafer, and a step of forming a protective film on the semiconductor wafer; Dicing the semiconductor wafer and inspecting the semiconductor device in the semiconductor wafer state, comprising:
In the inspection step, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a master clock, a timing generation circuit that receives the test pattern data and generates the test waveform, To a semiconductor device under test, a comparison circuit for determining a response waveform from the semiconductor device under test, and a test signal output from a semiconductor test device having a fail memory for storing the determined result. A method for manufacturing a semiconductor device, comprising: applying a test to a semiconductor device to be tested to inspect the semiconductor device. A step of forming circuit elements on a semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements and external connection terminals on the semiconductor wafer, and a step of forming a protective film on the semiconductor wafer; Dicing the semiconductor wafer and inspecting the semiconductor device in the semiconductor wafer state, comprising:
In the test step, a test signal formed by using a plurality of scramble memories having a smaller capacity than that of the semiconductor device under test is applied to the semiconductor device under test. Device manufacturing method. A step of forming circuit elements on a semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements and external connection terminals on the semiconductor wafer, and a step of forming a protective film on the semiconductor wafer; A method of manufacturing a semiconductor device, comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a diced and individualized state.
In the inspection step, an algorithmic pattern generator that generates test pattern data including information on a test waveform, a master clock, a timing generation circuit that receives the test pattern data and generates the test waveform, To a semiconductor device under test, a comparison circuit for determining a response waveform from the semiconductor device under test, and a test signal output from a semiconductor test device having a fail memory for storing the determined result. A method for manufacturing a semiconductor device, comprising: applying a test to a semiconductor device to be tested to inspect the semiconductor device. A step of forming circuit elements on a semiconductor wafer, a step of forming wiring for electrically connecting electrodes of the circuit elements and external connection terminals on the semiconductor wafer, and a step of forming a protective film on the semiconductor wafer; A method of manufacturing a semiconductor device, comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a diced and individualized state.
In the test step, a test signal formed by using a plurality of scramble memories having a smaller capacity than that of the semiconductor device under test is applied to the semiconductor device under test. Device manufacturing method.

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