TWI551021B - Flyback power converter and control method thereof - Google Patents

Description

Flyback power converter and control method thereof

The present invention relates to a power converter, and more particularly to a flyback power converter capable of stabilizing an output current and a control method therefor.

Traditional flyback power converters must use an opto-coupler to feedback the output voltage for electrical isolation. However, optocouplers are susceptible to operating temperatures, so the development of primary side sensing methods to replace optocouplers has become a trend.

In addition, in the existing flyback power converter design, the designer usually compares the detected output current with a set value, and uses the comparison result as the basis for controlling the power conversion operation. For example, the general power conversion control behavior is generally to increase the on-time of the power switch to increase the output current when the detected output current is less than the set value, and to reduce the power switch when detecting that the output current is greater than the set value. The on-time is reduced to reduce the output current to maintain a dynamic balance of the output current at the set point.

However, although such a control method can maintain the output current to be dynamically stable, since such a control method is generally more susceptible to load operation or operation of the power conversion circuit, it often drifts when the load changes. This makes it difficult to maintain an average output current.

The present invention provides a flyback power converter and a control method thereof that solve the problems described in the prior art.

The flyback power converter of the present invention includes a power conversion circuit and a control circuit. The power conversion circuit includes a transformer and a power switch. The transformer has a primary side winding, a secondary side winding, and an auxiliary winding. The power switch is coupled to the primary side winding, wherein the power switch is controlled by the pulse width modulation control signal, so that the transformer converts the input power on the primary side winding to the output on the secondary side winding in response to switching of the power switch Voltage and output current. The control circuit is coupled to the power conversion circuit for detecting the first voltage on the auxiliary winding and the second voltage on the power switch, and thereby controlling the operation of the power conversion circuit. The control circuit adjusts the disable period of the pulse width modulation control signal according to the first voltage and the pulse width modulation control signal, and generates a timing value according to the second voltage, and generates a current indication signal according to the second voltage. The control circuit determines, according to the product of the count value and the current indication signal, whether the average output current of the output current in the signal period of the pulse width modulation control signal conforms to the preset current value, thereby determining the duty cycle of the pulse width modulation control signal according to the determination result. .

A control method of a flyback power conversion circuit, wherein the flyback power conversion circuit includes a transformer and a power switch, and the transformer has a primary side winding, a secondary side winding, and an auxiliary winding. The control method includes: detecting a first voltage on the auxiliary winding and a second voltage on the power switch; and prohibiting the pulse width modulation control signal according to the first voltage and the pulse width modulation control signal used to control the power switch During the energy period, the timing value is generated according to the second voltage; the current indication signal is generated according to the second voltage; the product of the count value and the current indication signal is calculated; and the average output current of the flyback power conversion circuit is determined according to the product to meet the preset current value; According to the judgment result, the duty cycle of the pulse width modulation control signal is determined.

Based on the above, an embodiment of the present invention provides a flyback power converter and a control method thereof, which can obtain a power conversion circuit by detecting a voltage on an auxiliary winding of a transformer and a voltage associated with a magnitude of an inductor current on a primary side. The operation information is further determined by the characteristic that the product of the output current of the reverse power conversion is substantially constant in the product of the average value of the signal period and the length of the disable time, thereby determining the transition time point of the pulse width modulation control signal. The average output current can be stably maintained at a preset current setting value without causing unstable drift with load operation or operation of the power conversion circuit.

The above described features and advantages of the invention will be apparent from the following description.

In order to make the disclosure of the present disclosure easier to understand, the following specific embodiments are examples of the disclosure that can be implemented. In addition, wherever possible, the same elements, components, and steps in the drawings and embodiments are used to represent the same or similar components.

1 is a functional block diagram of a flyback power converter according to an embodiment of the invention. Referring to FIG. 1, the flyback power converter 100 of the present embodiment can be applied to an AC-to-DC conversion system or a DC-to-DC conversion system. The input power source Pin is converted into an output power source Pout for use by the load LD of the back end.

Taking the AC-DC power conversion system illustrated in FIG. 1 as an example, the rectifier circuit 50 (for example, a full bridge rectifier) rectifies the AC power source ACin, and accordingly generates an input power source Pin to provide the flyback power converter 100. The flyback power converter 100 performs buck/boost conversion on the received input power source Pin to generate an output power source Pout to drive the load LD at the back end. On the other hand, in the application of the DC-DC power conversion system, the flyback power converter 100 can directly connect an external DC power source as its input power source Pin, and similarly buck/boost the input power source Pin. The output power source Pout is generated to drive the load LD at the back end.

The load LD can be, for example, a light emitting diode module, a DC motor driver, or any other electronic device that requires a stable current supply, which is not limited by the present invention.

Specifically, the flyback power converter 100 includes a power conversion circuit 110 and a control circuit 120. The power conversion circuit 110 includes at least a transformer and a power switch (not shown, which will be further described in the following embodiments), wherein the power switch of the power conversion circuit 110 is controlled by the pulse width modulation control signal provided by the control circuit 120. The control signal, PWM control signal) is switched by Spwm, so that the transformer is converted into the output voltage Vo and the output current Io in response to the switching of the power switch.

The control circuit 120 is coupled to the power conversion circuit 110 for operating under the DC system voltage VDD generated by the power conversion circuit, and generates a pulse width modulation control signal Spwm in response to a power supply requirement of the load LD. The operation of the power conversion circuit 110 is controlled.

The flyback power converter 100 of the present invention will be further described below with the circuit architecture shown in FIG. 3 is a schematic diagram of a circuit architecture of a flyback power converter according to an embodiment of FIG. 1.

Referring to FIG. 2, in the embodiment, the power conversion circuit 110 includes a transformer T, a power switch SW, an auxiliary line AC, a resistor Rcs, an output diode D1, and an output capacitor Co. The control circuit 120 can be implemented by, but not limited to, an integrated wafer having a drive pin P_DR, detection pins P_DT1 and P_DT2, and a power pin P_VDD.

The transformer T has a primary side winding Np, a secondary side winding Ns, and an auxiliary winding Na. The common-polarity terminal of the primary winding Np of the transformer T is used to receive the input voltage Vin, and the secondary winding s of the transformer T and the same end of the auxiliary winding Na are coupled to the secondary side. Ground terminal GND2.

In the configuration of the primary side, the first end (eg, the drain) of the power switch SW is coupled to the opposite-polarity terminal of the transformer T. The control terminal (eg, the gate) of the power switch SW is coupled to the drive pin P_DR of the control circuit 120 to receive the pulse width modulation control signal Spwm generated by the control circuit 120. The second end (for example, the source) of the power switch SW is coupled to the first end of the resistor Rcs and the detecting pin P_DT2 of the control circuit 120, so as to feedback the voltage information Vcs indicating the magnitude of the current flowing through the power switch SW. Control circuit 120 serves as a basis for control. The second end of the resistor Rcs is coupled to the ground terminal GND1 of the primary side.

In the configuration of the secondary side, the anode of the diode D1 is coupled to the opposite end of the secondary side winding Ns of the transformer T, and the cathode of the diode D1 is used to generate the output voltage Vo. The current flowing through the secondary side winding Ns and the diode D1 is herein defined as the inductor current Is, and the current supplied to the load LD is defined as the output current Io. The first end of the capacitor Co is coupled to the cathode of the diode D1, and the second end of the capacitor C1 is coupled to the ground GND2 of the secondary side.

In the configuration of the auxiliary winding Na side, the auxiliary line AC may include, for example, resistors R1 to R3, a capacitor C1, and a diode D2. The first end of the resistor R1 is coupled to the same end of the primary side winding, and the second end of the resistor R1 is coupled to the power pin P_VDD of the control circuit 120 to provide a DC system voltage VDD. The resistors R2 and R3 are connected in series with each other and coupled between the opposite end of the auxiliary winding Na and the ground GND2, wherein the resistors R2 and R3 form a voltage dividing structure, and the voltage dividing point/common node is coupled to the control circuit 120. The detection pin P_DT1 is provided to provide the voltage information V _DET indicating the voltage across the auxiliary winding Na to the control circuit 120. The capacitor C1 is coupled between the second end of the resistor R1 and the ground GND2. The anode of the diode D2 is coupled to the opposite end of the auxiliary coil Na, and the cathode of the diode D2 is coupled to the power pin P_VDD of the control circuit 120. It is to be noted that the grounding end GND1 of the primary side and the grounding end GND2 of the secondary side may be the same or different grounding surfaces, for example, and the invention is not limited thereto.

In detail, in the case where the flyback power converter 100 is in normal operation, the control circuit 120 correspondingly generates a pulse width modulation signal PWM to control the operation of the power conversion circuit 110 in response to the power supply demand of the load LD. Under this condition, when the power switch SW is turned on in response to the pulse width modulation control signal PWM generated by the control circuit 120, the input voltage Vin is connected across the primary side winding Np of the transformer T to As for the primary side winding Np, it is reflected in the input voltage Vin and the storage can cause the inductor current Ip to increase linearly. At the same time, on the secondary side winding Ns, due to the reverse bias of the diode D1, the secondary side winding Ns of the transformer T will have no current flowing. In addition, on the auxiliary winding Na side, since the reverse bias of the diode D2 is blocked, the auxiliary winding Na of the transformer T also has no current flowing. At this time, the output current Io is supplied by the output capacitor Co discharging the load LD.

On the other hand, when the power switch SW is turned off in response to the pulse width modulation control signal Spwm generated by the control circuit 120, the energy stored in the primary side winding Np of the transformer T is transferred based on Lenz's law. The secondary side winding Ns to the transformer T and the auxiliary winding Na. At the same time, since the diode D1 is turned on in the forward bias, the energy transferred to the secondary side winding Ns of the transformer T will charge the capacitor Co, and supply the output voltage Vo to the load LD. At this time, the output current Io is the same as the inductor current Is. In addition, the energy transferred to the auxiliary winding Na of the transformer T will supply the DC system voltage VDD to the control circuit 120 through the diode D2.

Therefore, it can be seen that the operation mode of the power switch 100 is alternately turned on and off based on the pulse width modulation control signal Spwm generated by the control circuit 120, and the flyback power converter 100 continuously supplies the output voltage Vo and the DC system voltage. VDD.

The control method of the flyback power converter 100 will be described with reference to the flow of steps illustrated in FIG. 3 . 3 is a flow chart showing the steps of a method for controlling a flyback power conversion circuit according to an embodiment of the present invention.

Referring to FIG. 2 and FIG. 3 simultaneously, in the embodiment, the control circuit 120 first detects the voltage V _DET on the auxiliary winding Na and the voltage Vcs on the power switch SW during the operation of the power conversion circuit 110 (steps) S310), wherein the voltage V _DET is related to the input voltage Vin during the period in which the power switch SW is turned on and is related to the output voltage Vo during the off period of the power switch SW, and the voltage Vcs is the inductor current with the primary side. Ip size is related.

Then, the control circuit 120 counts the disable period of the pulse width modulation control signal Spwm according to the detected signal voltage V _DET and the signal period of the pulse width modulation control signal Spwm, and generates a timing value accordingly (step S320). On the other hand, the control circuit 120 generates a current indicating signal indicating the magnitude of the secondary side inductor current Is/output current Io according to the detected ratio of the voltage V _CS to the turns ratio of the transformer T (step S330).

After obtaining the timing value of the length of the disable period of the pulse width modulation control signal Spwm and the current indication signal regarding the magnitude of the output current Io, the control circuit 120 calculates the length of the disable period of the pulse width modulation control signal Spwm and The product of the output current Io (step S340), and further determining, according to the calculated product, whether the average output current of the output current Io in the signal period of the pulse width modulation control signal Spwm meets the set preset current value (step S350) Then, the duty cycle of the pulse width modulation control signal Spwm is determined according to the judgment result (step S360).

According to the above control method, in the embodiment, the control circuit 120 can obtain the operation of the power conversion circuit 110 by detecting the voltage V _DET on the auxiliary winding Na of the transformer T and the voltage corresponding to the magnitude of the inductor current Ip on the primary side. Information such as input voltage Vin, output voltage Vo, output current Io, and charge/discharge time. The control circuit 120 can calculate the length of the disable period of the pulse width modulation control signal Spwm according to the information, and then based on the average value and the length of the disable time of the output current Io of the reverse power conversion in each signal period. The product of the product is substantially constant to determine the transition time point of the pulse width modulation control signal Spwm, thereby modulating the duty cycle of the pulse width modulation control signal Spwm generated. In this way, the average output current of the power conversion circuit 110 can be stably maintained at a preset current setting value without causing unstable drift with the operation of the load LD or the operation of the power conversion circuit 110.

In addition, since the voltage V _DET detected by the control circuit 120 through the auxiliary line AC can respectively indicate information about the input voltage Vin and the output voltage Vo during the period in which the power switch SW is turned on and off, therefore, In an exemplary embodiment, the control circuit 120 can also perform output over-voltage protection and output short-circuit protection according to the detected voltage V _DET during the on period of the power switch SW (ie, the enable period of the pulse width modulation control signal Spwm). And according to the voltage V _DET detected during the off period of the power switch SW (ie, the disable period of the pulse width modulation control signal Spwm), a control action such as high voltage compensation, low voltage compensation, or undervoltage protection is performed to improve the overall operation. The operational stability of the flyback power converter 100.

An example of the implementation of the control circuit 120 will be specifically described below with reference to FIGS. 4 and 5. 4 is a functional block diagram of a control circuit according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a circuit architecture of a control circuit in accordance with an embodiment of FIG.

Referring to FIG. 4, in the embodiment, the control circuit 120 includes a pulse width modulation signal generating circuit 122, a switch driving circuit 124, and an average output current detecting circuit 126. The pulse width modulation signal generating circuit 122 is configured to generate a periodic signal T_pwm indicating a duty cycle of the pulse width modulation signal Spwm according to the preset clock signal PWM_CLK and the error amplification signal Sea. The switch driving circuit 124 is coupled to the pulse width modulation signal generating circuit 122 and the power switch SW. The switch driving circuit 124 generates a pulse width modulation control signal Spwm having a corresponding enable period and disable period according to the received periodic signal T_pwm.

The average output current detecting circuit 126 is coupled to the pulse width modulation signal generating circuit 122, and can be used to count the disable period of the pulse width modulation signal Spwm according to the voltage V _DET and the periodic signal T_pwm and generate a timing value accordingly. In addition, the average output current detecting circuit 126 also samples the voltage Vcs to generate a current indicating signal.

In this embodiment, the average output current detecting circuit 126 multiplies the count value and the current indicating signal to generate a product signal. The average output current detecting circuit 126 then performs error amplification on the calculated product signal and a reference voltage representing a specific current setting value, and accordingly generates an error amplification signal Sea to be supplied to the pulse width modulation signal generating circuit 122. The pulse width modulation signal generating circuit 122 switches the periodic signal T_pwm from the enable level (for example, a high level) to the disable level according to the error amplification signal Sea when the product signal is equal to the reference voltage (for example, low). Level). Since the signal period of the pulse width modulation control signal Spwm is fixed and determined by the preset clock signal PWM_CLK in the pulse width modulation signal generating circuit 122, the pulse width modulation control is adjusted according to the error amplification signal Sea. The mode of the transition time of the signal Spwm is the control of the duty cycle of the pulse width modulation control signal Spwm.

More specifically, a specific circuit configuration example of the control circuit 120 can be as shown in FIG. Referring to FIG. 5, in the embodiment, the pulse width modulation signal generating circuit 122 includes a triangular wave and square wave generating circuit TSGC, a comparator COMP, and a flip-flop D1. The average output current detecting circuit 126 includes a timer CTC, a sample and hold circuit SHC, a multiplier MC, and an error amplifier EA. Among them, the timer CTC can be implemented by an architecture including an inverter INV, an inverting comparator INVC, a flip-flop D2, and an accumulator AAC (however, the present invention is not limited thereto).

In the pulse width modulation signal generating circuit 122, the triangular wave and square wave generating circuit TSGC provides a preset clock signal PWM_CLK to the set terminal (labeled as S) of the flip-flop D1, and provides the reference voltage Vref1 to the comparator COMP. Inverting terminal. The non-inverting terminal of the comparator COMP is coupled to the output of the error amplifier EA, and the output of the comparator COMP is coupled to the reset terminal (labeled as R) of the flip-flop D1. The output of the flip-flop D1 (labeled Q) is coupled to the input of the switch drive circuit 124 and the inverter INV to provide a periodic signal T_pwm.

In the average output current detecting circuit 126, the timer CTC receives the voltage V _DET and the periodic signal T_pwm, and starts timing according to the periodic signal T_pwm when the pulse width modulation control signal Spwm enters the disable period to generate the timing value CV_Toff, And the timing value CV_Toff is reset according to the voltage V _DET .

More specifically, in the timer CTC, the output of the inverter INV is coupled to the clock input of the flip-flop D2 (labeled CK). The non-inverting terminal of the inverting comparator INVC receives the voltage V _DET , the inverting terminal of the inverting comparator INVC is coupled to the reference voltage Vref2 , and the output terminal of the inverting comparator INVC is coupled to the reset terminal of the flip-flop D2 . The data input terminal (labeled as D) of the flip-flop D2 receives the DC system voltage VDD, and the output terminal of the flip-flop D2 is generated during the disable period according to the signals on the data input terminal, the clock input terminal and the reset terminal. The disable period indication signal SToff is switched to the high level. The disable period indication signal SToff and the period signal T_pwm are mutually inverted. The accumulator AAC performs an accumulating action when the indication signal SToff is switched to the high level during the disable period, thereby generating a count value CV_Toff indicating the length of the inactive period.

The sample and hold circuit SHC is configured to sample and hold the voltage Vcs during the enable period of the pulse width modulation control signal Spwm, and accordingly generate a current indication signal Scd indicating the magnitude of the primary side inductor current Ip at the sampling time point. In the present embodiment, the sample and hold circuit SHC may be designed to perform sampling only at half of the enabling period, or to sample at fixed time intervals during the enabling period, which is not limited by the present invention.

The multiplier MC is coupled to the timer CTC and the sample and hold circuit SHC, which can be used to multiply the count value CV_Toff outputted by the timer CTC and the current indication signal Scd outputted by the sample and hold circuit SHC to generate a product signal Sm. .

The inverting terminal of the error amplifier EA is coupled to the output of the multiplier MC to receive the product signal Sm. The non-inverting terminal of the error amplifier EA is coupled to a reference voltage Vrefi indicating a preset current value. The output of the error amplifier EA is coupled to the non-inverting terminal of the comparator COMP to provide an error amplification signal.

The specific circuit operation of the control circuit 120 when the power conversion circuit 110 operates in the discontinuous conduction mode (DCM) will be described below with the signal timing of FIG.

Referring to FIG. 2, FIG. 5 and FIG. 6 simultaneously, when the signal timing enters the disable period Toff from the enable period Ton, the pulse width modulation control signal Spwm switches from the high level to the low level, so that the power switch SW reacts. The pulse width modulation control signal Spwm at the low level is turned off.

During the disable period Toff, the current path on the primary side is cut off, so that the inductor current Ip drops to zero, and the secondary side winding Ns starts to discharge based on the energy stored in the previous uniform energy period Ton, and accordingly The inductor current Is is generated, wherein the inductor current Is gradually decreases with the discharge time during the disable period Toff.

In addition, the voltage across the auxiliary winding Na is related to the turns ratio of the output voltage Vo and the secondary side winding Ns, so the voltage V _DET can be expressed as the output voltage Vo and the auxiliary winding Na and the second time. The parameter of the turns ratio of the side winding Ns and the resistance value of the resistors R1 and R2 (V _DET =Na/Ns*Vo*R1/(R1+R2)). Therefore, the inverting comparator 124 outputs a low-level signal in response to the voltage V _DET during the disable period Toff, so that the flip-flop D2 outputs the high-level disable period indication signal according to the inverted periodic signal T_pwm. SToff. At this time, the accumulator AAC performs an accumulating count based on the high-level disable period indication signal SToff, and accordingly generates a timing value CV_Toff indicating the length of the inactive period.

As the secondary side winding Ns and the auxiliary winding Na are discharged, the inductor current Is drops from the peak current Isp to zero, and the voltage V _DET also drops rapidly and begins to oscillate. Wherein, when the voltage V _DET falls below the reference voltage Vref2, the inverting comparator INVC will change to output a high level signal, so that the flip-flop D2 reacts to the output of the inverting comparator INVC to indicate the disable period. The signal SToff is pulled down to the low level. At this time, the accumulator AAC responds to the low-level disable period indication signal SToff and stops counting.

Then, when the preset clock signal PWM_CLK is enabled, the signal period Tp enters the enable period Ton from the disable period Toff. At this time, the pulse width modulation control signal Spwm is switched from the low level to the high level, so that the power switch SW is turned on in response to the high level pulse width modulation control signal Spwm.

During the enable period Ton, the primary side winding Np stores energy based on the input voltage Vin, so that the primary side inductor current Ip gradually rises from zero current. Therefore, the voltage Vcs rises based on the gradually rising inductor current Ip.

On the other hand, the secondary side winding Ns and the auxiliary winding Na have no current flow, so the voltage V _DET is a negative voltage associated with the input voltage Vin (which can be expressed as VDET=-Na/Np*Vin*R2/( R1+R2), where Na/Np represents the turns ratio of the auxiliary winding Na to the primary side winding Np). At this time, since the voltage V _DET is a negative voltage, the inverting comparator INVC continuously outputs a high-level signal to the reset terminal of the flip-flop D2, so that the disable period indication signal SToff is maintained during the enable period Ton. Low level.

In the present embodiment, the multiplier MC performs multiplication processing based on the current indication signal Scd generated by the sample and hold circuit SHC and the timing value CV_Toff generated by the timer CTC. The product signal Sm representing the multiplication result is supplied to the inverting terminal of the error amplifier EA, thereby being compared with the reference voltage Vrefi of the error amplifier EA.

As shown in FIG. 6, since the voltage Vcs gradually rises with time during the enable period Ton, the multiplication result of the count value CV_Toff and the current indication signal Scd is gradually increased until the level of the product signal Sm is equal to the reference voltage. In Vrefi, it means that the current average output current Iavg has reached the set preset current value. At this time, the error amplification signal Sea causes the comparator COMP to output a high-level signal to reset the flip-flop D1, so that the periodic signal T_pwm is pulled from the high level to the low level, and the next period is disabled again. period.

Since the product of the power conversion behavior of the flyback power conversion circuit has a characteristic that the product of the average output current Iavg and the length of the disable period in each signal period Tp is constant, the present embodiment compares the product signal by Determining the transition time of the pulse width modulation signal Spwm by means of the reference voltage Vrefi (representing the current setting value), the output current Io is The average value in one signal period Tp is stably maintained at the current set value.

The specific circuit operation of the control circuit 120 when the power conversion circuit 110 is operated in the continuous conduction mode (CCM) will be described below with the signal timing of FIG.

Referring to FIG. 2, FIG. 5 and FIG. 7, the operation of this embodiment is substantially the same as that of the foregoing embodiment of FIG. The only difference between the two is that in the DCM, the disable period indication signal SToff is only high level during the period when the inductor current Ip is not zero, that is, under DCM, the timer CTC only counts the inductor current Ip. The length of the period of zero. In the CCM, since the inductor current Is does not fall to zero during the disable period Toff, the disable period indication signal SToff will be at a high level during the entire inactive period Toff, that is, under the CCM, timing The length of the period counted by the CTC is the length of the inactive period Toff.

In addition to the above differences, under the CCM, the control circuit 120 can also switch the pulse width modulation control signal Spwm accurately when the average output current Iavg meets the preset current value by comparing the product signal Sm with the reference voltage Vrefi. Therefore, the effect that the average value of the output current Io in each signal period Tp is stably maintained at the current set value can be achieved as well. For the operation of the remaining circuits, please refer to the description of the foregoing embodiment of FIG. 6, and details are not described herein again.

In summary, the embodiment of the present invention provides a flyback power converter and a control method thereof, which can obtain power conversion by detecting a voltage on an auxiliary winding of a transformer and a voltage associated with an inductor current of a primary side. The operation information of the circuit is determined based on the characteristic that the product of the output current of the reverse power conversion is substantially constant in the product of the average value of the signal period and the length of the disable time, thereby determining the transition time of the pulse width modulation control signal. Therefore, the average output current can be stably maintained at a preset current setting value without generating an unstable drift depending on the load operation condition or the operation of the power conversion circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

50‧‧‧Rectifier circuit
100‧‧‧Return-type power converter
110‧‧‧Power conversion circuit
120‧‧‧Control circuit
122‧‧‧ Pulse width modulation signal generation circuit
124‧‧‧Switch drive circuit
126‧‧‧Average current detection circuit
AAC‧‧‧ accumulator
AC‧‧‧Auxiliary line
ACin‧‧‧AC power supply
C1, Co‧‧‧ capacitor
CTC‧‧‧Timer
COMP‧‧‧ comparator
CV_Toff‧‧‧ count value
D1, D2‧‧‧ diode
DFF1, DFF2‧‧‧ forward and reverse
EA‧‧‧Error Amplifier
GND1, GND2‧‧‧ Ground
INV‧‧‧Inverter
INVC‧‧‧ Inverting Comparator
Ip, Is‧‧‧Inductor Current
Ipp, Isp‧‧‧ peak current
Io‧‧‧ output current
MC‧‧‧ Multiplier
Na‧‧‧Auxiliary winding
Np‧‧‧ primary side winding
Ns‧‧‧ secondary winding
P_DR‧‧‧ drive pin
P_DT1, P_DT2‧‧‧Detection pin
P_VDD‧‧‧ power pin
Pin‧‧‧ input power
Pout‧‧‧Output power supply
R1, R2, R3, Rcs‧‧‧ resistors
S310~S360‧‧‧Return-type power conversion circuit control method steps
Scd‧‧‧current indication signal
Sea‧‧‧Error amplification signal
SHC‧‧‧Sampling and Holding Circuit
SToff‧‧‧Indication signal during the ban period
Spwm‧‧‧ pulse width modulation control signal
SW‧‧‧Power switch
T‧‧‧Transformer
T_pwm‧‧‧cycle signal
TSGC‧‧‧ triangle wave and square wave generating circuit
VDD‧‧‧DC system voltage
V _DET , Vcs‧‧‧ voltage
Vo‧‧‧ output voltage
Vref1, Vref2, Vrefi‧‧‧ reference voltage

1 is a functional block diagram of a flyback power converter according to an embodiment of the invention. 2 is a circuit schematic diagram of a flyback power converter in accordance with an embodiment of FIG. 1. 3 is a flow chart showing the steps of a method for controlling a flyback power conversion circuit according to an embodiment of the present invention. 4 is a functional block diagram of a control circuit according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a circuit architecture of a control circuit in accordance with an embodiment of FIG. FIG. 6 is a timing diagram of signals of a flyback power converter according to an embodiment of the invention. FIG. 7 is a timing diagram of signals of a flyback power converter according to another embodiment of the present invention.

S310~S360‧‧‧Return-type power conversion circuit control method steps

Claims (9)

A flyback power converter includes: a power conversion circuit comprising: a transformer having a primary side winding, a secondary side winding, and an auxiliary winding; and a power switch coupled to the primary side winding, wherein The power switch is controlled by a pulse width modulation control signal, so that the transformer converts an input power on the primary side winding to an output voltage on the secondary side winding in response to switching of the power switch And a control circuit coupled to the power conversion circuit for detecting a first voltage on the auxiliary winding and a second voltage on the power switch, and thereby controlling the operation of the power conversion circuit The control circuit counts an inactive period of the pulse width modulation control signal according to the first voltage and the pulse width modulation control signal, and generates a timing value according to the second voltage, and generates a current according to the second voltage. An indication signal, wherein the control circuit determines the output current to be a signal week of the pulse width modulation control signal according to a product of the count value and the current indication signal An average output current in compliance with a preset current value, whereby judgment based on the result of the decision the duty cycle of the PWM control signal. The flyback power converter of claim 1, wherein the control circuit comprises: a pulse width modulation signal generating circuit for generating the indication according to a preset clock signal and an error amplification signal a one-cycle signal of the duty cycle of the wide-band signal; a switch driving circuit coupled to the pulse width modulation signal generating circuit and the power switch for generating the pulse width modulation control signal according to the periodic signal; and an average An output current detecting circuit is coupled to the pulse width modulation signal generating circuit for counting the disable period according to the first voltage and generating the timing value, and sampling the second voltage to generate the current indicating signal, The average output current detecting circuit multiplies the count value by the current indicating signal to generate a product signal, and the difference between the product signal and a reference voltage is amplified to generate the error amplifying signal. The pulse width modulation signal generating circuit. The flyback power converter of claim 2, wherein when the product signal is equal to the reference voltage, the pulse width modulation signal generating circuit selects the periodic signal from the uniform level according to the error amplification signal Switch to an inactive level. The flyback power converter of claim 2, wherein the average output current detecting circuit comprises: a timer that receives the first voltage and the periodic signal, and enters the disable according to the periodic signal Timing is started to generate the timing value, and the timing value is reset according to the first voltage; a sampling and holding circuit for sampling and maintaining the second voltage during the uniform energy period of the pulse width modulation control signal And generating the current indication signal; a multiplier coupled to the timer and the sample and hold circuit for multiplying the count value by the current indication signal to generate the product signal; and an error An amplifier having a first input coupled to the output of the multiplier to receive the product signal, a second input coupled to the reference voltage, and an output coupled to the pulse width modulation signal generating circuit to provide the error Zoom in on the signal. The flyback power converter of claim 1, wherein the power switch is turned on during a uniform energy period of the pulse width modulation control signal, so that the primary side winding reacts to the turned on power switch. The energy storage device, wherein the control circuit obtains an input voltage information according to the first detection voltage detected during the enabling period. The flyback power converter of claim 5, wherein the power switch is turned off during the disable period, thereby transferring electrical energy stored in the primary side winding to the secondary winding, thereby The secondary winding generates an inductor current, wherein the control circuit obtains an output voltage information according to the first detected voltage detected during the disable period. The flyback power converter of claim 1, wherein the control circuit has a first detecting end, a second detecting end, a power end, and a driving end, the first of the power switches The second end of the power switch is coupled to the second detecting end, and the control end of the power switch is coupled to the driving end. The power conversion circuit further includes: an auxiliary line coupled to the auxiliary winding and the first detecting end for generating a power source according to the input power source, a voltage is supplied to the power terminal, and the first voltage is supplied to the first detecting end; a resistor having a first end coupled to the second end of the power switch and the second detecting end, and a second The end is coupled to a first ground end; an output diode having an anode coupled to the secondary side winding; and an output capacitor having a first end coupled to the second end of the output diode and second The terminal is coupled to a second ground. A control method for a flyback power conversion circuit, wherein the flyback power conversion circuit includes a transformer and a power switch, and the transformer has a primary side winding, a secondary side winding, and an auxiliary winding, the control method The method includes: detecting a first voltage on the auxiliary winding and a second voltage on the power switch; and counting the pulse width modulation according to the first voltage and a pulse width modulation control signal used to control the power switch Controlling a disable period of the signal, and generating a timing value; generating a current indicating signal according to the second voltage; calculating a product of the count value and the current indicating signal; determining the flyback power conversion circuit according to the product Whether an average output current meets a preset current value; and determining a duty cycle of the pulse width modulation control signal according to the judgment result.