TWI784755B - Controller applied to a flyback power converter and operational method thereof - Google Patents

Abstract

A controller applied to a flyback power converter has a new feedback detection function. The controller includes a sample-and-hold circuit and a disable circuit. The sample-and-hold circuit is used for sampling a feedback voltage to generate a sampling voltage, wherein the controller generates a compensation voltage according to the sampling voltage, and an output voltage of a secondary side of the flyback power converter corresponds to the compensation voltage. The disable circuit is used for disabling a sampling signal to make the sample-and-hold circuit stop sampling the feedback voltage according to an input voltage, the sampling voltage, and a peak of a detection voltage.

Description

Controller for flyback power converter and method of operation thereof

The present invention relates to a controller applied to a flyback power converter and its operation method, especially a controller capable of de-sampling signals according to the peak value of input voltage, sampling voltage and detection voltage at the same time and its operation method.

In the prior art, a controller applied to the primary side of a single-stage flyback power factor correction (power factor correction, PFC) power converter receives an input voltage (wherein the input voltage is related to a DC voltage, and the DC The voltage is generated by rectifying an AC voltage through the bridge rectifier included in the single-stage flyback power factor correction power converter), and comparing the input voltage with a threshold voltage, wherein when the input voltage is lower than the threshold When the voltage is high, the sampling signal that can be input to the sampling and holding circuit in the controller is disabled. In this way, the sample-and-hold circuit stops sampling a feedback voltage to generate a sampling voltage until the sampling signal is re-enabled. In addition, the controller can generate a compensation voltage according to the sampling voltage, and adjust the frequency reduction of a gate control signal (controlling a power switch included in the single-stage flyback power factor correction power converter) according to the compensation voltage A frequency variation curve is used to control the output voltage of the secondary side of the single-stage flyback power factor correction power converter.

However, because the sample-and-hold circuit stops sampling the Feedback voltage is used to generate the sampling voltage, so the sampling voltage generated by the sample-and-hold circuit does not change anymore. If the load coupled to the single-stage flyback power factor correction power converter changes or the input voltage changes at this time, since the sampling voltage no longer changes, the compensation voltage related to the sampling voltage cannot be real-time In response to the change of the load or the change of the input voltage, the overshoot/undershoot of the output voltage occurs. Because in the prior art, the threshold voltage is a fixed value, if the threshold voltage is too high, the de-energization interval of the sampling signal becomes too long, resulting in that when the load changes or the input voltage changes, the The overshoot/undershoot of the output voltage will be more serious, even beyond the range that the single-stage flyback power factor correction power converter can regulate the output voltage; if the threshold voltage is too low, because the single-stage flyback power The excitation current of the primary side of the factor correction power converter is too small, so the reflected voltage of the secondary side of the single-stage flyback power factor correction power converter is too low, resulting in an incorrect (low) sampling voltage. In this way, the output voltage becomes higher, and even the single-stage flyback power factor correction power converter oscillates.

Therefore, how to solve the above-mentioned problem caused by the threshold voltage being the fixed value has become an important task for the designer of the controller.

An embodiment of the present invention provides a controller applied to a flyback power converter, wherein the controller has a new feedback detection function. The controller includes a sample hold circuit and a disable circuit. The sample and hold circuit is used to sample a feedback voltage to generate a sample voltage, wherein the controller generates a compensation voltage according to the sample voltage, and the output voltage of the secondary side of the flyback power converter and the compensation voltage related. The disabling circuit is used for disabling a sampling signal according to the peak value of an input voltage, the sampling voltage and a detection voltage so that the sampling and holding circuit stops sampling the feedback voltage.

Another embodiment of the present invention provides an operation method of a controller applied to a flyback power converter, wherein the controller has a new feedback detection function, and the controller includes a sample-and-hold circuit and a disable circuit . The operation method comprises that the disabling circuit determines whether to disable a sampling signal according to the peak value of an input voltage, a sampling voltage, and a detection voltage; and when the disabling circuit disables the sampling signal, the sampling and holding circuit stops Sampling a feedback voltage to generate the sampling voltage until the sampling signal is re-enabled.

The invention provides a controller applied to a flyback power converter, wherein the controller has a new feedback detection function. Because the new feedback detection function enables the controller to simultaneously disable a sampling signal according to the peak values of an input voltage, a sampling voltage and a detection voltage, so compared with the prior art, the present invention has the following advantages: First, because the peak value of the detection voltage changes with the load on the secondary side of the flyback power converter, the controller can detect the secondary side of the flyback power converter through the peak value of the detection voltage. Second, because the sampling voltage can change with the output voltage of the secondary side of the flyback power converter, so the controller can avoid errors in the sampling signal; third, in the control Under the premise that the controller can avoid the error of the sampling signal, the controller detects the load of the secondary side of the flyback power converter and the input voltage, and can effectively reduce the de-energy interval of the sampling signal so that the sampling The de-energy interval of the signal is optimized.

100: flyback power converter

102: The first voltage divider circuit

103: Power switch

104: Bridge rectifier

106: The second voltage divider circuit

200: controller

202: Sample and hold circuit

204: De-energizing circuit

2042: first comparator

2044: Peak Generator

2046: second comparator

2048: The third comparator

2050: Reverse and gate

2052: and gate

FCS: first comparison signal

GND1, GND2: ground potential

GCS: gate control signal

NAUX: auxiliary winding

OS: output signal

PRI: primary side

SEC: Secondary side

SCS: second comparison signal

TCS: third comparison signal

T1-T9: time

VP: Peak

VCS: detection voltage

VCC, FB, GATE, IN, CS, GND, COMP: pins

VAUX: auxiliary voltage

VFB: feedback voltage

VIN: input voltage

VAC: AC voltage

VBRI: DC voltage

VOUT: output voltage

VTH1: the first threshold voltage

VTH2: the second threshold voltage

VTH3: the third critical voltage

VFBSH: sampling voltage

VCOMP: Compensation voltage

VTRI: Sampling signal

VTH1H: upper bound

VTH1L: Lower Bound

300-304: Steps

FIG. 1 is a schematic diagram illustrating a controller applied to a flyback power converter according to the first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the timing sequence of the disable circuit to disable the sampling signal according to the peak values of the input voltage, the sampling voltage and the detection voltage.

FIG. 3 is a flowchart illustrating an operation method of a controller applied to a flyback power converter according to a second embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a controller 200 applied to a flyback power converter (flyback power converter) 100 according to a first embodiment of the present invention, wherein the controller 200 has a new feedback detection Function, the controller 200 is applied to the primary side PRI of the flyback power converter 100 , and the flyback power converter 100 is a single-stage flyback power factor correction (power factor correction, PFC) power converter. In addition, the flyback power converter 100 and the controller 200 in FIG. 1 only show elements related to the present invention, and the ground potential GND1 of the primary side PRI of the flyback power converter 100 and the flyback power converter The ground potential GND2 of the secondary side SEC of 100 may be the same or different. As shown in FIG. 1, the controller 200 includes a sample-and-hold circuit 202 and a disable circuit 204, wherein the sample-and-hold circuit 202 receives a feedback voltage VFB through the pin FB of the controller 200, and is used for sampling the feedback voltage VFB to generate a sampling voltage VFBSH. In addition, as shown in FIG. 1 , the feedback voltage VFB is generated by the auxiliary voltage VAUX on the auxiliary winding NAUX included in the flyback power converter 100 through a first voltage dividing circuit 102 . After the sample-and-hold circuit 202 generates the sampling voltage VFBSH, related circuits in the controller 200 can generate a compensation voltage VCOMP (that is, the voltage on the pin COMP of the controller 200) according to the sampling voltage VFBSH, and adjust a compensation voltage VCOMP according to the compensation voltage VCOMP. The frequency variation curve of the gate control signal GCS is used to control the output voltage VOUT of the secondary side SEC of the flyback power converter 100, that is to say the output of the secondary side SEC of the flyback power converter 100 The voltage VOUT is related to the compensation voltage VCOMP. In addition, the gate control signal GCS is input to a power switch 103 included in the flyback power converter 100 through the pin GATE of the controller 200 , wherein the gate control signal GCS is used to control the power switch 103 is turned on and off, and the flyback power converter 100 is operated in a quasi-resonant mode. In addition, as shown in FIG. 1 , the auxiliary voltage VAUX can be input to the controller 200 through the pin VCC of the controller 200 as the power supply voltage of the controller 200 , and the pin GND of the controller 200 receives the ground potential GND1 .

As shown in FIG. 1 , the disable circuit 204 includes a first comparator 2042 , a peak generator 2044 , a second comparator 2046 , a third comparator 2048 , an NAND gate 2050 and an NAND gate 2052 . The first comparator 2042 is used to receive an input voltage VIN through the pin IN of the controller 200, and when the input voltage VIN is less than a first threshold voltage VTH1, generate a first comparison signal FCS (that is, a first high potential signal), wherein the first comparator 2042 also has a hysteresis function. In addition, as shown in FIG. 1, a DC voltage VBRI is generated by rectifying an AC voltage VAC through the bridge rectifier 104 included in the flyback power converter 100, and the input voltage VIN is generated by passing the DC voltage VBRI through a second divider. generated by voltage circuit 106. The peak value generator 2044 is used to receive a detection voltage VCS through the pin CS of the controller 200 and thereby generate the peak value VP of the detection voltage VCS; the second comparator 2046 is used to receive the peak value VP and when the peak value VP is less than a first When the threshold voltage VTH2 is reached, a second comparison signal SCS (that is, a second high potential signal) is generated. The third comparator 2048 is used for receiving the sampling voltage VFBSH and generating a third comparison signal TCS (ie, a third high potential signal) when the sampling voltage VFBSH is smaller than a third threshold voltage VTH3 . The NAND gate 2050 is used to receive the first comparison signal FCS, the second comparison signal SCS and the third comparison signal TCS, and generate an output signal OS (ie, a first low level signal) accordingly. Because the output signal OS is the first low potential signal, the AND gate 2052 can disable the sampling signal VTRI according to the output signal OS, that is to say, when the AND gate 2052 receives the output signal OS, the sampling signal VTRI will not pass through the AND gate. 2052 to the sample and hold circuit 202 (the output of the AND gate 2052 is at a low potential at this moment). When the sample and hold circuit 202 does not receive the sampling signal VTRI, the sample and hold circuit 202 will stop sampling the feedback voltage VFB, and the sample and hold circuit 202 will maintain the previously generated sampling voltage VFBSH until the sampling signal VTRI is disabled. Interval ends. In addition, the present invention is not limited to the fact that the first comparison signal FCS is the first high potential signal, the second comparison signal SCS is the second high potential signal, the third comparison signal TCS is the third high potential signal, and the output signal OS is the first low potential signal, the NAND gate 2050 and the AND gate 2052, that is to say, as long as the disabling circuit 204 can use the input voltage VIN, the sampling voltage VFBSH, the peak value VP of the detection voltage VCS and the logic gate to disabling sampling The signal VTRI falls within the scope of the present invention.

In addition, please refer to FIG. 2 . FIG. 2 is a schematic diagram illustrating the timing sequence of the disabling circuit 204 disabling the sampling signal VTRI according to the peak value VP of the input voltage VIN, the sampling voltage VFBSH and the detection voltage VCS. As shown in FIG. 2, between time T0 and a time T1, between a time T2 and a time T3, and between a time T4 and a time T5, the input voltage VIN is less than the first threshold voltage VTH1 (wherein VTH1H is The upper boundary of the hysteresis interval corresponding to the first threshold voltage VTH1 and VTH1L is the lower boundary of the hysteresis interval corresponding to the first threshold voltage VTH1). Likewise, between time T0 and time T1 , between time T2 and time T3 , and between time T4 and time T5 , the peak value VP is also smaller than the second threshold voltage VTH2 . In addition, between time T0 and time T6 , between time T7 and time T8 , and between time T9 and time T5 , the sampling voltage VFBSH is smaller than the third threshold voltage VTH3 . As shown in Figure 2, only between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, the input voltage VIN is less than the first critical voltage VTH1, and the peak value VP is less than the second critical voltage VTH2, and the sampling voltage VFBSH less than the third threshold voltage VTH3 will occur at the same time, that is to say, only between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, the first comparator 2042, the second comparator 2046 and the third comparator 2048 respectively generate the first high potential signal, the second high potential signal and the third high potential signal at the same time. Because of the characteristics of the NAND gate 2050, the NAND gate 2050 will only generate the output signal OS between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5 (that is, the first low level signal). Therefore, because the NAND gate 2050 will only generate the output signal OS between the time T0 and the time T6, between the time T7 and the time T8, and between the time T9 and the time T5 (that is, the first A low potential signal), so the disabling circuit 204 will pass through the AND gate 2052 and the output signal OS to disabling sampling only between the time T0 and the time T6, between the time T7 and the time T8, and between the time T9 and the time T5 The signal VTRI, that is to say, the sample and hold circuit 202 will stop sampling the feedback voltage VFB between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, and maintain the current sampling voltage VFBSH, The period between time T0 and time T6 , between time T7 and time T8 , and between time T9 and time T5 is the de-energization interval of the sampling signal VTRI. In addition, as shown in Figure 2, the sample-and-hold circuit 202 can still sample feedback between time T6 and time T1, between time T2 and time T7, between time T8 and time T3, and between time T4 and time T9. Voltage VFB.

Because the disable circuit 204 can simultaneously disable the sampling signal VTRI according to the peak value VP of the input voltage VIN, the sampling voltage VFBSH, and the detection voltage VCS, so compared with the prior art, the present invention has the following advantages: First, because when the flyback When the load (not shown in FIG. 1 ) of the secondary side SEC of the type power converter 100 changes, the peak value VP of the detection voltage VCS will also change accordingly, so the disabling circuit 204 can pass the peak value of the detection voltage VCS VP detects the load change of the secondary side SEC of the flyback power converter 100; second, because the sampling voltage VFBSH can change with the output voltage VOUT, the disabling circuit 204 can avoid the error of the sampling signal VTRI; third, On the premise that the disabling circuit 204 can avoid errors in the sampling signal VTRI, detecting the load of the secondary side SEC of the flyback power converter 100 and the input voltage VIN can effectively reduce the disabling interval of the sampling signal VTRI so that The de-energy interval of the sampled signal VTRI is optimized. Therefore, compared with the prior art, the present invention can simultaneously meet the specification requirements of the voltage regulation rate<±5% and the dynamic rate of the load of the secondary side SEC<±13%.

Please refer to FIGS. 1-3 . FIG. 3 is a flow chart illustrating an operation method of a controller applied to a flyback power converter according to a second embodiment of the present invention. The operation method in Fig. 3 is explained by using the power converter 100 and the controller 200 in Fig. 1, and the detailed steps are as follows: Step 300: Start; Step 302: Whether the disable circuit 204 disables the sampling signal VTRI; If yes, proceed to Step 304; If not, proceed to Step 302; Step 304: The sampling and holding circuit 202 stops sampling the feedback voltage VFB to generate the sampling voltage VFBSH until the sampling signal VTRI is enabled again, then jump back to step 302 .

In step 302 , when the sampling signal VTRI is not disabled by the disabling circuit 204 , the sample and hold circuit 202 can sample the feedback voltage VFB to generate the sampling voltage VFBSH. In addition, as shown in Figure 2, only between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, the input voltage VIN is less than the first threshold voltage VTH1, and the peak value VP is less than the second The critical voltage VTH2 and the sampling voltage VFBSH will be less than the third critical voltage VTH3 at the same time, that is to say, only between the time T0 and the time T6, between the time T7 and the time T8, and between the time T9 and the time T5, the first The comparator 2042 , the second comparator 2046 and the third comparator 2048 respectively generate the first high potential signal, the second high potential signal and the third high potential signal at the same time. That is to say, the NAND gate 2050 will generate the output signal OS (that is, the first low potential signal) only between the time T0 and the time T6, between the time T7 and the time T8, and between the time T9 and the time T5. Therefore, because the NAND gate 2050 will only generate the output signal OS (that is, the first low potential signal) between the time T0 and the time T6, between the time T7 and the time T8, and between the time T9 and the time T5, so The disable circuit 204 disables the sampling signal VTRI through the AND gate 2052 and the output signal OS only between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5.

In step 304, the sample and hold circuit 202 will stop sampling the feedback voltage VFB between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, and maintain the current The voltage VFBSH is sampled until the sampling signal VTRI is re-enabled. In addition, as shown in Figure 2, the sample-and-hold circuit 202 can still sample feedback between time T6 and time T1, between time T2 and time T7, between time T8 and time T3, and between time T4 and time T9. Voltage VFB.

In summary, the controller provided by the present invention has a new feedback detection function. Because the new feedback detection function is to enable the disabling circuit in the controller to simultaneously disable the sampling signal according to the peak value of the input voltage, the sampling voltage and the detection voltage, so compared with the prior art, this The invention has the following advantages: First, because the peak value of the detection voltage changes with the load on the secondary side of the flyback power converter, the controller can detect the flyback power converter through the peak value of the detection voltage The load variation of the secondary side of the power converter; second, because the sampling voltage can change with the output voltage of the secondary side of the flyback power converter, so the controller can avoid the error of the sampling signal; the second 3. On the premise that the controller can avoid the error of the sampling signal, the controller detects the load on the secondary side of the flyback power converter and the input voltage, which can effectively reduce the de-energy of the sampling signal interval to optimize the de-energized interval of the sampled signal.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: flyback power converter

102: The first voltage divider circuit

103: Power switch

104: Bridge rectifier

106: The second voltage divider circuit

200: controller

202: Sample and hold circuit

204: De-energizing circuit

2042: first comparator

2044: Peak Generator

2046: second comparator

2048: The third comparator

2050: Reverse and gate

2052: and gate

FCS: first comparison signal

GND1, GND2: ground potential

GCS: gate control signal

NAUX: auxiliary winding

OS: output signal

PRI: primary side

SEC: Secondary side

SCS: second comparison signal

TCS: third comparison signal

VP: Peak

VCS: detection voltage

VCC, FB, GATE, IN, CS, GND, COMP: pins

VAUX: auxiliary voltage

VFB: feedback voltage

VIN: input voltage

VAC: AC voltage

VBRI: DC voltage

VOUT: output voltage

VTH1: the first threshold voltage

VTH2: the second threshold voltage

VTH3: the third threshold voltage

VFBSH: sampling voltage

VCOMP: Compensation voltage

VTRI: Sampling signal

Claims (13)

A controller applied to a flyback power converter, wherein the controller has a new feedback detection function, the controller includes: a sample and hold circuit for sampling a feedback voltage to generate a sampling voltage, wherein the controller generates a compensation voltage according to the sampling voltage, and the output voltage of the secondary side of the flyback power converter is related to the compensation voltage; and an energy-disabling circuit, comprising: a first comparator , used to receive an input voltage and generate a first comparison signal when the input voltage is less than a first threshold voltage, wherein the first comparator has a hysteresis function; and a peak value generator, used to receive a detection voltage And accordingly generate a peak value of the detection voltage; wherein the disabling circuit disables a sampling signal according to the input voltage, the sampling voltage and the peak value of the detection voltage so that the sample and hold circuit stops sampling the feedback voltage. The controller as claimed in item 1, wherein the controller is applied to the primary side of the flyback power converter, and the flyback power converter is a single-stage flyback power factor correction (power factor correction, PFC) power converter. The controller as claimed in claim 1, wherein the feedback voltage is related to an auxiliary voltage on an auxiliary winding included in the flyback power converter. The controller as claimed in claim 1, wherein the supply voltage of the controller is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter. The controller as claimed in claim 1, wherein the input voltage is related to a DC voltage, and the DC voltage is generated by rectifying an AC voltage by a bridge rectifier included in the flyback power converter. The controller as described in claim 1, wherein the disable circuit includes: a second comparator for receiving the peak value of the detection voltage and generating a voltage when the peak value of the detection voltage is less than a second threshold voltage A second comparison signal; a third comparator for receiving the sampling voltage and generating a third comparison signal when the sampling voltage is less than a third threshold voltage; an NAND gate for receiving the first comparison signal , the second comparison signal and the third comparison signal, and generate an output signal accordingly; and an AND gate, used to disable the sampling signal according to the output signal. A method for operating a controller applied to a flyback power converter, wherein the controller has a new feedback detection function, and the controller includes a sample-and-hold circuit and a disabling circuit, the operation The method includes: when an input voltage is less than a first critical voltage, a first comparator of the disabling circuit generates a first comparison signal; when a peak value of a detection voltage is less than a second critical voltage, the disabling A second comparator of the circuit generates a second comparison signal; when a sampling voltage is less than a third critical voltage, a third comparator of the disabling circuit generates a third comparison signal; the disabling circuit generates a third comparison signal according to the first A comparison signal, the second comparison signal and the third comparison signal determine Determine whether to disable a sampling signal; and when the disabling circuit disables the sampling signal, the sample hold circuit stops sampling a feedback voltage to generate the sampling voltage until the sampling signal is enabled again. The operation method as claimed in claim 7, wherein the controller generates a compensation voltage according to the sampled voltage, and the output voltage of the secondary side of the flyback power converter is related to the compensation voltage. The operation method as claimed in item 7, wherein the controller is applied to the primary side of the flyback power converter. The operation method as claimed in claim 7, wherein the feedback voltage is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter. The operation method as claimed in item 7, wherein the power supply voltage of the controller is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter. The operation method as claimed in claim 7, wherein the input voltage is related to a DC voltage, and the DC voltage is generated by rectifying an AC voltage through a bridge rectifier included in the flyback power converter. The operation method as described in claim item 7, wherein the disabling circuit determines whether to disable the sampling signal according to the first comparison signal, the second comparison signal and the third comparison signal includes: according to the first comparison signal, The second comparison signal and the third comparison signal generate an output signal number; and deactivate the sampled signal according to the output signal.

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