TWI547983B - Semiconductor device and method of fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

With the integration of semiconductor elements, in order to achieve high density and high performance, when manufacturing semiconductor elements, it tends to form an upward stacked structure to more effectively utilize the wafer area. Therefore, high aspect ratio semiconductor structures or openings often occur in small size components.

In the fabrication of the above components, in order to form trenches having a high aspect ratio, a very high etching selectivity is typically employed for the patterning process. However, in the case of using a very high etching selectivity ratio, there is a problem that the material layer on the sidewall of the trench cannot be completely removed. When a material layer remains on the sidewall of the trench and the material layer is a conductor, improper conduction occurs between the semiconductor elements, and the electrical performance of the device is deteriorated. Therefore, how to pattern a material layer (conductor layer) in a semiconductor structure having a trench having a high aspect ratio without leaving a material layer on the sidewall of the trench is a subject of current research.

The present invention provides a method of fabricating a semiconductor device in which a material layer (conductor layer) is patterned in a semiconductor structure having a trench having a high aspect ratio so that a sidewall of the trench does not leave a material layer or a material layer remains.

The present invention provides a method of manufacturing a semiconductor device. The above method of manufacturing a semiconductor element includes the following steps. A plurality of fin structures are formed on the substrate, and openings between the adjacent fin structures are provided. A layer of conductive material is formed to cover the fin structure and fill the opening. The conductor material layer and the fin structure are patterned to form a mesh structure. The mesh structure has a plurality of first strips extending in a first direction and a plurality of second strips extending in a second direction. The first strip intersects the second strip, and the mesh structure has a plurality of holes. The first strip is located on the substrate and is located at a position corresponding to the fin structure. The second strip is located on the substrate and the conductive material layer of the second strip spans the fin structure. The hole is located in the opening, and the first strip and the second strip are surrounded by the hole, and the hole extends to a position closer to the base than the bottom of the fin structure.

In an embodiment of the invention, the step of patterning the conductive material layer and the fin structure includes performing a non-selective etching process.

In an embodiment of the invention, the etching selectivity ratio between the conductor material layer and the fin structure is controlled to be 0.7 to 1.3 to perform the non-selective etching process.

In an embodiment of the invention, the step of forming the fin structure includes the following steps. A stacked layer is formed on the above substrate. The stacked layer includes at least one conductor layer and at least one dielectric layer that are alternately stacked. A charge storage layer is formed to cover the above-mentioned substrate at the bottom of the above opening and the surface of the above stacked layer.

In an embodiment of the invention, the method of manufacturing the semiconductor device further includes the following steps. A plurality of dielectric posts are formed to fill at least the holes. The conductor material layer and the dielectric post in the first strip are patterned such that the patterned conductor material layer forms a plurality of comb structures. Each comb structure includes a plurality of comb portions and a connecting portion. The comb portion is inserted into the opening between the adjacent fin structures and is in contact with a side wall of the adjacent fin structure. The connecting portion extends in the second direction and is located on the fin structure and connected to the comb portion.

In an embodiment of the invention, the step of forming the dielectric post and patterning the conductive material layer and the dielectric post in the first strip includes the following steps. A layer of dielectric material is formed to cover the mesh structure and fill the holes. The dielectric material layer and the conductive material layer in the first strip are patterned to form the comb structure, the plurality of cap layers, and the dielectric post. Each of the comb structures includes the above comb portion and the above connecting portion. Each of the cap layers is located on the connecting portion and extends along the second direction.

The invention further provides a semiconductor component. The above semiconductor element includes a substrate, a plurality of fin structures, a plurality of comb structures, and a plurality of dielectric posts. The fin structure is located on the substrate and extends in the first direction. An adjacent opening between the fin structures is provided. The comb structure includes a conductor material, and each of the comb structures includes a plurality of combs and a joint. The comb portion is inserted into the opening between the adjacent fin structures and is in contact with a side wall of the adjacent fin structure. The connecting portion extends in the second direction and is located on the fin structure and connected to the comb portion. The dielectric post is inserted into the opening between the adjacent fin structures and is in contact with the sidewall of the adjacent fin structure and the comb portion, and extends closer to the base than the bottom of the fin structure position.

In an embodiment of the invention, the fin structure includes a stacked layer and a charge storage layer. The stacked layer includes at least a conductor layer and at least a dielectric layer that are alternately stacked. The charge storage layer covers the substrate at the bottom of the opening and the surface of the stacked layer.

In an embodiment of the invention, each dielectric post has a different height.

In an embodiment of the invention, the height of each dielectric post is greater than the height of each fin structure.

Based on the above, the present invention can simultaneously pattern the fin structure and the material layer (conductor layer) and form a network structure, and in the semiconductor structure of the trench having a high aspect ratio, the sidewall of the trench does not have a material layer remaining. Patterning of the material layer (conductor layer) is performed. Such a method can effectively prevent improper conduction between the formed semiconductor elements, thereby improving the electrical performance of the elements.

The above described features and advantages of the invention will be apparent from the following description.

1A-1F are perspective views of a method of fabricating a semiconductor device in accordance with an embodiment of the invention. 2A to 2F are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line A-A' of Figs. 1A to 1F. 3A to 3F are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line B-B' of Figs. 1A to 1F. 4A to 4F are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line C-C' of Figs. 1A to 1F.

Referring to FIG. 1A, FIG. 2A, FIG. 3A, and FIG. 4A simultaneously, the substrate 10 is first provided. Substrate 10 can comprise a semiconductor material, an insulator material, a conductor material, or any combination of the foregoing. The material of the substrate 10 is, for example, a material selected from at least one selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, or any suitable material for use in the process of the present invention. Physical structure. The substrate 10 includes a single layer structure or a multilayer structure. In addition, a silicon on insulator (SOI) substrate 10 can also be used. The substrate 10 is, for example, tantalum or niobium.

Referring to FIG. 1A, FIG. 2A, FIG. 3A, and FIG. 4A simultaneously, a dielectric layer 12 is formed on the substrate 10. The dielectric layer 12 includes an oxide, a nitride, an oxynitride or a low dielectric constant material having a dielectric constant of less than 4. In an embodiment, the dielectric layer 12 is, for example, a bottom oxide layer (BOX). The thickness of the dielectric layer 12 is, for example, between 1000 Å and 5000 Å. The method of forming the dielectric layer 12 is, for example, a thermal oxidation method or a chemical vapor deposition method.

Referring again to FIGS. 1A, 2A, 3A, and 4A, a stacked layer 16 is then formed over the dielectric layer 12. The stacked layer 16 includes a plurality of electrically conductive layers 16a and a plurality of dielectric layers 16b that are alternately stacked. The material of the conductor layer 16a includes an undoped semiconductor or a doped semiconductor such as polysilicon or doped polysilicon. The thickness of each conductor layer 16a is, for example, between 100 Å and 500 Å. The thickness of each dielectric layer 16b is, for example, between 200 Å and 600 Å. The material of the dielectric layer 16b may be the same as or different from the material of the dielectric layer 12. The material of the dielectric layer 16b may include an oxide, a nitride, an oxynitride or a low dielectric constant material having a dielectric constant of less than 4. The method of forming the conductor layer 16a and the dielectric layer 16b is, for example, a thermal oxidation method or a chemical vapor deposition method.

Referring to FIG. 1A, FIG. 2A, FIG. 3A and FIG. 4A simultaneously, a charge storage layer 18 is formed to cover the surface of the stacked layer 16 and the surface of the dielectric layer 12 to form a plurality of fin structures 14. The material of the charge storage layer 18 includes an oxide, a nitride, or a combination thereof. Specifically, the material of the charge storage layer 18 includes tantalum nitride, tantalum oxide, or a combination thereof. The charge storage layer 18 can be a single layer or multiple layers. In an embodiment, the charge storage layer 18 is, for example, a single layer of tantalum nitride layer. In another embodiment, the charge storage layer 18 is, for example, a composite layer composed of an Oxide-Nitride-Oxide (ONO) layer. The thickness of the charge storage layer 18 is, for example, between 100 Å and 300 Å. The method of forming the charge storage layer 18 is, for example, a chemical vapor deposition method or a thermal oxidation method.

Referring to FIG. 1A, FIG. 2A, FIG. 3A, and FIG. 4A simultaneously, the adjacent fin structures 14 have openings T therebetween. The opening T can be an opening of any length, width, shape. The cross section of the opening T may be any shape, for example, a V shape, a U shape, a diamond shape or a combination thereof, but the invention is not limited thereto.

Referring to FIG. 1A, FIG. 2A, FIG. 3A and FIG. 4A simultaneously, in an embodiment, each of the fin structures 14 may optionally further include a first hard mask layer 20. The first hard mask layer 20 is, for example, located between the stacked layer 16 and the charge storage layer 18, but the invention is not limited thereto. The first hard mask layer 20 can be a single layer or multiple layers. The material of the first hard mask layer 20 is, for example, tantalum oxide, tantalum nitride or other material having a high Young's modulus. The thickness of the first hard mask layer 20 is, for example, between 100 Å and 1000 Å. The method of forming the first hard mask layer 20 is, for example, a chemical vapor deposition method.

Referring to FIGS. 1A, 1B, 2B, 3B, and 4B, a conductive material layer 22 is formed to cover the surface of the charge storage layer 18 and the dielectric layer 12 covering the fin structure 14, and fill the opening T. The conductor material layer 22 comprises an undoped semiconductor or a doped semiconductor, such as a polysilicon or a doped polysilicon. The thickness of the layer of conductor material 22 on top of the fin structure 14 is, for example, between 500 Å and 1500 Å. The method of forming the conductor material layer 22 is, for example, a chemical vapor deposition method.

Referring to FIG. 1C, FIG. 2C, FIG. 3C, and FIG. 4C simultaneously, a mask structure 24 is formed on the conductor material layer 22. The mask structure 24 includes, for example, a first advanced patterning film (APF) 24a, a dielectric anti-reflective coating film (DARC) 24b, a second advanced patterned film 24c, and the like. A silicon-containing hard-mask bottom anti-reflection coating (SHB) and a patterned photoresist layer 24e are provided. The material of the first advanced patterned film 24a is, for example, amorphous carbon. The material of the dielectric anti-reflection layer 24b is, for example, bismuth oxynitride. The material of the second advanced patterned film 24c is, for example, amorphous carbon. The material of the anti-reflective layer 24d containing the hard mask bottom is, for example, an organosilicon polymer, a polysilane or a combination thereof. The material of the patterned photoresist layer 24e is, for example, a positive photoresist, a negative photoresist, or a combination thereof. The thickness of the first advanced patterned film 24a is, for example, between 4,000 Å and 15,000 Å. The thickness of the dielectric anti-reflection layer 24b is, for example, between 300 Å and 2000 Å. The thickness of the second advanced patterned film 24c is, for example, between 500 Å and 4,000 Å. The thickness of the anti-reflective layer 24d at the bottom of the ruthenium-containing hard mask is, for example, between 200 Å and 1000 Å. The thickness of the patterned photoresist layer 24e is, for example, between 200 Å and 3,000 Å. The first advanced patterned film 24a, the dielectric anti-reflective layer 24b, the second advanced patterned film 24c, and the ruthenium-containing hard mask bottom anti-reflective layer 24d are formed, for example, by chemical vapor deposition. The method of forming the patterned photoresist layer 24e is, for example, a spin coating method in combination with a lithography process. In an embodiment, the planarization process of the conductive material layer 22 may be performed prior to forming the mask structure 24 to facilitate subsequent patterning processes.

Referring to FIG. 1C, FIG. 1D, FIG. 2D, FIG. 3D and FIG. 4D, the mask structure 24 is used as a mask to perform a non-selective etching process, patterning the conductive material layer 22 and removing a portion of the charge storage layer 18 The dielectric layer 12 is also formed to form the mesh structure 26. By non-selective etching process is meant etching the conductor material layer 22, the charge storage layer 18, and the dielectric layer 12 at substantially equal etch rates. In one embodiment, the etch selectivity ratio of the conductor material layer 22 to the charge storage layer 18 and the conductor material layer 22 to the dielectric layer 12 is, for example, 0.7 to 1.3. Although the range of the etching selection ratio is enumerated above, the present invention is not limited thereto. As long as it can be ensured that the conductor material layer 22 on the side wall of the opening for forming the isolation structure can be completely removed, it can be arbitrarily adjusted to a desired etching selectivity ratio. The non-selective etching process is, for example, a dry etching method. The dry etching method may be sputtering etching, reactive ion etching, or the like. In one embodiment, the gases used in the non-selective etching process are, for example, NF ₃ , HBr, CH ₄ , N ₂ , He, Ar, SF ₆ , CH ₂ F _{2 ,} and CH ₃ F.

Referring again to FIGS. 1D, 2D, 3D, and 4D, the mask structure 24 is removed and the mesh structure 26 is exposed. The mesh structure 26 has a plurality of first strips 26a and a plurality of second strips 26b that intersect. More specifically, the first strip 26a extends in the first direction D1 and is located at a position corresponding to the fin structure 14. That is, each of the first strips 26a includes a fin structure 14 and a first strip conductor layer 25a on the fin structure 14. The second strip 26b extends in the second direction D2 and is located on the substrate 10, and the second strip conductor layer 25b in the second strip 26b spans the fin structure 14. That is, each second strip 26b includes a portion of the fin structure 14 and a second strip conductor layer 25b that spans the fin structure 14. The first strip conductor layer 25a and the second strip conductor layer 25b are patterned by the conductor material layer 22 in FIGS. 1C, 2C, 3C, and 4C. The first strip conductor layer 25a and the second strip conductor layer 25b cross each other to form the mesh layer 25.

In other words, the mesh structure 26 has a plurality of holes P. The circumference of the hole P is surrounded by a first strip 26a and a second strip 26b. The hole P is located in the opening T between the adjacent two fin structures 14 (please refer to FIG. 1A and FIG. 1D simultaneously). Moreover, the hole P extends into the dielectric layer 12 below the charge storage layer 18, that is, the bottom of the hole P to be closer to the substrate 10 than the bottom of the fin structure 14. The method of removing the mask structure 24 is, for example, a dry etching method. The dry etching method may be sputtering etching, reactive ion etching, or the like.

Since the mesh structure 26 is formed by performing a non-selective etching process, the conductive material layer 22 can be effectively prevented or reduced from remaining on the sidewalls of the openings for forming the isolation structure, thereby preventing the formation of the formed semiconductor elements. Improper conduction. In addition, since the conductor material layer 22 is patterned into the mesh layer 25, sufficient supporting force can be imparted in both directions, thereby preventing the pattern from collapsing.

Referring to FIGS. 1C and 1D, FIG. 2D, FIG. 3D, and FIG. 4D simultaneously, the distance between the adjacent two holes P in the first direction D1 is, for example, between 200 Å and 400 Å. The spacing of the adjacent two holes P in the second direction D2 is, for example, between 200 Å and 400 Å. P, for example, area of the void is between 5000nm ² to 10000nm ^2. The shape of the hole P is, for example, a circle, a square, a diamond, or a combination thereof. Although the shape, the area, the pitch, and the like of the hole P are listed above, the present invention is not limited thereto. The hole P may have any shape, area, and pitch as long as it can be ensured that the conductor material layer 22 on the side wall of the opening for forming the isolation structure (i.e., the hole P) can be completely removed.

Referring again to FIGS. 1C and 1D, FIG. 2D, FIG. 3D, and FIG. 4D, in one embodiment, the sidewall of each first strip 26a is inclined from the sidewall of each second strip 26b. More specifically, the first angle A1 of each of the first strips 26a may be smaller than the second angle A2 of each of the second strips 26b. The first angle A1 is an angle between the side wall of the first strip 26a at the bottom of the hole P and the surface of the substrate 10. The second angle A2 is the angle between the side wall of the second strip 26b at the bottom of the hole P and the surface of the substrate 10.

Referring to FIG. 1D, FIG. 2D, FIG. 3D, and FIG. 4D simultaneously, during the etching process, the degree of etching is uneven due to the loading effect, resulting in the formed mesh structure 26. The height H3 of the side walls of the plurality of holes P may not be completely the same, but since the holes P are filled with a dielectric material in a subsequent process, even if the height H3 of each hole P is different, the entire component is not affected. Electrical performance. In an embodiment, the heights H3 of the sidewalls of the plurality of holes P of the mesh structure 26 are different. In yet another embodiment, the height H3 of the sidewall of each of the holes P of the mesh structure 26 is greater than the height H of the first strip 26a. For example, the height H3 of the side wall of each hole P of the mesh structure 26 exceeds 30% or more of the height H of the first strip 26a, or is 40% or more. In an embodiment, the height H3 of the side wall of the hole P is, for example, between 7000 Å and 12000 Å. The height H3 of the side wall of each hole P of the mesh structure 26 exceeds the height H 1000 Å to 5000 Å of the first strip 26a. By setting the height H3 of the side wall of each hole P of the mesh structure 26 to be more than 30% of the height H of the first strip 26a, the conductor material on the side wall of the opening for forming the isolation structure can be more ensured. Layer 22 can be completely removed.

Referring to FIG. 1E, FIG. 2E, FIG. 3E, and FIG. 4E simultaneously, a dielectric material layer 28a covering the mesh structure 26 and filling the holes P is formed. The material of the dielectric material layer 28a includes an oxide, a nitride, an oxynitride or a low dielectric constant material having a dielectric constant of less than 4. The thickness of the dielectric material layer 28a on the mesh structure 26 is, for example, between 200 Å and 1000 Å. The method of forming the dielectric material layer 28a is, for example, a chemical vapor deposition method.

Referring to FIG. 1D, FIG. 1E and FIG. 1F, FIG. 2F, FIG. 3F and FIG. 4F, a patterning process, such as a lithography and etching process, is performed to pattern the dielectric material layer 28a and the mesh structure 26, thereby forming A plurality of comb structures 30 and dielectric posts 28. More specifically, by the above-described patterning process, the cap layer 28b on the surface of the second strip 26b and the dielectric post 28 located in the hole P are left. The top cover layer 28b is located on the connecting portion 30b and extends along the second direction D2. Moreover, by the patterning process described above, the first strip 26a of the mesh structure 26 is partially removed leaving the comb structure 30. Each of the comb structures 30 includes a plurality of comb portions 30a and a connecting portion 30b. Each comb portion 30a is inserted into the opening T between the adjacent two fin structures 14 and is in contact with the sidewall of the charge storage layer 18 in the adjacent fin structure 14 (please refer to FIGS. 1A and 1F). The connecting portion 30b connects the comb portion 30a and extends in the second direction D2. In an embodiment, the length of the connecting portion 30b in the first direction D1 is, for example, between 400 Å and 600 Å. In an embodiment, the spacing between the connecting portions 30b is, for example, between 200 Å and 400 Å. In an embodiment, the length W1 of the connecting portion 30b in the first direction D1 is smaller than the length W2 of each dielectric post 28 in the first direction D1.

Further, during the above-described patterning process, after the cap layer 28b and the comb structure 30 are formed, over-etching may be performed to remove a portion of the fin structure 14 between the cap layers 28b. Therefore, the height (first height H1) of each fin structure 14 between adjacent two comb structures 30 may be lower than the height of each fin structure 14 below each comb structure 30 (the Two heights H2). In an embodiment, the first height H1 is less than 500 Å to 1000 Å less than the second height H2. Due to the load effect, the conductor material between the adjacent two comb structures 30 may be incompletely removed, but by over etching and removing the fin structure between the cap layers 28b. A part of 14 can ensure that after the above-mentioned patterning process, the adjacent two comb-like structures 30 are not electrically connected to each other due to the residual of the conductor material.

1F, 2F, 3F, and 4F, the semiconductor device of the present invention includes a substrate 10, a dielectric layer 12, a plurality of fin structures 14, a plurality of comb structures 30, and a plurality of dielectric posts 28. The dielectric layer 12 is on the substrate 10. A plurality of fin structures 14 are located on the dielectric layer 12 and extend in the first direction D1. The fin structure 14 includes a stacked layer 16 and a charge storage layer 18. The stacked layer 16 includes a plurality of conductor layers 16a and a plurality of dielectric layers 16b that are alternately stacked. There are openings T between adjacent fin structures 14. A charge storage layer 18 overlies the surface of the stacked layer 16 and the dielectric layer 12.

Referring to FIG. 1F, FIG. 2F, FIG. 3F, and FIG. 4F simultaneously, the comb structure 30 may be a conductor material. Each of the comb structures 30 includes a plurality of comb portions 30a and a connecting portion 30b. A plurality of comb portions 30a are inserted into the opening T between the adjacent two fin structures 14 and are in contact with the sidewalls of the charge storage layer 18 in the adjacent fin structures 14. The connecting portion 30b extends in the second direction D2 and is located on the charge storage layer 18 and connected to the comb portion 30a.

A plurality of dielectric posts 28 are inserted into the opening T between the adjacent two fin structures 14 and are in contact with the sidewalls of the adjacent fin structures 14 and the comb portions 30a of the comb structure 30, and extend to the fins Structure 14 is closer to the location of substrate 10 (i.e., dielectric post 28 extends into dielectric layer 12 below charge storage layer 18). The height H3 of the plurality of dielectric posts 28 may not be identical. In an embodiment, the heights H3 of the plurality of dielectric posts 28 are different. In another embodiment, the height H3 of each dielectric post 28 is greater than the height H1 of the fin structure 14. For example, the height H3 of each dielectric post 28 exceeds 30% or more of the height H1 of the fin structure 14, or is 40% or more.

In an embodiment, the sidewalls of each fin structure 14 may be inclined relative to the sidewalls of each comb portion 30a. More specifically, the first angle A1 of each of the fin structures 14 (i.e., the charge storage layer 18) is smaller than the second angle A2 of each of the comb portions 30a. The first angle A1 is the angle between the side wall of each fin structure 14 and the surface of the substrate 10, and the second angle A2 is the angle between the side wall of each comb portion 30a and the surface of the substrate 10. The length W1 of each of the connecting portions 30b in the first direction D1 may be different from the length W2 of each of the dielectric posts 28 in the first direction D1. In an embodiment, the length W1 of each of the connecting portions 30b in the first direction D1 is smaller than the length W2 of each of the dielectric posts 28 in the first direction D1.

Referring to FIG. 1F, FIG. 2F, FIG. 3F and FIG. 4F simultaneously, the height of each fin structure 14 in the first direction D1 may be different. In an embodiment, the first height H1 of a portion of each fin structure 14 is lower than the second height H2 of another portion of each fin structure 14. The first height H1 is the height of each fin structure 14 between the adjacent two comb structures 30. The second height H2 is the height of each fin structure 14 located below each comb structure 30.

Referring again to FIGS. 1F, 2F, 3F, and 4F, the semiconductor device of the present invention may further include a plurality of cap layers 28b. A plurality of cap layers 28b are located on the connecting portion 30b of the comb structure 30 and extend along the second direction D2.

In summary, in the embodiment of the present invention, by performing a non-selective etching process and forming a mesh structure, the material layer remaining on the sidewall of the trench can be effectively removed, thereby preventing improper conduction between the formed semiconductor elements. In addition, since the conductor material layer is patterned into a mesh shape, sufficient supporting force can be imparted in both directions, thereby preventing the pattern from collapsing.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base
12, 16b‧‧‧ dielectric layer
14‧‧‧Fin structure
16‧‧‧Stacking
16a‧‧‧Conductor layer
18‧‧‧Charge storage layer
20‧‧‧First hard mask layer
22‧‧‧Conductor layer
24‧‧‧ Cover structure
24a‧‧‧First advanced patterned film
24b‧‧‧Dielectric anti-reflection layer
24c‧‧‧Second advanced patterned film
24d‧‧‧Anti-reflective layer at the bottom of the hard mask
24e‧‧‧ patterned photoresist layer
25‧‧‧ mesh layer
25a‧‧‧First strip conductor layer
25b‧‧‧Second strip conductor layer
26‧‧‧Mesh structure
26a‧‧‧first article
26b‧‧‧Second article
28‧‧‧ dielectric column
28a‧‧‧ dielectric material layer
30‧‧‧Comb structure
30a‧‧‧Comb
30b‧‧‧Connecting Department
28b‧‧‧Top cover
A1‧‧‧ first angle
A2‧‧‧second angle
D1‧‧‧ first direction
D2‧‧‧ second direction
H, H3‧‧‧ height
H1‧‧‧ first height
H2‧‧‧second height
P‧‧‧ Hole
T‧‧‧ openings
W1, W2‧‧‧ length

1A-1F are perspective views of a method of fabricating a semiconductor device in accordance with an embodiment of the invention. 2A to 2F are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line A-A' of Figs. 1A to 1F. 3A to 3F are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line B-B' of Figs. 1A to 1F. 4A to 4F are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line C-C' of Figs. 1A to 1F.

10‧‧‧Base

12, 16b‧‧‧ dielectric layer

14‧‧‧Fin structure

16‧‧‧Stacking

16a‧‧‧Conductor layer

18‧‧‧Charge storage layer

20‧‧‧First hard mask layer

28‧‧‧ dielectric column

28b‧‧‧Top cover

30‧‧‧Comb structure

30a‧‧‧Comb

30b‧‧‧Connecting Department

A1‧‧‧ first angle

D1‧‧‧ first direction

D2‧‧‧ second direction

H3‧‧‧ Height

H1‧‧‧ first height

H2‧‧‧second height

W1, W2‧‧‧ length

Claims (10)

A method of fabricating a semiconductor device, comprising: forming a plurality of fin structures on a substrate, an adjacent opening between the fin structures; forming a layer of conductive material to cover the fin structures and filling The opening; and patterning the layer of conductor material and the fin structures to form a mesh structure having a plurality of first strips extending in a first direction and extending in a second direction a plurality of second strips, the first strips intersecting the second strips, and the mesh structure has a plurality of holes, wherein the first strips are located on the substrate and are located Positioning corresponding to the fin structures, the second strips are located on the substrate and the layer of the conductor material in the second strips spans the fin structures, the holes being located in the openings And the first strip and the second strip are surrounded by the holes, and the holes extend to a position closer to the base than the bottoms of the fin structures. The method of fabricating a semiconductor device according to claim 1, wherein the step of patterning the conductor material layer and the fin structures comprises performing a non-selective etching process. The method of manufacturing a semiconductor device according to claim 2, wherein an etching selectivity ratio between the conductor material layer and the fin structures is controlled to be 0.7 to 1.3 to perform the non-selective etching process. The method of fabricating a semiconductor device according to claim 1, wherein the forming the fin structures comprises: forming a stacked layer on the substrate, the stacked layer comprising at least one conductor layer and at least one stacked alternately a dielectric layer; and a charge storage layer is formed to cover the substrate at the bottom of the opening and the surface of the stacked layer. The method of fabricating a semiconductor device according to claim 1, further comprising: forming a plurality of dielectric pillars to fill at least the holes; and patterning the conductor material layer in the first strips and The dielectric pillars are configured such that the patterned layer of the conductor material forms a plurality of comb structures, each comb structure comprising: a plurality of comb portions inserted in the openings between the adjacent fin structures And contacting adjacent sidewalls of the fin structures; and a connecting portion extending in the second direction on the fin structures and connecting the comb portions. The method of manufacturing a semiconductor device according to claim 5, wherein the forming the dielectric pillars and patterning the conductive material layer and the dielectric pillars in the first strips comprises: forming a dielectric layer a layer of electrical material to cover the mesh structure and fill the holes; and patterning the layer of dielectric material and the layer of conductive material in the first strips to form the comb structures, a cap layer and the dielectric posts, each of the comb structures including the comb portions and the connecting portion, each cap layer being located on the connecting portion and extending along the second direction. A semiconductor device comprising: a substrate; a plurality of fin structures on the substrate and extending in a first direction, an adjacent opening between the fin structures; a plurality of comb structures, The comb structure includes a conductor material, each comb structure comprising: a plurality of comb portions inserted in the openings between adjacent fin structures and in contact with sidewalls of adjacent fin structures; a connecting portion extending in a second direction on the fin structures and connecting the comb portions; and a plurality of dielectric posts inserted in the opening between the adjacent fin structures and The sidewalls of the adjacent fin structures and the comb portions are in contact and extend to a position closer to the substrate than the bottom of the fin structures. The semiconductor device of claim 7, wherein the fin structures comprise a stacked layer and a charge storage layer, the stacked layer comprising at least one conductor layer and at least one dielectric layer alternately stacked, the charge storage A layer covers the substrate at the bottom of the opening and the surface of the stacked layer. The semiconductor device of claim 7, wherein each of the dielectric posts has a different height. The semiconductor component of claim 7, wherein the height of each dielectric post is greater than the height of each fin structure.