TWI545709B - 半導體封裝之製造方法 - Google Patents
半導體封裝之製造方法 Download PDFInfo
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- TWI545709B TWI545709B TW102113240A TW102113240A TWI545709B TW I545709 B TWI545709 B TW I545709B TW 102113240 A TW102113240 A TW 102113240A TW 102113240 A TW102113240 A TW 102113240A TW I545709 B TWI545709 B TW I545709B
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- Prior art keywords
- layer
- conductive
- ubm
- top surface
- pattern
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- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000010410 layer Substances 0.000 claims description 125
- 238000000034 method Methods 0.000 claims description 69
- 229910000679 solder Inorganic materials 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 10
- 238000007639 printing Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000004070 electrodeposition Methods 0.000 description 4
- 239000013067 intermediate product Substances 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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Description
本發明係關於一種半導體封裝,且更特定言之,係關於一種在不進行電沈積程序之情況下製造出具有焊料覆蓋之半導體晶粒之方法
隨著電子裝置之近來快速小型化,存在對覆晶技術之擴大需求以滿足電子裝置中的高密度互連。覆晶互連程序中的廣泛使用的一個步驟涉及焊料合金至晶粒之導電襯墊上之沈積。在常用的凸塊技術中,電鍍為如今工業中較為常用之技術之一。然而,在當前技術中電鍍程序面臨若干問題。一般電鍍程序成本超過網版印刷或落球(ball dropping)程序。另外,因為焊料中禁止使用鉛的原因,改變了焊料之組成。當焊料之各種成分之電化學還原電位之間存在巨大差異時,錫及其他金屬諸如銅之電鍍係困難的。
此外,電解質穩定性之控制亦為錫及其合金在水溶液中之電沈積的普遍問題。前述因素意味電鍍需要更成熟的操作技巧改進及更高的成本。
本發明提供不使用電沈積程序而形成焊料覆蓋之方法。隨
著在印刷或落球程序期間引入光阻層,上述方法以平均相較於電沈積程序低的支出提供對焊膏體積之較好控制。
本發明之一個實施例描述一種提供一半導體結構之方法,其中該方法包括以下步驟:提供一基板,該基板上有至少一導電襯墊;在該基板上形成一圖案層,其中該圖案層包括暴露該導電襯墊之至少一部分之一開口;在該開口中沈積一導電層,其中一高度差存在於該導電層之頂面與該鄰近圖案層之頂面之間,且該導電層之頂面低於該鄰近圖案層之頂面;在該導電層上形成一頂蓋層;及移除該圖案層;其中該頂蓋層形成步驟允許該頂蓋層與該導電層之間的接觸面積實質上等於該導電層之頂面面積。
在一個實施例中,前述方法中的形成該頂蓋層之該步驟包括可為落球、隨機噴塗、印刷、焊膏塗佈或其組合之一安置程序。
在另一實施例中,前述方法中的形成該頂蓋層之該步驟包括一焊料回焊程序。
在另一實施例中,移除該圖案層之該步驟可在一高溫處理下伴隨著該回焊步驟達成。
前文已頗為廣泛地概述本發明之特徵及技術優勢以便可更好地理解隨後的本發明之詳細描述。本發明之額外特徵及優勢將在下文中加以描述,且形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解,所揭示之概念及特定實施例可易於用作修改或設計其他結構或程序以用於進行本發明之同樣目的之基礎。熟習此項技術者亦應認識到,此等等效構造並不脫離如隨附申請專利範圍中所闡明之本發明之精神及範疇。
11‧‧‧介電層
12‧‧‧基板
13‧‧‧導電襯墊
21‧‧‧圖案層
23‧‧‧開口
31‧‧‧導電層
31A‧‧‧導電層之頂面
31B‧‧‧導電層之側壁
32‧‧‧導電層之頂面
33‧‧‧圖案層之頂面
41‧‧‧凸塊下金屬層
51‧‧‧焊膏層
61‧‧‧焊球
71‧‧‧焊球
82‧‧‧刮刀
83‧‧‧焊膏
111‧‧‧頂蓋層
121‧‧‧頂蓋層
d‧‧‧導電層之頂面與鄰近圖案層之頂面之間的高度差
D‧‧‧圖案層之高度
t‧‧‧焊膏之厚度
圖1至圖4說明用於製造半導體晶粒之程序的示意性剖視圖;圖5描繪焊膏印刷程序後之中間產物的示意性剖視圖;圖6描繪落球程序後之中間產物的示意性剖視圖;圖7描繪隨機噴塗程序後之中間產物的示意性剖視圖;圖8描繪焊膏塗佈程序期間之中間產物的示意性剖視圖;且圖9及圖10描繪焊料回焊程序及圖案層移除後之產物的示意性剖視圖。
以下描述請參考附圖,以便於說明本發明之目的及優點。
根據一個實施例,本發明揭示一種提供一半導體結構(例如,一封裝結構)之方法。如圖1中所示,複數個導電襯墊13以微光顯影方式沈積於基板12之頂面上。在本實施例中,沈積程序可為(但不限制於)化學氣相沈積程序、電漿增強化學氣相沈積程序、諸如濺鍍或物理氣相沈積程序,或類似程序。基板12可為半導體基板或印刷電路板。作為鈍化層之介電層11實質上形成於導電襯墊13之上。介電層11可為(但不限制於)氧化物層、氮化物層或聚合層。複數個開口形成於介電層11上。該等開口經配置以與導電襯墊13耦接且暴露導電襯墊13之一部分。
在圖2中,圖案層21形成於介電層11之無開口之部分上。圖案層21可為(但不限制於)光阻層或介電層。複數個開口23在預定位置中形成於圖案層21上,使得導電襯墊13之頂面暴露於外部環境中。
如圖2及圖3中所示,導電層31允許導電層31之頂面32低於鄰近圖案層21之頂面33之方式沈積於開口23中。高度差「d」存在於導電層31之頂面32與鄰近圖案層21之頂面33之間。在一個實施例中,高度差「d」為在圖案層21之高度「D」之一半至四分之一之範圍內。導
電層31可以若干方式(諸如,經由化學氣相沈積程序、電漿增強化學氣相沈積程序,及諸如濺鍍或物理氣相沈積程序)中之任一方式沈積。用於導電層32之材料包括任何導電金屬,通常為銅、金、鎳或其合金。
請參考圖4所示,根據另一實施例,一凸塊下金屬41(UBM)層形成於介電層11及導電襯墊13之暴露部分之上。該UBM層包括至少兩層下金屬層,即黏接層及晶種層。該黏接層與導電襯墊13直接接觸且通常由鈦或鎢化鈦(TiW)製成,以便提供導電襯墊13與導電層31之間的機械上較佳之連接及較好的黏著性。該晶種層定位於該黏接層上且由金、銅、鎳或合金組成。圖4中所示之UBM 41層由金屬濺鍍程序、氣相沈積程序或金屬膏印刷程序形成。然而,由熟習此項技術者構想之其他方式亦可用於本發明之UBM形成步驟中。
如圖5中所示,焊膏層51藉由印刷程序形成於導電層31之上。在該印刷程序後,可繼續實行一回焊程序,以完成頂蓋層之形成。在本實施例中,焊膏可利用網版印刷(screen printing)或鋼板印刷(stencil printing)程序,從而在導電層31上形成圖案化焊膏。圖案化焊膏之尺寸不必與導電層之尺寸相同。換言之,該焊膏之寬度可由網版上的圖案或刻板上的開口控制,而該焊膏之厚度「t」可由相對於安置有網版或鋼板之位置決定。
如圖6中所示,焊球61藉由落球程序安置於導電層31之上。該落球程序可伴隨落球之後的回焊程序形成頂蓋層(solder cap)。於實施時,複數個焊球安置於具有眾多開口之模板上,其中該等開口之分佈對應於導電層之圖案。鋼板上開口之尺寸可經調整以允許一個或多個焊球通過。另外,焊球尺寸大小可依製造程序自由選擇。在本實施例中,至少一焊球可安置於結構之表面上。因為表面形態現包括複數個凹谷及凸起,所以各種大小之焊球可在鋼板之協助下於凹谷中自行定
位(self-assembled)。如圖6所示,進行落球程序以在每一凹谷中形成一個焊球,而在圖7中,隨機噴塗程序允許複數個焊球71陷於凹谷中。焊料覆蓋層之最終厚度由本步驟中安置之焊接材料的量來決定。可進行合理計算以選擇焊球之大小及上文所述之置放方法。
如圖8所示,形成覆蓋層之替代方法涉及焊膏塗佈。塗佈程序可伴隨之後的回焊程序形成頂蓋層。在一個實施例中,焊膏83由基質中摻混複數個焊珠之黏合基質組成。刮刀82用以在導電層及圖案層之表面上塗佈焊膏。由於該表面上存在凹谷結構,預定量之焊膏殘留於該凹谷結構中,而多餘的焊膏由刮刀82刮除。殘留於該凹谷結構中之焊膏的量由該凹谷結構之尺寸決定;因此,導電層與圖案層之間的高度差d(如圖3中所展示)與最終產物(即,回焊之焊料)的大小直接相關。在本實施例中,高度差「d」可處在(但不限制於)圖案層之高度「D」之三分之一至四分之一之範圍內。
在於導電層上塗覆焊接材料之後,進行回焊程序。接下來,取決於圖案層之材料,藉由光阻剝離程序或蝕刻程序移除該圖案層。在一個實施例中,焊料回焊程序及圖案層移除程序係在一個高溫處理下相伴完成。如圖9所示,半球狀的頂蓋層111形成於導電層31之上。然而,頂蓋層111並不限制於半球形狀。基於焊接材料之實際量及焊料相對於導電層之可濕性(wettability),該頂蓋層之最終形態為大體上之凸起結構。根據以上陳述之程序,在移除圖案層後,焊接材料僅與導電層31之表面31A接觸,且導電層31之側壁31B上實質上不含任何焊接材料。
如圖10中所示,在一個實施例中,UBM 41定位於導電層31下。在移除圖案層後UBM層41才會暴露出來。因此,需要一額外程序移除UBM層不與導電層31接觸之部分。
雖然已詳細地描述了本發明及其優勢,但應理解,在不脫離如
由隨附申請專利範圍界定的本發明之精神及範疇之情況下,本文中可進行各種改變、替代及更改。舉例而言,上文所論述之程序中之多者可以不同方法來實施且可由其他程序或其組合替代。
此外,本申請案之範疇不欲限於說明書中所描述之程序、機器、製造、物質組成、手段、方法及步驟之特定實施例。如一般熟習此項技術者將易於自本發明之揭示內容瞭解,根據本發明,可利用當前存在或日後將開發出的執行與本文中所描述之相應實施例大體上相同的功能或達成與本文中所描述之相應實施例大體上相同的結果之程序、機器、製造、物質組成、手段、方法或步驟。因此,隨附申請專利範圍意欲在其範疇中包括此等程序、機器、製造、物質組成、手段、方法或步驟。
11‧‧‧介電層
12‧‧‧基板
13‧‧‧導電襯墊
31‧‧‧導電層
31A‧‧‧導電層之頂面
31B‧‧‧導電層之側壁
111‧‧‧頂蓋層
Claims (10)
- 一種提供一半導體結構之方法,該方法包含以下步驟:提供一基板且該基板上具有至少一導電襯墊;在該基板上形成一凸塊下金屬(UBM)層;在該基板上形成一圖案層,其中該圖案層包括暴露該UBM層之至少一部分之一開口;在該開口中沈積一導電層,其中一高度差存在於該導電層之頂面與該鄰近圖案層之頂面之間,且該導電層之該頂面低於該鄰近圖案層之該頂面;在該導電層上形成一頂蓋層;以及移除該圖案層;其中該頂蓋層形成步驟允許該頂蓋層與該導電層之間的接觸面積實質上等於該導電層之頂面面積,進一步包含移除該UBM層之一步驟。
- 如請求項1之方法,其中該UBM層包括與該導電襯墊直接接觸之黏接層及位於該黏接層上之晶種層。
- 如請求項1之方法,其中該UBM層係藉由濺鍍、氣相沈積或印刷形成。
- 如請求項1之方法,其中該高度差在該圖案層高度之一半至四分之一的範圍內。
- 如請求項1之方法,其中該導電層係由選自鎳、銅、金及其組合 之材料形成。
- 如請求項1之方法,其中該頂蓋層為一焊料層。
- 如請求項6之方法,其中形成該頂蓋層包含一回焊步驟。
- 如請求項7之方法,其中形成該頂蓋層的步驟包含落球(ball dropping)、隨機噴塗(random spraying)、印刷(printing)、焊膏塗佈(solder paste spreading)或其組合之一安置步驟,且該回焊步驟在該安置步驟之後。
- 如請求項1之方法,其中移除該UBM層之該步驟係移除該UBM層不與該導電層接觸之部分。
- 如請求項7之方法,其中移除該圖案層之該步驟可在一高溫處理下伴隨著該回焊步驟達成。
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US13/534,289 US9023727B2 (en) | 2012-06-27 | 2012-06-27 | Method of manufacturing semiconductor packaging |
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TW201401467A TW201401467A (zh) | 2014-01-01 |
TWI545709B true TWI545709B (zh) | 2016-08-11 |
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TW102113240A TWI545709B (zh) | 2012-06-27 | 2013-04-15 | 半導體封裝之製造方法 |
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US9082754B2 (en) * | 2012-08-03 | 2015-07-14 | International Business Machines Corporation | Metal cored solder decal structure and process |
US9202793B1 (en) * | 2013-12-26 | 2015-12-01 | Stats Chippac Ltd. | Integrated circuit packaging system with under bump metallization and method of manufacture thereof |
US9524926B2 (en) * | 2014-09-26 | 2016-12-20 | Texas Instruments Incorporated | Packaged device with additive substrate surface modification |
CN108538735B (zh) * | 2017-03-02 | 2020-05-29 | 中芯国际集成电路制造(上海)有限公司 | 金属凸块装置及其制造方法 |
US11114406B2 (en) * | 2019-01-31 | 2021-09-07 | Sandisk Technologies Llc | Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip |
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TWI245402B (en) * | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
CN1166481C (zh) * | 2002-06-28 | 2004-09-15 | 威盛电子股份有限公司 | 高分辨率焊接凸块形成方法 |
US20090174069A1 (en) * | 2008-01-04 | 2009-07-09 | National Semiconductor Corporation | I/o pad structure for enhancing solder joint reliability in integrated circuit devices |
US8492891B2 (en) * | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
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2012
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US20140004697A1 (en) | 2014-01-02 |
CN103515259A (zh) | 2014-01-15 |
TW201401467A (zh) | 2014-01-01 |
CN103515259B (zh) | 2016-12-28 |
US9023727B2 (en) | 2015-05-05 |
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