TWI541917B - Method for manufacturing package substrate - Google Patents
Method for manufacturing package substrate Download PDFInfo
- Publication number
- TWI541917B TWI541917B TW100136852A TW100136852A TWI541917B TW I541917 B TWI541917 B TW I541917B TW 100136852 A TW100136852 A TW 100136852A TW 100136852 A TW100136852 A TW 100136852A TW I541917 B TWI541917 B TW I541917B
- Authority
- TW
- Taiwan
- Prior art keywords
- tin
- solder
- package substrate
- copper
- copper solder
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims description 29
- 238000000034 method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 55
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 20
- 239000002335 surface treatment layer Substances 0.000 claims description 16
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 11
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 238000007654 immersion Methods 0.000 claims description 5
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims 1
- 229910000765 intermetallic Inorganic materials 0.000 description 12
- 239000010410 layer Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
本發明係有關一種封裝基板之製法，尤指一種供焊球植接其上之封裝基板之製法。The invention relates to a method for manufacturing a package substrate, in particular to a method for manufacturing a package substrate on which a solder ball is implanted.
隨電子產品朝多功能、高性能的發展，半導體封裝結構對應開發出不同的封裝型態。其中一種該半導體封裝結構，主要係將晶片放置並電性連接至一封裝基板(package substrate)上，再將封裝基板連同晶片進行封裝，最後將其上封裝有晶片之封裝基板藉焊球結合於電路板上。因此，習知封裝基板上均具有電性接觸墊，以供該封裝基板藉之與晶片及電路板電性連接。With the development of multi-functional and high-performance electronic products, semiconductor package structures have developed different package types. One of the semiconductor package structures is mainly to place and electrically connect the wafer to a package substrate, package the package substrate together with the wafer, and finally bond the package substrate on which the wafer is packaged to the solder ball. On the board. Therefore, the conventional package substrate has an electrical contact pad for electrically connecting the package substrate to the chip and the circuit board.
請參閱第1A及1B圖，係為習知封裝基板之製法。如第1A圖所示，一基板10係具有複數銅材之電性接觸墊100，該基板10上形成有絕緣保護層11，且該絕緣保護層11形成有複數開孔110，以令該電性接觸墊100外露出該開孔110；接著，於該開孔110中之電性接觸墊100上形成表面處理層12，且該表面處理層12之材質係為化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG)；最後，如第1B圖所示，於該表面處理層12上形成錫銀銅（SAC）無鉛錫膏，再回焊該錫銀銅無鉛錫膏，以形成焊球15。Please refer to FIGS. 1A and 1B for the fabrication of a conventional package substrate. As shown in FIG. 1A, a substrate 10 is an electrical contact pad 100 having a plurality of copper materials. The substrate 10 is formed with an insulating protective layer 11 and the insulating protective layer 11 is formed with a plurality of openings 110 for making the electricity. The opening contact hole 100 is exposed to the opening 110; then, the surface treatment layer 12 is formed on the electrical contact pad 100 in the opening 110, and the surface treatment layer 12 is made of nickel-palladium immersion gold (Electroless Nickel) /Electroless Palladium/Immersion Gold, ENEPIG); Finally, as shown in FIG. 1B, a tin-silver-copper (SAC) lead-free solder paste is formed on the surface treatment layer 12, and the tin-silver-copper lead-free solder paste is reflowed to form Solder ball 15.
惟，習知之製法中，該SAC無鉛錫膏與電性接觸墊100之間的表面處理層12介面上易形成不良之介面合金共化物(Inter Metallic Compound, IMC)層，而該不良之IMC層因脆性較強，會損及焊球15之機械強度、壽命及抗疲勞度(Fatigue Strength)，而導致焊球15脫落，造成產品之可靠度不良。However, in the conventional method, the surface of the surface treatment layer 12 between the SAC lead-free solder paste and the electrical contact pad 100 is likely to form a poor interface of an Inter Metallic Compound (ICC) layer, and the defective IMC layer Due to the strong brittleness, the mechanical strength, the life and the fatigue resistance of the solder ball 15 are damaged, and the solder ball 15 falls off, resulting in poor reliability of the product.
再者，因該不良之IMC層會隨回焊時間的增加而增厚，致減少焊球15位於該開孔110中之部分，導致焊球15之固著力降低，而使該焊球15容易鬆落。Moreover, since the defective IMC layer is thickened with an increase in the reflow time, the portion of the solder ball 15 located in the opening 110 is reduced, resulting in a decrease in the fixing force of the solder ball 15 and making the solder ball 15 easy. Loose.
因此，如何克服上述習知技術中之種種問題，實已成目前亟欲解決的課題。Therefore, how to overcome the various problems in the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之缺失，本發明遂提供一種封裝基板之製法，係先提供一具有電性接觸墊與絕緣保護層之基板，且該絕緣保護層外露該電性接觸墊，再於該基板之電性接觸墊上形成材質為化鎳鈀浸金之表面處理層，接著於該表面處理層上形成錫銅焊料，最後於該錫銅焊料上形成錫銀銅焊料。In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for manufacturing a package substrate by first providing a substrate having an electrical contact pad and an insulating protective layer, and the insulating protective layer exposes the electrical contact pad, and then the substrate A surface treatment layer made of nickel-palladium immersion gold is formed on the electrical contact pad, and then a tin-copper solder is formed on the surface-treated layer, and finally a tin-silver-copper solder is formed on the tin-copper solder.
由上可知，本發明之製法中，主要藉由形成二次焊料，且先形成錫銅焊料，以使該錫銅焊料與電性接觸墊之間的表面處理層介面上形成良好之介面合金共化物(IMC)層，而該良好之IMC層因穩定性較佳，故不會影響後續回焊製程中所形成之焊球之機械強度、壽命及抗疲勞度，可避免焊球脫落，以提升產品之可靠度。It can be seen from the above that in the method of the present invention, a secondary solder is formed mainly, and a tin-copper solder is first formed to form a good interface alloy on the surface treatment layer interface between the tin-copper solder and the electrical contact pad. The (IMC) layer, and the good IMC layer has good stability, so it does not affect the mechanical strength, life and fatigue resistance of the solder balls formed in the subsequent reflow process, and can prevent the solder balls from falling off to improve Product reliability.
再者，因該良好之IMC層不會隨時間增加而增厚，故可維持後續回焊製程中所形成之焊球位於該開孔中之比例，以避免焊球之固著力降低之習知問題，故該焊球不易從該基板上鬆落。 Moreover, since the good IMC layer does not increase in thickness with time, the ratio of the solder balls formed in the subsequent reflow process to the opening can be maintained to avoid the reduction of the fixing force of the solder balls. The problem is that the solder ball is not easily loosened from the substrate.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.
請參閱第2A至2F圖，係為本發明封裝基板之製法之剖視示意圖。 Please refer to FIGS. 2A to 2F, which are cross-sectional views showing the manufacturing method of the package substrate of the present invention.
如第2A圖所示，首先，提供一具有電性接觸墊200之基板20，且該基板20上具有絕緣保護層21，該絕緣保護層21具有開孔210，以令該電性接觸墊200外露出該開孔210。 As shown in FIG. 2A, first, a substrate 20 having an electrical contact pad 200 is provided, and the substrate 20 has an insulating protective layer 21 having an opening 210 for the electrical contact pad 200. The opening 210 is exposed.
如第2B圖所示，於該開孔210中之電性接觸墊200上形成表面處理層22，且形成該表面處理層22之材質係為 化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)。 As shown in FIG. 2B, a surface treatment layer 22 is formed on the electrical contact pad 200 in the opening 210, and the material forming the surface treatment layer 22 is Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG).
如第2C圖所示，藉由印刷方式(如圖所示之網板3)，於該表面處理層22上形成錫銅焊料23。於本實施例中，該錫銅焊料23係為錫銅無鉛錫膏。 As shown in Fig. 2C, a tin-copper solder 23 is formed on the surface treatment layer 22 by a printing method (such as the screen 3 as shown). In the present embodiment, the tin-copper solder 23 is a tin-copper lead-free solder paste.
如第2D圖所示，移除該網板3，且將該錫銅焊料23’進行回焊製程，以於該錫銅焊料23’與電性接觸墊200之間的表面處理層22介面上形成良好之介面合金共化物(Inter Metallic Compound,IMC)層。 As shown in FIG. 2D, the stencil 3 is removed, and the tin-copper solder 23' is subjected to a reflow process to interface the surface treatment layer 22 between the tin-copper solder 23' and the electrical contact pad 200. A good interface of Inter Metallic Compound (IMC) is formed.
如第2E圖所示，藉由印刷方式(如圖所示之網板3)，於該錫銅焊料23’上形成錫銀銅焊料24。於本實施例中，該錫銀銅焊料24係為錫銀銅無鉛錫膏。 As shown in Fig. 2E, a tin-silver-copper solder 24 is formed on the tin-copper solder 23' by a printing method (such as the screen 3 as shown). In this embodiment, the tin-silver-copper solder 24 is a tin-silver-copper lead-free solder paste.
如第2F圖所示，移除該網板3，且將該錫銀銅焊料24與該錫銅焊料23’進行回焊製程，以形成焊球25。 As shown in Fig. 2F, the screen 3 is removed, and the tin-silver-copper solder 24 and the tin-copper solder 23' are subjected to a reflow process to form the solder balls 25.
本發明之封裝基板之製法，係藉由先形成錫銅焊料23，以經回焊製程後形成良好之IMC層，而該良好之IMC層因具有較穩定之特性，故不會影響焊球25之機械強度、壽命及抗疲勞度，有效避免焊球25脫落，以提升產品之可靠度。 The package substrate of the present invention is formed by first forming a tin-copper solder 23 to form a good IMC layer after the reflow process, and the good IMC layer has a relatively stable property and thus does not affect the solder ball 25 The mechanical strength, life and fatigue resistance effectively prevent the solder ball 25 from falling off to improve the reliability of the product.
再者，藉由該錫銅焊料23’所形成的良好之IMC層，其厚度不會隨時間增加，故當經回焊製程形成焊球25後，可維持焊球25位於該開孔210中之比例，有效避免該焊球25之固著力降低之習知問題，以使該焊球25不易從該基板20上鬆落。 Moreover, the thickness of the good IMC layer formed by the tin-copper solder 23' does not increase with time, so that after the solder ball 25 is formed by the reflow process, the solder ball 25 can be maintained in the opening 210. The ratio is effective to avoid the conventional problem of the reduction of the fixing force of the solder ball 25, so that the solder ball 25 is not easily loosened from the substrate 20.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10,20‧‧‧基板 10,20‧‧‧substrate
100,200‧‧‧電性接觸墊 100,200‧‧‧Electrical contact pads
11,21‧‧‧絕緣保護層 11,21‧‧‧Insulating protective layer
110,210‧‧‧開孔 110,210‧‧‧ openings
12,22‧‧‧表面處理層 12,22‧‧‧Surface treatment layer
15,25‧‧‧焊球 15,25‧‧‧ solder balls
23,23’‧‧‧錫銅焊料 23,23'‧‧‧ tin-copper solder
24‧‧‧錫銀銅焊料 24‧‧‧ tin silver solder
3‧‧‧網板 3‧‧‧ stencil
第1A至1B圖係為習知封裝基板之製法的剖視示意圖；以及第2A至2F圖係為本發明封裝基板之製法的剖視示意圖。 1A to 1B are schematic cross-sectional views showing a method of manufacturing a conventional package substrate; and Figs. 2A to 2F are schematic cross-sectional views showing a method of manufacturing the package substrate of the present invention.
20．．．基板20. . . Substrate
200．．．電性接觸墊200. . . Electrical contact pad
21．．．絕緣保護層twenty one. . . Insulating protective layer
22．．．表面處理層twenty two. . . Surface treatment layer
23’．．．錫銅焊料twenty three'. . . Tin-copper solder
24．．．錫銀銅焊料twenty four. . . Tin-silver copper solder
3．．．網板3. . . Stencil
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100136852A TWI541917B (en) | 2011-10-12 | 2011-10-12 | Method for manufacturing package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100136852A TWI541917B (en) | 2011-10-12 | 2011-10-12 | Method for manufacturing package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201316424A TW201316424A (en) | 2013-04-16 |
| TWI541917B true TWI541917B (en) | 2016-07-11 |
Family
ID=48803118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100136852A TWI541917B (en) | 2011-10-12 | 2011-10-12 | Method for manufacturing package substrate |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI541917B (en) |
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2011
- 2011-10-12 TW TW100136852A patent/TWI541917B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW201316424A (en) | 2013-04-16 |
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