TWI541627B - Reference voltage circuit - Google Patents

Description

Reference voltage circuit

The present invention relates to a reference voltage circuit.

Figure 6 is a circuit diagram showing a conventional reference voltage circuit.

The conventional reference voltage circuit includes PMOS transistors 101 to 103, NMOS transistors 201 to 204 and 301, an output terminal 401, a power supply terminal 501, a ground terminal 502, and a resistor 601. The threshold voltage of the NMOS transistor 301 (hereinafter _referred to as V _tnl ) is lower than the threshold voltage of the NMOS transistors 201 to 204 (hereinafter _referred to as V _tnh ). The PMOS transistors 102 and 103 constitute a PMOS transistor 101 and a current mirror circuit, and a 汲 terminal current of a desired ratio of the 汲 terminal current of the PMOS transistor 101 flows. The NMOS transistor 204 constitutes an NMOS transistor 203 and a current mirror circuit, and flows through the 汲 terminal current of a desired ratio of the 汲 terminal current of the NMOS transistor 203.

The source terminals of the PMOS transistors 101 to 103 are connected to the power supply terminals. The gate terminals of the PMOS transistors 102 and 103 are connected to the gate terminal and the gate terminal of the PMOS transistor 101, and the gate terminal of the NMOS transistor 201. The gate terminals of the NMOS transistors 201 and 202 are connected to the NMOS terminal of the NMOS transistor 201 and the NMOS terminal of the PMOS transistor 102. The source terminal of the NMOS transistor 202 is connected to a ground terminal. One end of the resistor 601 is connected to the source terminal of the NMOS transistor 201, and the other end is connected to the ground terminal. NMOS The gate terminals of the crystals 203, 204, and 301 are connected to the NMOS terminals of the NMOS transistor 203 and the PMOS transistor 103. The source terminals of the NMOS transistors 203 and 204 are connected to a ground terminal. The 汲 terminal of the NMOS transistor 301 is connected to a power supply terminal. The output terminal 401 is connected to the NMOS terminal of the NMOS transistor 204 and the source terminal of the NMOS transistor 301.

The K values of the NMOS transistors 201 to ₂₀₄ and ₃₀₁ are K ₂₀₁ , K ₂₀₂ , K ₂₀₃ , K ₂₀₄ and K ₃₀₁ , respectively, and the resistance value of the resistor 601 is R ₆₀₁ .

The PMOS transistors 101 and 102, the NMOS transistors 201 and 202, and the resistor 601 constitute a constant current circuit. For example, when each transistor operates in the saturation region, if the K values of the PMOS transistors 101 and 102 are equal, the currents flowing to the PMOS transistors 101 and 102 are equal, and the current value is 0 A or a certain current value (hereinafter). Set to I _K ). The starter circuit is provided so that the current does not become 0A, whereby the PMOS transistors 101 and 102, the NMOS transistors 201 and 202, and the resistor 601 operate as a constant current circuit. The constant current I _K is expressed by the following equation.

Where K ₂₀₁ >K ₂₀₂ .

In the PMOS transistor 103, the constant current I _K is mirrored, and the NMOS transistor 204 mirrors the 汲 terminal current of the PMOS transistor 103. For example, when all of the transistors of FIG. 6 operate in the saturation region, if the K values of the PMOS transistors 101 and 103 are equal, the K values of the NMOS transistors 203 and 204 are equal, and the constant current flows through the NMOS transistors 204 and 301. I _K. When the voltage between the gate and the source required to supply the constant current I _K to the NMOS transistors 204 and 301 is V _GS204K and V _GS301K , respectively, the voltage of the output terminal 401 (hereinafter _referred to as V _refK ), if (1) is used When it is expressed by the following formula.

Where K ₂₀₁ >K ₂₀₂ .

As described above, the reference voltage circuit of FIG. 6 to the output line _{V tnl, V tnh, K 201} , K 202, K 204, K 301, R 601 determined by the reference voltage _V refK circuit.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-148530

However, in the conventional reference voltage circuit shown in FIG. 6, the equation (2), in addition to the K value and the threshold value of the transistor, the resistance value determines the reference voltage value, so there is an influence on the process variation or temperature. The problem of the influence of characteristics becomes large. In addition, if the correction is performed in such a manner as to reduce the temperature characteristic of the reference voltage value, there is also an increase in the variation due to process variation. Question. In addition, in order to perform correction, since it is necessary to incorporate a temperature sensor or a logic circuit for correction, there is a problem that the circuit scale is increased.

The present invention has been made in view of the above problems, and provides a method for reducing the variation of the reference voltage value and the reference voltage value to a desired range without increasing the circuit scale. The reference voltage circuit inside.

In order to solve the above problems, the reference voltage circuit of the present invention has a configuration in which a first MOS transistor is provided, and a second MOS transistor is connected to a gate terminal of the first MOS transistor and has a high voltage. The absolute value and the K value of the absolute value of the threshold value of the first MOS transistor and the K value; and the current mirror circuit that distributes the absolute value of the threshold value according to the first MOS transistor and the second MOS transistor a differential current; a third MOS transistor, which is a current flowing through the current mirror circuit; and a fourth MOS transistor having an absolute value that is higher than a threshold value of the third MOS transistor and a threshold value of the K value. The value and the K value, and the current flowing through the current mirror circuit, is based on the constant voltage output of the difference between the absolute value of the third MOS transistor and the fourth MOS transistor and the K value as the reference voltage.

When the reference voltage circuit of the present invention is used, the variation in the reference voltage value due to the variation of the resistance process or the variation in the correction value of the reference voltage value or the temperature characteristic can be reduced without increasing the circuit scale.

The present embodiment will be described below with reference to the drawings.

[Example 1]

Fig. 1 is a circuit diagram showing a reference voltage circuit of the first embodiment.

The reference voltage circuit of the first embodiment includes PMOS transistors 101 and 102, NMOS transistors 201, 301 and 302, an output terminal 401, a power supply terminal 501, and a ground terminal 502. The threshold voltage of the NMOS transistors 301 and 302 (hereinafter _referred to as V _tnl ) is lower than the threshold voltage of the NMOS transistor 201 (hereinafter _referred to as V _tnh ). The K values of the NMOS transistors ₂₀₁ , ₃₀₁ , and ₃₀₂ are K ₂₀₁ , K ₃₀₁ , and K _{302 , respectively} . The PMOS transistor 101 and the PMOS transistor 102 constitute a current mirror circuit.

Next, the connection of the reference voltage circuit of the first embodiment will be described.

The source terminals of the PMOS transistors 101, 102 are connected to the power supply terminal 501. The gate terminal of the PMOS transistor 102 is connected to the gate terminal and the gate terminal of the PMOS transistor 101 and the gate terminal of the NMOS transistor 301. The gate terminals of the NMOS transistors 201 and 301 are connected to the NMOS terminal and the gate terminal of the NMOS transistor 302 and the NMOS terminal 102, and the source terminal is connected to the ground terminal 502. The output terminal 401 is connected to the drain terminal of the NMOS transistor 201 and the source terminal of the NMOS transistor 302.

Next, the operation of the reference voltage circuit of the first embodiment will be described.

The 汲 terminal currents of the PMOS transistors 101 and 102 are set to I ₁₀₁ and I ₁₀₂ , respectively. The voltage of the output terminal 401 is set to V _ref . Since the PMOS transistors 101 and 102 constitute a current mirror circuit, if the respective K values are equal, the current I ₁₀₁ and the current I ₁₀₂ are equal in current. FIG. 2 shows the characteristics of the gate-to-source voltage (hereinafter referred to as V _GS ) versus the terminal current (hereinafter referred to as I _D ) when the NMOS transistor 201 and the NMOS transistor 301 operate in the saturation region. The rising position and the slope of each curve are determined by the threshold voltage and the K value, respectively. Since the current I _{101 is} equal to the current I ₁₀₂ , the NMOS transistor 201 is connected to the gate terminal of the NMOS transistor 301. Therefore, if the two transistors operate in the saturation region, the voltage V _GS becomes the point A. When the start-up circuit is provided, the current I ₁₀₁ (=I ₁₀₂ ) is the current value at point A (hereinafter _referred to as I _A ), and the value is _expressed by V _tnl , V _tnh , K ₂₀₁ , and K ₃₀₁ as follows.

Among them, K ₂₀₁ >K ₃₀₁ .

When the voltages V _GS required to pass the current I _{A of the} NMOS transistors 201 and 302 are V _GS201A and V _GS302A , respectively, and the ground terminal voltage is VSS, the reference voltage V _ref of the output terminal 401 is V _ref = VSS. +V _GS201A -V _GS302A . The values of voltage V _GS201A and voltage V _GS302A are determined by the values of I _A , V _tnl , V _tnh , K ₂₀₁ , and K ₃₀₂ . Since the current I _A is determined by the values of V _tnl , V _tnh , K ₂₀₁ , and K ₃₀₁ , the value of the reference voltage V _ref of the output terminal 401 is only V _tnh , V _tnl , K ₂₀₁ , K . The values of ₃₀₁ and K ₃₀₂ are determined.

When the NMOS transistor 201 and the NMOS transistor 302 operate in the saturation region, the reference voltage V _ref is expressed by the following equation.

Here, if all of the transistors operate in the saturation region, the current I _A of the equation (4) is substituted into the equation (3), and the reference voltage V _ref is expressed by the following equation.

Among them, K ₂₀₁ >K ₃₀₁ .

As can be seen from equation (5), the value of the reference voltage V _{ref is} a voltage determined by V _tnh , V _tnl , K ₂₀₁ , K ₃₀₁ , and K ₃₀₂ . In this way, a reference voltage that does not cause a variation due to a process variation of the resistor can be obtained. In addition, when the temperature characteristics are corrected, only the values of K ₂₀₁ , K ₃₀₁ , and K ₃₀₂ can be adjusted to easily correct them.

Here, the case where the NMOS transistors 201, 301, and 302 operate in the saturation region is taken as an example, but even if either or all of them operate in the weak inversion domain, the V _GS pair I _{D of the} two transistors is used. By setting K ₂₀₁ and K _{301 in} a manner in which the curves intersect, the current I _A determined by the values of V _tnl , V _tnh , K ₂₀₁ , and K ₃₀₁ can be formed. Further, the reference voltage V _ref may be determined by the values of V _tnl , V _tnh , K ₂₀₁ , K ₃₀₁ , and K ₃₀₂ . Therefore, the temperature characteristic can be corrected only by adjusting the K value of each transistor.

The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. Transistor 汲 The extreme pole current ratio is used to correct the reference voltage value.

According to the above, it is possible to prevent variations due to variations in the process of the resistor, and when the temperature characteristics are corrected, the reference voltage can be easily corrected by adjusting only the values of K ₂₀₁ , K ₃₀₁ , and K ₃₀₂ .

[Embodiment 2]

Fig. 3 is a circuit diagram showing a reference voltage circuit of the second embodiment.

The reference voltage circuit of the second embodiment includes PMOS transistors 101 to 106, NMOS transistors 201 to 204, 301 to 303, an output terminal 401, a power supply terminal 501, a ground terminal 502, and resistors 601 to 602. The threshold voltages of the NMOS transistors 301 to 302 (hereinafter _referred to as V _tnl ) are lower than the threshold voltages of the NMOS transistors 201 to 202 (hereinafter _referred to as V _tnh ). The K values of the NMOS transistors ₂₀₁ , ₂₀₂ , ₃₀₁ , and ₃₀₂ are set to K ₂₀₁ , K ₂₀₂ , K ₃₀₁ , and K _{302 , respectively} . The resistance values of the resistors ₆₀₁ and ₆₀₂ are set to R ₆₀₁ and R ₆₀₂ , respectively. The NMOS transistors 203 and 204 constitute a current mirror circuit. The PMOS transistor 101 and the PMOS transistors 102, 103, and 104 constitute a current mirror circuit.

Next, the connection of the reference voltage circuit of the second embodiment will be described.

The source terminals of the PMOS transistors 101 to 106 are connected to the power supply terminal 501. The gate terminals of the PMOS transistors 102-104 are connected to the gate terminal and the NMOS terminal of the PMOS transistor 101 and the NMOS terminal of the NMOS transistor 301. The gate terminals of the NMOS transistors 201, 301 are connected to the ? terminal of the NMOS transistor 201 and the ? terminal of the PMOS transistor 102, and the source terminal is connected to the ground terminal 502. resistance One end of the 601 is connected to the gate terminal of the NMOS transistor 202 and the source terminal of the NMOS transistor 303, and the other end is connected to the gate terminal of the NMOS transistor 204 and the gate terminal of the NMOS transistor 302. The NMOS terminal of the NMOS transistor 202 is connected to the gate terminals of the PMOS transistor 103 and the NMOS transistor 303, and the source terminal is connected to the ground terminal. The 汲 terminal of the NMOS transistor 303 is connected to the power supply terminal 501. The NMOS terminal of NMOS transistor 302 is connected to the NMOS terminal 104 and the PMOS transistor 105, 106, and the source terminal is connected to ground terminal 502. The gate terminals of the NMOS transistors 203, 204 are connected to the ? terminal of the NMOS transistor 203 and the ? terminal of the PMOS transistor 105, and the source terminal is connected to the ground terminal 502. One end of the resistor 602 is connected to the 汲 terminal of the PMOS transistor 106 and the output terminal 401, and the other end is connected to the ground terminal 502.

Next, the operation of the reference voltage circuit of the second embodiment will be described. The voltage of the output terminal 401 is set to the reference voltage V _ref . The current flowing to the PMOS transistors 101 and 102 is the current I _A determined by the values of V _tnl , V _tnh , K ₂₀₁ , and K ₃₀₁ described in the equation (3) of the first embodiment, if the K values are equal. .

The current-based PMOS transistors 103 and 104 flowing to the PMOS transistors 103 and 104 constitute the PMOS transistor 101 and the current mirror circuit. Therefore, if the respective K values are the same, the current I _A flows.

The NMOS transistor 303 controls the gate terminal voltage of the NMOS transistor 202 such that the voltage between the gate and the source of the NMOS transistor 202 becomes the voltage required to pass the current I _A . The PMOS transistor 104, the NMOS transistor 203, and the NMOS transistor 204 control the gate terminal voltage of the NMOS transistor 302 such that the voltage between the gate and the source of the NMOS transistor 302 becomes the voltage required to pass the current I _A .

When the voltage between the gate and the source required for the NMOS transistors 202 and 302 to _{pass the} current I _{A is} set to the voltage V _GS202A and the voltage V _GS302A respectively, the voltage V _{ref2 of the} V _GS202A -V _GS302A appears at both ends of the resistor 601. . The voltage V _ref2 is determined by the values of I _A , V _tnl , V _tnh , K ₂₀₂ , and K ₃₀₂ . Since the current I _A is determined by the values of V _tnl , V _tnh , K ₂₀₁ , and K ₃₀₁ , the voltage V _ref2 is determined by the values of V _tnl , V _tnh , K ₂₀₁ , K ₂₀₂ , K ₃₀₁ , and K ₃₀₂ . In this way, a reference voltage that does not cause a variation due to a process variation of the resistor can be obtained. Further, the temperature characteristics of the voltage V _ref2 can be corrected to be gentle with _{respect to} the temperature characteristics of I _A , V _{GS 202A} , and V _{GS 302} A by adjusting the values of K ₂₀₂ and K ₃₀₂ .

When each transistor operates in the saturation _region , the value of the voltage V _ref2 is expressed by the following equation.

Among them, K ₂₀₁ >K ₃₀₁ .

As can be seen from equation (6), the value of the voltage V _ref2 is a reference voltage determined by V _tnh , V _tnl , K ₂₀₁ , K ₂₀₂ , K ₃₀₁ , and K ₃₀₂ . Further, when the temperature characteristics are corrected, it is only necessary to adjust the values of K ₂₀₁ , K ₂₀₂ , K ₃₀₁ , and K ₃₀₂ .

The NMOS transistors 203 and 204 constitute a current mirror circuit. Since the potentials of the PMOS transistors 105 and 106 are the same between the gate terminal terminals, the same current flows in each of the transistor systems. Therefore, the same current flows through the resistors 601 and 602, and the reference voltage V _ref of the output terminal 401 is V _ref = VSS + V _ref2 × (R ₆₀₂ / R ₆₀₁ ), and the voltage V _ref2 can be output to form a resistance ratio R _{602 .} /R ₆₀₁ times the arbitrary reference voltage value. In general, the deviation of the resistance ratio in the same wafer can be neglected as much as possible, so that an arbitrary reference voltage which is not affected by the process variation due to resistance can be obtained.

In the case of the P-type substrate, in the first embodiment, since the back gate bias is applied to the NMOS transistor 302, the effect of determining the reference voltage value is added to the back gate bias effect of the NMOS transistor 302 due to process variation. The cause of the deviation will increase. However, in the second embodiment, even when a P-type substrate is used, since the back gate bias is not applied to the transistor that determines the reference voltage value, the reference voltage value is only V _tnl , V _tnh , K . The values of ₂₀₁ , K ₂₀₂ , K ₃₀₁ , and K ₃₀₂ are determined. Therefore, according to the configuration of the second embodiment of the present invention, even when a P-type substrate is used, the variation due to the variation of the reference voltage process is less, and the reference voltage value or its temperature can be reduced. The correction value of the feature.

Here, the NMOS transistors 201 to 204 use transistors having the same threshold voltage V _tnh , but if a pair of current mirror circuits can be formed by the NMOS transistors 203 and 204, the threshold value can also be combined with the NMOS transistor. 201, 202 are different. Further, the NMOS transistors 301 to 303 use a transistor having the same threshold voltage V _tnl , but the NMOS transistor 303 may also use a transistor having a relative operating power supply voltage and having an appropriate threshold voltage different from the others.

The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. The 汲 terminal current ratio of the transistor is used to correct the reference voltage value.

According to the above, the deviation due to the process variation of the resistor does not occur, and when the temperature characteristic is corrected, the reference value can be easily corrected by adjusting only the values of K ₂₀₁ , K ₂₀₂ , K ₃₀₁ , and K ₃₀₂ . Voltage.

[Example 3]

Fig. 4 is a circuit diagram showing a reference voltage circuit of the third embodiment.

The reference voltage circuit of the third embodiment includes PMOS transistors 101, 701, and 702, NMOS transistors 201 and 202, an output terminal 401, a power supply terminal 501, and a ground terminal 502. The absolute value of the threshold voltage (hereinafter _referred to as V _tpl ) of the PMOS transistors 701 and 702 | V _tpl | is lower than the absolute value of the threshold voltage of the PMOS transistor 101 (hereinafter _referred to as V _tph ) | V _tph |. The K values of the PMOS transistors ₁₀₁ , ₇₀₁ , and ₇₀₂ are set to K101, K701, and K702, respectively. The NMOS transistors 201 and 202 constitute a current mirror circuit.

Next, the connection of the reference voltage circuit of the third embodiment will be described. The source terminals of the NMOS transistors 201, 202 are connected to the ground terminal 502. The gate terminal of the NMOS transistor 202 is connected to the gate terminal and the NMOS terminal of the NMOS transistor 201 and the NMOS terminal of the PMOS transistor 701. The gate terminal of the PMOS transistors 101, 701 is connected to The 汲 terminal and the gate terminal of the PMOS transistor 702 and the 汲 terminal of the NMOS transistor 202 are connected to the power supply terminal 501. The output terminal 401 is connected to the drain terminal of the PMOS transistor 101 and the source terminal of the PMOS transistor 702.

Next, the operation of the reference voltage circuit of the third embodiment will be described. The reference voltage circuit of the third embodiment is a circuit that forms a reference voltage based on the power supply terminal voltage (VDD). The circuit operation is such that the roles of the PMOS transistor and the NMOS transistor of the first embodiment are reversed. The currents flowing to the NMOS transistors 201 and 202 (hereinafter referred to as I _B ) are at the intersection of the V _GS -I _D curves of the PMOS transistors 101 and 701, and if the starting circuit is not stabilized at 0 A, It becomes a constant current determined by V _tph , V _tpl , K ₁₀₁ , and K ₇₀₁ . When the voltage between the gate and the source required to pass the current I _{B of the} PMOS transistors 101 and 702 is V _GS101B and V _GS702B , respectively, the reference voltage V _ref appearing at the output terminal 401 becomes V _ref = VDD-(| V _GS101B |-| V _GS702B |), the value of which is determined by I _B , V _tph , V _tpl , K ₁₀₁ , K ₇₀₂ . Since the current I _B is determined by V _tph , V _tpl , K ₁₀₁ , and K ₇₀₁ , the reference voltage value V _ref4 is determined only by V _tph , V _tpl , K ₁₀₁ , K ₇₀₁ , and K ₇₀₂ . In this way, a reference voltage that does not cause a variation due to a process variation of the resistor can be obtained.

Further, by setting the values of K ₁₀₁ and K ₇₀₂ , it is possible to _correct the temperature characteristics of the reference voltage value V _ref with respect to the temperature characteristics of I _B , V _GS101B , and V _GS702B .

When all the transistors operate in the saturation region, the constant current I _B and the reference voltage V _ref are expressed by the following equation.

Among them, K ₁₀₁ >K ₇₀₁ .

Among them, K ₁₀₁ >K ₇₀₁ .

As can be seen from (8), the value of the reference voltage V _{ref is} a reference voltage determined by V _tph , V _tpl , K ₁₀₁ , K ₇₀₁ , and K ₇₀₂ . Further, when the temperature characteristics are corrected, it is only necessary to adjust the values of K ₁₀₁ , K ₇₀₁ , and K ₇₀₂ .

The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. The 汲 terminal current ratio of the transistor is used to correct the reference voltage value.

According to the above, it is possible to prevent the variation due to the resistance variation of the process, and when the temperature characteristic is corrected, the reference voltage can be easily corrected by adjusting only the values of K ₁₀₁ , K ₇₀₁ , and K ₇₀₂ .

[Example 4]

Fig. 5 is a circuit diagram showing a reference voltage circuit of the fourth embodiment.

The reference voltage circuit of the fourth embodiment includes PMOS transistors 101 to 104, 701 to 703, NMOS transistors 201 to 206, an output terminal 401, a power supply terminal 501, a ground terminal 502, and resistors 601 and 602. The absolute value of the threshold voltage | V _tpl | of the PMOS transistors 701, 702 is lower than the absolute value of the threshold voltage | V _tph | of the PMOS transistors 101, 102. The K values of the PMOS transistors ₁₀₁ , ₁₀₂ , ₇₀₁ , and _{702 are K101} , _K102 , _K701 , and _{K702, respectively} . The resistance values of the resistors ₆₀₁ and ₆₀₂ are set to R ₆₀₁ and R ₆₀₂ , respectively. The PMOS transistors 103 and 104 constitute a current mirror circuit, and the NMOS transistor 201 and the NMOS transistors 202, 203, and 204 constitute a current mirror circuit.

Next, the connection of the reference voltage circuit of the fourth embodiment will be described. The source terminals of the NMOS transistors 201 to 206 are connected to the ground terminal 502. The gate terminals of the NMOS transistors 202-204 are connected to the gate terminal and the NMOS terminal 201 of the NMOS transistor 201 and the NMOS terminal of the PMOS transistor 701. The gate terminals of the PMOS transistors 101 and 701 are connected to the NMOS terminal of the PMOS transistor 101 and the NMOS terminal of the NMOS transistor 202, and the source terminal is connected to the power supply terminal 501. One end of the resistor 601 is connected to the gate terminal of the PMOS transistor 102 and the source terminal of the PMOS transistor 703, and the other end is connected to the gate terminal of the PMOS transistor 104 and the gate terminal of the PMOS transistor 702. The 汲 terminal of the PMOS transistor 102 is connected to the NMOS terminal of the NMOS transistor 203 and the gate terminal of the PMOS transistor 703, and the source terminal is connected to the power supply terminal 501. The 汲 terminal of the PMOS transistor 703 is connected to the ground terminal 502. The 汲 terminal of the PMOS transistor 702 is connected to the NMOS terminal of the NMOS transistor 204 and the NMOS The gate terminals of the crystals 205, 206 are connected to the power supply terminal 501. The gate terminals of the PMOS transistors 103 and 104 are connected to the NMOS terminal of the PMOS transistor 103 and the NMOS terminal of the NMOS transistor 205, and the source terminal is connected to the power supply terminal 501. One end of the resistor 602 is connected to the NMOS terminal of the NMOS transistor 206 and the output terminal 401, and the other end is connected to the power supply terminal 501.

Next, the operation of the reference voltage circuit of the fourth embodiment will be described. The reference voltage circuit of the fourth embodiment reverses the action of the PMOS transistor and the NMOS transistor of the second embodiment. The current flowing to the NMOS transistors 201 to 204 is a constant current (I _B ) determined by the above-described V _tph , V _tpl , K ₁₀₁ , and K ₇₀₁ in the third embodiment. When the voltage V _GS required to flow the current I _B in the PMOS transistors 102 and 702 is V _GS102B and V _GS702B , respectively, the voltage V _ref5 appearing at both ends of the resistor 601 becomes V _ref5 =| V _GS102B |-| V _GS702B |, the value is determined by I _B , V _tpl , V _tph , K ₁₀₂ , K ₇₀₂ . Since the current I _B is determined by V _tph , V _tpl , K ₁₀₁ , and K ₇₀₁ , by taking out the voltage V _ref5 , it is possible to prevent V _tph , V _tpl , K ₁₀₁ , K ₁₀₂ , K ₇₀₁ , K from occurring. The reference voltage of the deviation due to the process variation caused by the resistance determined by the value of ₇₀₂ . Further, by adjusting the values of K ₁₀₂ and K ₇₀₂ , it is possible to _correct the temperature characteristics of the voltages V _{ref5 with respect to} the temperature characteristics of I _B , V _{GS 102B} , and V _{GS 702 B} .

If all of the transistors operate in the saturation _region , the voltage V _ref5 is expressed by the following equation.

Among them, K ₁₀₁ >K ₇₀₁ .

As can be seen from equation (9), the value of the voltage V _ref5 is a reference voltage determined by V _tph , V _tpl , K ₁₀₁ , K ₁₀₂ , K ₇₀₁ , and K ₇₀₂ . Further, when the temperature characteristics are corrected, only the values of K ₁₀₁ , K ₁₀₂ , K ₇₀₁ , and K ₇₀₂ may be adjusted.

Since the PMOS transistor 104 and the NMOS transistor 206 are connected to the same current, the reference voltage V _ref of the output terminal 401 is V _ref = VDD - V _ref5 × (R ₆₀₂ / R ₆₀₁ ), and the output voltage V _ref5 can be output. R ₆₀₂ /R ₆₀₁ times the power supply terminal voltage reference for any reference voltage value. In general, the deviation of the resistance ratio in the same wafer can be neglected, so that an arbitrary reference voltage which does not cause an influence of process variation due to resistance can be obtained.

The reference voltage circuit of the fourth embodiment is a circuit that forms a reference voltage based on the power supply terminal voltage (VDD). When an N-type substrate is used, the reference voltage value is not affected by the back gate bias effect. In the circuit of the third embodiment, since the back gate bias is applied to the PMOS transistor 702 of FIG. 4, the effect of determining the reference voltage value is added to the back gate bias effect of the PMOS transistor 702 due to process variation. The cause of the deviation will increase. However, in the fourth embodiment, even when an N-type substrate is used, the back gate bias is not applied to the transistor that determines the reference voltage value, so the reference voltage value is only V _tpl , V _tph , K . The values of ₁₀₁ , K ₁₀₂ , K ₇₀₁ , and K ₇₀₂ are determined. Therefore, according to the configuration of the fourth embodiment of the present invention, even when the N-type substrate is used, the variation due to the process variation is less, and the correction of the reference voltage value or its temperature characteristic can be reduced. value.

Here, the PMOS transistors 101 to 104 use transistors having the same threshold voltage V _tph , but if the PMOS transistors 103 and 104 constitute a current mirror circuit, even if the threshold value is different from the PMOS transistors 101 and 102 can. Further, the PMOS transistors 701 to 703 use a transistor having the same threshold voltage V _tpl , but the PMOS transistor 703 may also use a transistor having an appropriate threshold voltage different from that according to the operating power supply voltage.

The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. The 汲 terminal current ratio of the transistor is used to correct the reference voltage value.

With the above, can be obtained due to variation of the resistance of the process will not be changed, while correcting temperature characteristics, by adjusting only the _{K 101, K 102, K 701} , K ₇₀₂ a value can be easily corrected reference voltage .

As described above, the reference voltage circuit of the present invention may be configured to include a first MOS transistor, and a second MOS transistor whose gate terminal is connected to the gate terminal of the first MOS transistor. And having an absolute value and a K value that are higher than a threshold value of a threshold value of the first MOS transistor and a K value; and a current mirror circuit that is based on a threshold value of the first MOS transistor and the second MOS transistor The absolute value of the difference a current; a third MOS transistor, which is a current flowing through the current mirror circuit; and a fourth MOS transistor having an absolute value of a threshold value higher than a threshold value of the third MOS transistor and a K value, and K The current flowing through the current mirror circuit is a constant voltage output based on the difference between the absolute value of the third MOS transistor and the fourth MOS transistor and the K value as the reference voltage.

Therefore, the circuit for generating a constant voltage of the reference voltage circuit shown in the embodiment or the circuit for outputting the constant voltage as the reference voltage is not limited to the circuits.

101~106‧‧‧ PMOS transistor

201~206‧‧‧ NMOS transistor

301~303‧‧‧ NMOS transistor with low threshold

401‧‧‧Output terminal

501‧‧‧Power terminal

502‧‧‧ Grounding terminal

601, 602‧‧‧ resistance

701~703‧‧‧ PMOS transistor with low absolute value

Fig. 1 is a circuit diagram showing a reference voltage circuit of the first embodiment.

2 is a graph showing a curve of a gate-to-source voltage versus a terminal current of two NMOS transistors having different thresholds and K values.

Fig. 3 is a circuit diagram showing a reference voltage circuit of the second embodiment.

Fig. 4 is a circuit diagram showing a reference voltage circuit of the third embodiment.

Fig. 5 is a circuit diagram showing a reference voltage circuit of the fourth embodiment.

Figure 6 is a circuit diagram showing a conventional reference voltage circuit.

101, 102‧‧‧ PMOS transistor

201‧‧‧ NMOS transistor

301, 302‧‧‧ NMOS transistors with low threshold

401‧‧‧Output terminal

501‧‧‧Power terminal

502‧‧‧ Grounding terminal

Claims (3)

A reference voltage circuit comprising: a first MOS transistor having a source terminal connected to a first power supply terminal; and a second MOS transistor having a source terminal connected to a first power supply terminal and a gate terminal And being connected to the gate terminal of the first MOS transistor, and having an absolute value and a K value which are higher than a threshold value of a threshold value and a K value of the threshold value of the first MOS transistor; and a current mirror circuit a current according to a difference between an absolute value of a threshold value of the first MOS transistor and the second MOS transistor; a third MOS transistor that is a current that flows through the current mirror circuit; and a fourth MOS transistor that has a higher value The absolute value of the threshold value of the third MOS transistor and the absolute value of the threshold value of the K value and the K value, and the current flowing through the current mirror circuit is based on the third MOS transistor and the fourth MOS transistor. The absolute value of the limit value and the constant voltage output of the K value are used as the reference voltage. The reference voltage circuit according to claim 1, wherein the current mirror circuit includes: a fifth MOS transistor, wherein the 汲 terminal and the gate terminal are connected to the 汲 terminal of the first MOS transistor; a 6MOS transistor having a gate terminal connected to a gate terminal of the fifth MOS transistor, and a gate terminal connected to a gate terminal and a gate terminal of the second MOS transistor; In the seventh MOS transistor, the gate terminal is connected to the gate terminal of the fifth MOS transistor, the 汲 terminal is connected to the 汲 terminal of the third MOS transistor; and the eighth MOS transistor is connected to the gate terminal. a gate terminal connected to the fifth MOS transistor, a 汲 terminal connected to the 汲 terminal of the fourth MOS transistor; and a resistor, wherein one of the terminals is connected to the gate terminal of the third MOS transistor, and One terminal is connected to the gate terminal of the fourth MOS transistor, and a constant voltage output based on the voltage across the resistor is used as a reference voltage. The reference voltage circuit of claim 1, wherein the current mirror circuit includes: a fifth MOS transistor, wherein the 汲 terminal and the gate terminal are connected to the 汲 terminal of the first MOS transistor; In the sixth MOS transistor, the gate terminal is connected to the gate terminal of the fifth MOS transistor, and the gate terminal is connected to the gate terminal and the gate terminal of the third MOS transistor, and the third MOS transistor is formed. In order to connect the gate terminal to the gate terminal of the second MOS transistor and to connect the source terminal to the gate terminal of the second MOS transistor, the fourth MOS transistor and the second MOS transistor are common to each other. Thereby, the reference voltage is output from a connection point of the source terminal of the third MOS transistor and the gate terminal of the second MOS transistor.