TWI541627B - Reference voltage circuit - Google Patents

Reference voltage circuit Download PDF

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TWI541627B
TWI541627B TW101135095A TW101135095A TWI541627B TW I541627 B TWI541627 B TW I541627B TW 101135095 A TW101135095 A TW 101135095A TW 101135095 A TW101135095 A TW 101135095A TW I541627 B TWI541627 B TW I541627B
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terminal
mos transistor
reference voltage
value
transistor
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TW101135095A
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TW201333660A (en
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Taro Yamasaki
Fumiyasu Utsunomiya
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Sii Semiconductor Corp
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26Current mirrors
    • G05F3/262Current mirrors using field-effect transistors only
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26Current mirrors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Control Of Electrical Variables (AREA)

Description

基準電壓電路 Reference voltage circuit

本發明係關於基準電壓電路。 The present invention relates to a reference voltage circuit.

圖6係顯示習知之基準電壓電路的電路圖。 Figure 6 is a circuit diagram showing a conventional reference voltage circuit.

習知之基準電壓電路係具備有:PMOS電晶體101~103、NMOS電晶體201~204、301、輸出端子401、電源端子501、接地端子502、及電阻601。NMOS電晶體301的臨限值電壓(以下設為Vtnl)係低於NMOS電晶體201~204的臨限值電壓(以下設為Vtnh)。PMOS電晶體102與103係構成PMOS電晶體101與電流鏡電路,流通PMOS電晶體101的汲極端子電流的希望比的汲極端子電流。NMOS電晶體204係構成NMOS電晶體203與電流鏡電路,流通NMOS電晶體203的汲極端子電流的希望比的汲極端子電流。 The conventional reference voltage circuit includes PMOS transistors 101 to 103, NMOS transistors 201 to 204 and 301, an output terminal 401, a power supply terminal 501, a ground terminal 502, and a resistor 601. The threshold voltage of the NMOS transistor 301 (hereinafter referred to as V tnl ) is lower than the threshold voltage of the NMOS transistors 201 to 204 (hereinafter referred to as V tnh ). The PMOS transistors 102 and 103 constitute a PMOS transistor 101 and a current mirror circuit, and a 汲 terminal current of a desired ratio of the 汲 terminal current of the PMOS transistor 101 flows. The NMOS transistor 204 constitutes an NMOS transistor 203 and a current mirror circuit, and flows through the 汲 terminal current of a desired ratio of the 汲 terminal current of the NMOS transistor 203.

PMOS電晶體101~103的源極端子係被連接於電源端子。PMOS電晶體102及103的閘極端子係被連接於PMOS電晶體101的閘極端子及汲極端子、NMOS電晶體201的汲極端子。NMOS電晶體201及202的閘極端子係被連接於NMOS電晶體201的汲極端子及PMOS電晶體102的汲極端子。NMOS電晶體202的源極端子係被連接於接地端子。電阻601的一端係被連接於NMOS電晶體201的源極端子,另一端係被連接於接地端子。NMOS電 晶體203、204及301的閘極端子係被連接於NMOS電晶體203及PMOS電晶體103的汲極端子。NMOS電晶體203及204的源極端子係被連接於接地端子。NMOS電晶體301的汲極端子係被連接於電源端子。輸出端子401係被連接於NMOS電晶體204的汲極端子及NMOS電晶體301的源極端子。 The source terminals of the PMOS transistors 101 to 103 are connected to the power supply terminals. The gate terminals of the PMOS transistors 102 and 103 are connected to the gate terminal and the gate terminal of the PMOS transistor 101, and the gate terminal of the NMOS transistor 201. The gate terminals of the NMOS transistors 201 and 202 are connected to the NMOS terminal of the NMOS transistor 201 and the NMOS terminal of the PMOS transistor 102. The source terminal of the NMOS transistor 202 is connected to a ground terminal. One end of the resistor 601 is connected to the source terminal of the NMOS transistor 201, and the other end is connected to the ground terminal. NMOS The gate terminals of the crystals 203, 204, and 301 are connected to the NMOS terminals of the NMOS transistor 203 and the PMOS transistor 103. The source terminals of the NMOS transistors 203 and 204 are connected to a ground terminal. The 汲 terminal of the NMOS transistor 301 is connected to a power supply terminal. The output terminal 401 is connected to the NMOS terminal of the NMOS transistor 204 and the source terminal of the NMOS transistor 301.

NMOS電晶體201~204、301的K值係分別為K201、K202、K203、K204及K301,電阻601的電阻值為R601The K values of the NMOS transistors 201 to 204 and 301 are K 201 , K 202 , K 203 , K 204 and K 301 , respectively, and the resistance value of the resistor 601 is R 601 .

PMOS電晶體101與102、NMOS電晶體201與202、及電阻601係構成定電流電路。例如,各電晶體在飽和領域進行動作時,若PMOS電晶體101與102的K值相等,流至PMOS電晶體101與102的電流係相等,該電流值為0A或取某定電流值(以下設為IK)。以電流不會成為0A的方式設置起動電路,藉此PMOS電晶體101與102、NMOS電晶體201與202、及電阻601係作為定電流電路來進行動作。定電流IK係以下式表示。 The PMOS transistors 101 and 102, the NMOS transistors 201 and 202, and the resistor 601 constitute a constant current circuit. For example, when each transistor operates in the saturation region, if the K values of the PMOS transistors 101 and 102 are equal, the currents flowing to the PMOS transistors 101 and 102 are equal, and the current value is 0 A or a certain current value (hereinafter). Set to I K ). The starter circuit is provided so that the current does not become 0A, whereby the PMOS transistors 101 and 102, the NMOS transistors 201 and 202, and the resistor 601 operate as a constant current circuit. The constant current I K is expressed by the following equation.

其中,K201>K202Where K 201 >K 202 .

在PMOS電晶體103係使定電流IK作鏡像(mirror),在NMOS電晶體204係使PMOS電晶體103的汲極端子電流作鏡像。例如,若圖6的電晶體全部在飽和領域進行動作時,若PMOS電晶體101與103的K值相等,NMOS電晶體203與204的K值相等,在NMOS電晶體204與 301係流通定電流IK。將NMOS電晶體204與301流通定電流IK所需的閘極源極間電壓分別設為VGS204K、VGS301K時,輸出端子401的電壓(以下設為VrefK),若使用(1)式時,係以下式表示。 In the PMOS transistor 103, the constant current I K is mirrored, and the NMOS transistor 204 mirrors the 汲 terminal current of the PMOS transistor 103. For example, when all of the transistors of FIG. 6 operate in the saturation region, if the K values of the PMOS transistors 101 and 103 are equal, the K values of the NMOS transistors 203 and 204 are equal, and the constant current flows through the NMOS transistors 204 and 301. I K. When the voltage between the gate and the source required to supply the constant current I K to the NMOS transistors 204 and 301 is V GS204K and V GS301K , respectively, the voltage of the output terminal 401 (hereinafter referred to as V refK ), if (1) is used When it is expressed by the following formula.

其中,K201>K202Where K 201 >K 202 .

如上所述,圖6的基準電壓電路係輸出以Vtnl、Vtnh、K201、K202、K204、K301、R601所決定的基準電壓VrefK的電路。 As described above, the reference voltage circuit of FIG. 6 to the output line V tnl, V tnh, K 201 , K 202, K 204, K 301, R 601 determined by the reference voltage V refK circuit.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開2007-148530號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-148530

但是,在圖6所示之習知之基準電壓電路中,由(2)式,除了電晶體的K值及臨限值以外,電阻值決定基準電壓值,因此會有對製程變動的影響或溫度特性的影響變大的課題。此外,若以減小基準電壓值的溫度特性的方式進行補正時,亦會有因製程變動所致之偏差要因增加的 課題。此外,為了進行補正,由於必須內置溫度感測器或補正用的邏輯電路,因此會有電路規模增大的課題。 However, in the conventional reference voltage circuit shown in FIG. 6, the equation (2), in addition to the K value and the threshold value of the transistor, the resistance value determines the reference voltage value, so there is an influence on the process variation or temperature. The problem of the influence of characteristics becomes large. In addition, if the correction is performed in such a manner as to reduce the temperature characteristic of the reference voltage value, there is also an increase in the variation due to process variation. Question. In addition, in order to perform correction, since it is necessary to incorporate a temperature sensor or a logic circuit for correction, there is a problem that the circuit scale is increased.

本發明係鑑於上述課題而研創者,提供一種不會增加電路規模,而可減少因製程變動所致之偏差要因,且將基準電壓值、及基準電壓值的溫度特性輕易地補正為所希望範圍內的基準電壓電路。 The present invention has been made in view of the above problems, and provides a method for reducing the variation of the reference voltage value and the reference voltage value to a desired range without increasing the circuit scale. The reference voltage circuit inside.

本發明之基準電壓電路係為解決上述課題,形成為以下構成:具備有:第1MOS電晶體;第2MOS電晶體,其係閘極端子被連接於第1MOS電晶體的閘極端子,且具有高於第1MOS電晶體的臨限值的絕對值與K值的臨限值的絕對值與K值;電流鏡電路,其係流通根據第1MOS電晶體與第2MOS電晶體的臨限值的絕對值的差的電流;第3MOS電晶體,其係流通電流鏡電路的電流;及第4MOS電晶體,其係具有高於第3MOS電晶體的臨限值的絕對值與K值的臨限值的絕對值與K值,且流通電流鏡電路的電流,將根據第3MOS電晶體與第4MOS電晶體的臨限值的絕對值與K值的差的定電壓輸出作為基準電壓。 In order to solve the above problems, the reference voltage circuit of the present invention has a configuration in which a first MOS transistor is provided, and a second MOS transistor is connected to a gate terminal of the first MOS transistor and has a high voltage. The absolute value and the K value of the absolute value of the threshold value of the first MOS transistor and the K value; and the current mirror circuit that distributes the absolute value of the threshold value according to the first MOS transistor and the second MOS transistor a differential current; a third MOS transistor, which is a current flowing through the current mirror circuit; and a fourth MOS transistor having an absolute value that is higher than a threshold value of the third MOS transistor and a threshold value of the K value. The value and the K value, and the current flowing through the current mirror circuit, is based on the constant voltage output of the difference between the absolute value of the third MOS transistor and the fourth MOS transistor and the K value as the reference voltage.

若使用本發明之基準電壓電路,不會使電路規模增大,而可減小因電阻的製程變動所致之基準電壓值的偏差、或基準電壓值或溫度特性的補正值的偏差。 When the reference voltage circuit of the present invention is used, the variation in the reference voltage value due to the variation of the resistance process or the variation in the correction value of the reference voltage value or the temperature characteristic can be reduced without increasing the circuit scale.

以下參照圖示,說明本實施形態。 The present embodiment will be described below with reference to the drawings.

[實施例1] [Example 1]

圖1係顯示第1實施形態之基準電壓電路的電路圖。 Fig. 1 is a circuit diagram showing a reference voltage circuit of the first embodiment.

第1實施形態之基準電壓電路係具備有:PMOS電晶體101、102、NMOS電晶體201、301、302、輸出端子401、電源端子501、及接地端子502。NMOS電晶體301、302的臨限值電壓(以下設為Vtnl)係低於NMOS電晶體201的臨限值電壓(以下設為Vtnh)。NMOS電晶體201、301、302的K值分別為K201、K301、K302。PMOS電晶體101與PMOS電晶體102係構成電流鏡電路。 The reference voltage circuit of the first embodiment includes PMOS transistors 101 and 102, NMOS transistors 201, 301 and 302, an output terminal 401, a power supply terminal 501, and a ground terminal 502. The threshold voltage of the NMOS transistors 301 and 302 (hereinafter referred to as V tnl ) is lower than the threshold voltage of the NMOS transistor 201 (hereinafter referred to as V tnh ). The K values of the NMOS transistors 201 , 301 , and 302 are K 201 , K 301 , and K 302 , respectively . The PMOS transistor 101 and the PMOS transistor 102 constitute a current mirror circuit.

接著,說明第1實施形態之基準電壓電路的連接。 Next, the connection of the reference voltage circuit of the first embodiment will be described.

PMOS電晶體101、102的源極端子係被連接於電源端子501。PMOS電晶體102的閘極端子係被連接於PMOS電晶體101的閘極端子及汲極端子與NMOS電晶體301的汲極端子。NMOS電晶體201、301的閘極端子係被連接於NMOS電晶體302的汲極端子及閘極端子與PMOS電晶體102的汲極端子,源極端子係被連接於接地端子502。輸出端子401係被連接於NMOS電晶體201的汲極端子與NMOS電晶體302的源極端子。 The source terminals of the PMOS transistors 101, 102 are connected to the power supply terminal 501. The gate terminal of the PMOS transistor 102 is connected to the gate terminal and the gate terminal of the PMOS transistor 101 and the gate terminal of the NMOS transistor 301. The gate terminals of the NMOS transistors 201 and 301 are connected to the NMOS terminal and the gate terminal of the NMOS transistor 302 and the NMOS terminal 102, and the source terminal is connected to the ground terminal 502. The output terminal 401 is connected to the drain terminal of the NMOS transistor 201 and the source terminal of the NMOS transistor 302.

接著,說明第1實施形態之基準電壓電路的動作。 Next, the operation of the reference voltage circuit of the first embodiment will be described.

將PMOS電晶體101、102的汲極端子電流分別設為 I101、I102。將輸出端子401的電壓設為Vref。PMOS電晶體101、102係構成電流鏡電路,因此若各自的K值相等,電流I101與電流I102係流通相等的電流。在圖2中顯示NMOS電晶體201與NMOS電晶體301在飽和領域進行動作時之閘極源極間電壓(以下設為VGS)對汲極端子電流(以下設為ID)特性。各個曲線的上升位置與斜率係分別藉由臨限值電壓與K值來決定。由於電流I101與電流I102相等,NMOS電晶體201與NMOS電晶體301的閘極端子係相連接,因此若該2個電晶體在飽和領域進行動作,電壓VGS係成為A點。若設置起動電路,電流I101(=I102)係成為A點的電流值(以下設為IA),該值係藉由Vtnl、Vtnh、K201、K301而如下式表示。 The 汲 terminal currents of the PMOS transistors 101 and 102 are set to I 101 and I 102 , respectively. The voltage of the output terminal 401 is set to V ref . Since the PMOS transistors 101 and 102 constitute a current mirror circuit, if the respective K values are equal, the current I 101 and the current I 102 are equal in current. FIG. 2 shows the characteristics of the gate-to-source voltage (hereinafter referred to as V GS ) versus the terminal current (hereinafter referred to as I D ) when the NMOS transistor 201 and the NMOS transistor 301 operate in the saturation region. The rising position and the slope of each curve are determined by the threshold voltage and the K value, respectively. Since the current I 101 is equal to the current I 102 , the NMOS transistor 201 is connected to the gate terminal of the NMOS transistor 301. Therefore, if the two transistors operate in the saturation region, the voltage V GS becomes the point A. When the start-up circuit is provided, the current I 101 (=I 102 ) is the current value at point A (hereinafter referred to as I A ), and the value is expressed by V tnl , V tnh , K 201 , and K 301 as follows.

其中,K201>K301Among them, K 201 >K 301 .

若將NMOS電晶體201、302流通電流IA所需的電壓VGS分別設為VGS201A、VGS302A、將接地端子電壓設為VSS時,輸出端子401的基準電壓Vref係成為Vref=VSS+VGS201A-VGS302A。電壓VGS201A、電壓VGS302A的值係以IA、Vtnl、Vtnh、K201、K302的值決定。由(3)式,電流IA係以Vtnl、Vtnh、K201、K301的值決定,因此輸出端子401的基準電壓Vref的值係僅以Vtnh、Vtnl、K201、K301、K302的值決定。 When the voltages V GS required to pass the current I A of the NMOS transistors 201 and 302 are V GS201A and V GS302A , respectively, and the ground terminal voltage is VSS, the reference voltage V ref of the output terminal 401 is V ref = VSS. +V GS201A -V GS302A . The values of voltage V GS201A and voltage V GS302A are determined by the values of I A , V tnl , V tnh , K 201 , and K 302 . Since the current I A is determined by the values of V tnl , V tnh , K 201 , and K 301 , the value of the reference voltage V ref of the output terminal 401 is only V tnh , V tnl , K 201 , K . The values of 301 and K 302 are determined.

若NMOS電晶體201與NMOS電晶體302在飽和領 域進行動作,基準電壓Vref係以下式表示。 When the NMOS transistor 201 and the NMOS transistor 302 operate in the saturation region, the reference voltage V ref is expressed by the following equation.

在此,若所有電晶體在飽和領域進行動作,在(4)式的電流IA代入(3)式,基準電壓Vref係以下式表示。 Here, if all of the transistors operate in the saturation region, the current I A of the equation (4) is substituted into the equation (3), and the reference voltage V ref is expressed by the following equation.

其中,K201>K301Among them, K 201 >K 301 .

由(5)式可知,基準電壓Vref的值係以Vtnh、Vtnl、K201、K301、K302所決定的電壓。如此一來,可得不會發生因電阻之製程變動所致之偏差的基準電壓。此外,補正溫度特性時,僅調整K201、K301、K302的值即可輕易進行補正。 As can be seen from equation (5), the value of the reference voltage V ref is a voltage determined by V tnh , V tnl , K 201 , K 301 , and K 302 . In this way, a reference voltage that does not cause a variation due to a process variation of the resistor can be obtained. In addition, when the temperature characteristics are corrected, only the values of K 201 , K 301 , and K 302 can be adjusted to easily correct them.

在此,係以NMOS電晶體201、301、302在飽和領域進行動作的情形為例,但是即使任一者或全部在弱反轉領域進行動作,亦若以兩電晶體的VGS對ID曲線相交的方式設定K201、K301,即可形成前述以Vtnl、Vtnh、K201、及K301的值所決定的電流IA。此外,基準電壓Vref亦可以Vtnl、Vtnh、K201、K301、K302的值來決定。因此,僅藉由調整各電晶體的K值,即可進行溫度特性的補正。 Here, the case where the NMOS transistors 201, 301, and 302 operate in the saturation region is taken as an example, but even if either or all of them operate in the weak inversion domain, the V GS pair I D of the two transistors is used. By setting K 201 and K 301 in a manner in which the curves intersect, the current I A determined by the values of V tnl , V tnh , K 201 , and K 301 can be formed. Further, the reference voltage V ref may be determined by the values of V tnl , V tnh , K 201 , K 301 , and K 302 . Therefore, the temperature characteristic can be corrected only by adjusting the K value of each transistor.

其中,係以電流鏡電路的K值設為相等,藉由調整各電晶體的K值來補正基準電壓的方式為例,但是亦可藉由改變電流鏡電路的鏡像對的K值來調節各電晶體的 汲極端子電流比,來補正基準電壓值。 The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. Transistor 汲 The extreme pole current ratio is used to correct the reference voltage value.

藉由以上,可得不會發生因電阻之製程變動所致之偏差,在補正溫度特性時,藉由僅調整K201、K301、K302的值,即可輕易進行補正的基準電壓。 According to the above, it is possible to prevent variations due to variations in the process of the resistor, and when the temperature characteristics are corrected, the reference voltage can be easily corrected by adjusting only the values of K 201 , K 301 , and K 302 .

[實施例2] [Embodiment 2]

圖3係顯示第2實施形態之基準電壓電路的電路圖。 Fig. 3 is a circuit diagram showing a reference voltage circuit of the second embodiment.

第2實施形態之基準電壓電路係具備有:PMOS電晶體101~106、NMOS電晶體201~204、301~303、輸出端子401、電源端子501、接地端子502、及電阻601~602。NMOS電晶體301~302的臨限值電壓(以下設為Vtnl)係低於NMOS電晶體201~202的臨限值電壓(以下設為Vtnh)。NMOS電晶體201、202、301、302的K值係分別設為K201、K202、K301、K302。電阻601、602的電阻值係分別設為R601、R602。NMOS電晶體203、204係構成電流鏡電路。PMOS電晶體101與PMOS電晶體102、103、104係構成電流鏡電路。 The reference voltage circuit of the second embodiment includes PMOS transistors 101 to 106, NMOS transistors 201 to 204, 301 to 303, an output terminal 401, a power supply terminal 501, a ground terminal 502, and resistors 601 to 602. The threshold voltages of the NMOS transistors 301 to 302 (hereinafter referred to as V tnl ) are lower than the threshold voltages of the NMOS transistors 201 to 202 (hereinafter referred to as V tnh ). The K values of the NMOS transistors 201 , 202 , 301 , and 302 are set to K 201 , K 202 , K 301 , and K 302 , respectively . The resistance values of the resistors 601 and 602 are set to R 601 and R 602 , respectively. The NMOS transistors 203 and 204 constitute a current mirror circuit. The PMOS transistor 101 and the PMOS transistors 102, 103, and 104 constitute a current mirror circuit.

接著,說明第2實施形態之基準電壓電路的連接。 Next, the connection of the reference voltage circuit of the second embodiment will be described.

PMOS電晶體101~106的源極端子係被連接於電源端子501。PMOS電晶體102~104的閘極端子係被連接於PMOS電晶體101的閘極端子及汲極端子與NMOS電晶體301的汲極端子。NMOS電晶體201、301的閘極端子係被連接於NMOS電晶體201的汲極端子與PMOS電晶體102的汲極端子,源極端子係被連接於接地端子502。電阻 601的一端係被連接於NMOS電晶體202的閘極端子與NMOS電晶體303的源極端子,另一端係被連接於NMOS電晶體204的汲極端子與NMOS電晶體302的閘極端子。NMOS電晶體202的汲極端子係被連接於PMOS電晶體103與NMOS電晶體303的閘極端子,源極端子係被連接於接地端子。NMOS電晶體303的汲極端子係被連接於電源端子501。NMOS電晶體302的汲極端子係被連接於PMOS電晶體104的汲極端子與PMOS電晶體105、106的閘極端子,源極端子係被連接於接地端子502。NMOS電晶體203、204的閘極端子係被連接於NMOS電晶體203的汲極端子與PMOS電晶體105的汲極端子,源極端子係被連接於接地端子502。電阻602的一端係被連接於PMOS電晶體106的汲極端子與輸出端子401,另一端係被連接於接地端子502。 The source terminals of the PMOS transistors 101 to 106 are connected to the power supply terminal 501. The gate terminals of the PMOS transistors 102-104 are connected to the gate terminal and the NMOS terminal of the PMOS transistor 101 and the NMOS terminal of the NMOS transistor 301. The gate terminals of the NMOS transistors 201, 301 are connected to the ? terminal of the NMOS transistor 201 and the ? terminal of the PMOS transistor 102, and the source terminal is connected to the ground terminal 502. resistance One end of the 601 is connected to the gate terminal of the NMOS transistor 202 and the source terminal of the NMOS transistor 303, and the other end is connected to the gate terminal of the NMOS transistor 204 and the gate terminal of the NMOS transistor 302. The NMOS terminal of the NMOS transistor 202 is connected to the gate terminals of the PMOS transistor 103 and the NMOS transistor 303, and the source terminal is connected to the ground terminal. The 汲 terminal of the NMOS transistor 303 is connected to the power supply terminal 501. The NMOS terminal of NMOS transistor 302 is connected to the NMOS terminal 104 and the PMOS transistor 105, 106, and the source terminal is connected to ground terminal 502. The gate terminals of the NMOS transistors 203, 204 are connected to the ? terminal of the NMOS transistor 203 and the ? terminal of the PMOS transistor 105, and the source terminal is connected to the ground terminal 502. One end of the resistor 602 is connected to the 汲 terminal of the PMOS transistor 106 and the output terminal 401, and the other end is connected to the ground terminal 502.

接著,說明第2實施形態之基準電壓電路的動作。將輸出端子401的電壓設為基準電壓Vref。流至PMOS電晶體101、102的電流係若K值相等,則為以第1實施形態之(3)式所述之Vtnl、Vtnh、K201、K301的值所決定的電流IANext, the operation of the reference voltage circuit of the second embodiment will be described. The voltage of the output terminal 401 is set to the reference voltage V ref . The current flowing to the PMOS transistors 101 and 102 is the current I A determined by the values of V tnl , V tnh , K 201 , and K 301 described in the equation (3) of the first embodiment, if the K values are equal. .

流至PMOS電晶體103、104的電流係PMOS電晶體103、104構成PMOS電晶體101與電流鏡電路,因此若各自K值相同,則流通電流IAThe current-based PMOS transistors 103 and 104 flowing to the PMOS transistors 103 and 104 constitute the PMOS transistor 101 and the current mirror circuit. Therefore, if the respective K values are the same, the current I A flows.

NMOS電晶體303係以NMOS電晶體202的閘極源極間電壓成為流通電流IA所需電壓的方式控制NMOS電晶 體202的閘極端子電壓。PMOS電晶體104、NMOS電晶體203、NMOS電晶體204係以NMOS電晶體302的閘極源極間電壓成為流通電流IA所需電壓的方式控制NMOS電晶體302的閘極端子電壓。 The NMOS transistor 303 controls the gate terminal voltage of the NMOS transistor 202 such that the voltage between the gate and the source of the NMOS transistor 202 becomes the voltage required to pass the current I A . The PMOS transistor 104, the NMOS transistor 203, and the NMOS transistor 204 control the gate terminal voltage of the NMOS transistor 302 such that the voltage between the gate and the source of the NMOS transistor 302 becomes the voltage required to pass the current I A .

若將NMOS電晶體202、302流通電流IA所需之閘極源極間電壓分別設為電壓VGS202A、電壓VGS302A時,在電阻601的兩端係出現VGS202A-VGS302A的電壓Vref2。該電壓Vref2係以IA、Vtnl、Vtnh、K202、K302的值所決定。電流IA係以Vtnl、Vtnh、K201、K301的值決定,因此電壓Vref2亦即係以Vtnl、Vtnh、K201、K202、K301、K302的值決定。如此一來可得不會發生因電阻之製程變動所致之偏差的基準電壓。此外,電壓Vref2的溫度特性係藉由調整K202、K302的值,即可補正為相對於IA、VGS202A、VGS302A的溫度特性成為平緩。 When the voltage between the gate and the source required for the NMOS transistors 202 and 302 to pass the current I A is set to the voltage V GS202A and the voltage V GS302A respectively, the voltage V ref2 of the V GS202A -V GS302A appears at both ends of the resistor 601. . The voltage V ref2 is determined by the values of I A , V tnl , V tnh , K 202 , and K 302 . Since the current I A is determined by the values of V tnl , V tnh , K 201 , and K 301 , the voltage V ref2 is determined by the values of V tnl , V tnh , K 201 , K 202 , K 301 , and K 302 . In this way, a reference voltage that does not cause a variation due to a process variation of the resistor can be obtained. Further, the temperature characteristics of the voltage V ref2 can be corrected to be gentle with respect to the temperature characteristics of I A , V GS 202A , and V GS 302 A by adjusting the values of K 202 and K 302 .

各電晶體在飽和領域進行動作時,電壓Vref2的值係以下式表示。 When each transistor operates in the saturation region , the value of the voltage V ref2 is expressed by the following equation.

其中,K201>K301Among them, K 201 >K 301 .

由(6)式可知,電壓Vref2的值係以Vtnh、Vtnl、K201、K202、K301、K302所決定的基準電壓。此外,在補正溫度特性時,若僅調整K201、K202、K301、K302的值即可。 As can be seen from equation (6), the value of the voltage V ref2 is a reference voltage determined by V tnh , V tnl , K 201 , K 202 , K 301 , and K 302 . Further, when the temperature characteristics are corrected, it is only necessary to adjust the values of K 201 , K 202 , K 301 , and K 302 .

NMOS電晶體203、204係構成電流鏡電路,PMOS電晶體105、106由於閘極端子源極端子間電位相同,因此在各電晶體係流通相同的電流。因此,在電阻601、602亦流通相同的電流,輸出端子401的基準電壓Vref係成為Vref=VSS+Vref2×(R602/R601),可輸出將電壓Vref2形成電阻比R602/R601倍後的任意的基準電壓值。一般而言,同一晶片內的電阻比的偏離係可忽視般可減小,因此可得不會發生因電阻所致之製程變動影響的任意的基準電壓。 The NMOS transistors 203 and 204 constitute a current mirror circuit. Since the potentials of the PMOS transistors 105 and 106 are the same between the gate terminal terminals, the same current flows in each of the transistor systems. Therefore, the same current flows through the resistors 601 and 602, and the reference voltage V ref of the output terminal 401 is V ref = VSS + V ref2 × (R 602 / R 601 ), and the voltage V ref2 can be output to form a resistance ratio R 602 . /R 601 times the arbitrary reference voltage value. In general, the deviation of the resistance ratio in the same wafer can be neglected as much as possible, so that an arbitrary reference voltage which is not affected by the process variation due to resistance can be obtained.

若為P型基板,在第1實施形態中,由於對NMOS電晶體302施加背閘極偏壓,因此在決定基準電壓值的要因加入NMOS電晶體302的背閘極偏壓效果,因製程變動所致之偏差要因會增加。但是,在第2實施形態中,即使在使用P型基板的情形下,由於不會對決定基準電壓值的電晶體施加背閘極偏壓,因此基準電壓值僅以Vtnl、Vtnh、K201、K202、K301、K302的值決定。因此,若採取本發明之第2實施形態之構成,即使在使用P型基板的情形下,亦使因基準電壓的製程變動所致之偏差要因較少,而且可減小基準電壓值或其溫度特性的補正值。 In the case of the P-type substrate, in the first embodiment, since the back gate bias is applied to the NMOS transistor 302, the effect of determining the reference voltage value is added to the back gate bias effect of the NMOS transistor 302 due to process variation. The cause of the deviation will increase. However, in the second embodiment, even when a P-type substrate is used, since the back gate bias is not applied to the transistor that determines the reference voltage value, the reference voltage value is only V tnl , V tnh , K . The values of 201 , K 202 , K 301 , and K 302 are determined. Therefore, according to the configuration of the second embodiment of the present invention, even when a P-type substrate is used, the variation due to the variation of the reference voltage process is less, and the reference voltage value or its temperature can be reduced. The correction value of the feature.

在此,NMOS電晶體201~204係使用具有相同臨限值電壓Vtnh的電晶體,但是若可由NMOS電晶體203、204來構成一對電流鏡電路,則臨限值亦可與NMOS電晶體201、202不同。此外,NMOS電晶體301~303係使用具有相同臨限值電壓Vtnl的電晶體,但是NMOS電晶體303亦可使用相對動作電源電壓,具有與其他不同之適當 臨限值電壓的電晶體。 Here, the NMOS transistors 201 to 204 use transistors having the same threshold voltage V tnh , but if a pair of current mirror circuits can be formed by the NMOS transistors 203 and 204, the threshold value can also be combined with the NMOS transistor. 201, 202 are different. Further, the NMOS transistors 301 to 303 use a transistor having the same threshold voltage V tnl , but the NMOS transistor 303 may also use a transistor having a relative operating power supply voltage and having an appropriate threshold voltage different from the others.

其中,係以電流鏡電路的K值設為相等,藉由調整各電晶體的K值來補正基準電壓的方式為例,但是亦可藉由改變電流鏡電路的鏡像對的K值來調節各電晶體的汲極端子電流比,來補正基準電壓值。 The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. The 汲 terminal current ratio of the transistor is used to correct the reference voltage value.

藉由以上,可得不會發生因電阻之製程變動所致之偏差,在補正溫度特性時,藉由僅調整K201、K202、K301、K302的值,即可輕易進行補正的基準電壓。 According to the above, the deviation due to the process variation of the resistor does not occur, and when the temperature characteristic is corrected, the reference value can be easily corrected by adjusting only the values of K 201 , K 202 , K 301 , and K 302 . Voltage.

[實施例3] [Example 3]

圖4係顯示第3實施形態之基準電壓電路的電路圖。 Fig. 4 is a circuit diagram showing a reference voltage circuit of the third embodiment.

第3實施形態之基準電壓電路係具備有:PMOS電晶體101、701、702、NMOS電晶體201、202、輸出端子401、電源端子501、及接地端子502。PMOS電晶體701、702的臨限值電壓(以下設為Vtpl)的絕對值| Vtpl |係低於PMOS電晶體101的臨限值電壓(以下設為Vtph)的絕對值| Vtph |。PMOS電晶體101、701、702的K值係分別設為K101、K701、K702。NMOS電晶體201、202係構成電流鏡電路。 The reference voltage circuit of the third embodiment includes PMOS transistors 101, 701, and 702, NMOS transistors 201 and 202, an output terminal 401, a power supply terminal 501, and a ground terminal 502. The absolute value of the threshold voltage (hereinafter referred to as V tpl ) of the PMOS transistors 701 and 702 | V tpl | is lower than the absolute value of the threshold voltage of the PMOS transistor 101 (hereinafter referred to as V tph ) | V tph |. The K values of the PMOS transistors 101 , 701 , and 702 are set to K101, K701, and K702, respectively. The NMOS transistors 201 and 202 constitute a current mirror circuit.

接著,說明第3實施形態之基準電壓電路的連接。NMOS電晶體201、202的源極端子係被連接於接地端子502。NMOS電晶體202的閘極端子係被連接於NMOS電晶體201的閘極端子及汲極端子與PMOS電晶體701的汲極端子。PMOS電晶體101、701的閘極端子係被連接於 PMOS電晶體702的汲極端子及閘極端子與NMOS電晶體202的汲極端子,源極端子係被連接於電源端子501。輸出端子401係被連接於PMOS電晶體101的汲極端子與PMOS電晶體702的源極端子。 Next, the connection of the reference voltage circuit of the third embodiment will be described. The source terminals of the NMOS transistors 201, 202 are connected to the ground terminal 502. The gate terminal of the NMOS transistor 202 is connected to the gate terminal and the NMOS terminal of the NMOS transistor 201 and the NMOS terminal of the PMOS transistor 701. The gate terminal of the PMOS transistors 101, 701 is connected to The 汲 terminal and the gate terminal of the PMOS transistor 702 and the 汲 terminal of the NMOS transistor 202 are connected to the power supply terminal 501. The output terminal 401 is connected to the drain terminal of the PMOS transistor 101 and the source terminal of the PMOS transistor 702.

接著,說明第3實施形態之基準電壓電路的動作。第3實施形態之基準電壓電路係形成以電源端子電壓(VDD)為基準的基準電壓的電路。電路動作係成為使第1實施形態之PMOS電晶體與NMOS電晶體的作用反轉者。流至NMOS電晶體201、202的電流(以下設為IB)係在PMOS電晶體101、701的VGS-ID曲線的交點,若以在0A不會安定的方式設置起動電路時,即成為以Vtph、Vtpl、K101、K701所決定的一定電流。若將PMOS電晶體101、702流通電流IB所需之閘極源極間電壓分別設為VGS101B、VGS702B時,出現在輸出端子401的基準電壓Vref係成為Vref=VDD-(| VGS101B |-| VGS702B |),其值係以IB、Vtph、Vtpl、K101、K702決定。在此電流IB係以Vtph、Vtpl、K101、K701決定,因此基準電壓值Vref4係僅以Vtph、Vtpl、K101、K701、K702決定。如此一來,可得不會發生因電阻之製程變動所致之偏差的基準電壓。 Next, the operation of the reference voltage circuit of the third embodiment will be described. The reference voltage circuit of the third embodiment is a circuit that forms a reference voltage based on the power supply terminal voltage (VDD). The circuit operation is such that the roles of the PMOS transistor and the NMOS transistor of the first embodiment are reversed. The currents flowing to the NMOS transistors 201 and 202 (hereinafter referred to as I B ) are at the intersection of the V GS -I D curves of the PMOS transistors 101 and 701, and if the starting circuit is not stabilized at 0 A, It becomes a constant current determined by V tph , V tpl , K 101 , and K 701 . When the voltage between the gate and the source required to pass the current I B of the PMOS transistors 101 and 702 is V GS101B and V GS702B , respectively, the reference voltage V ref appearing at the output terminal 401 becomes V ref = VDD-(| V GS101B |-| V GS702B |), the value of which is determined by I B , V tph , V tpl , K 101 , K 702 . Since the current I B is determined by V tph , V tpl , K 101 , and K 701 , the reference voltage value V ref4 is determined only by V tph , V tpl , K 101 , K 701 , and K 702 . In this way, a reference voltage that does not cause a variation due to a process variation of the resistor can be obtained.

此外,藉由設定K101、K702的值,可以相對於IB、VGS101B、VGS702B的溫度特性,基準電壓值Vref的溫度特性成為平緩的方式進行補正。 Further, by setting the values of K 101 and K 702 , it is possible to correct the temperature characteristics of the reference voltage value V ref with respect to the temperature characteristics of I B , V GS101B , and V GS702B .

若所有電晶體在飽和領域進行動作時,定電流IB、基準電壓Vref係以下式表示。 When all the transistors operate in the saturation region, the constant current I B and the reference voltage V ref are expressed by the following equation.

其中,K101>K701Among them, K 101 >K 701 .

其中,K101>K701Among them, K 101 >K 701 .

由(8)可知,基準電壓Vref的值係以Vtph、Vtpl、K101、K701、K702所決定的基準電壓。此外,在補正溫度特性時,若僅調整K101、K701、K702的值即可。 As can be seen from (8), the value of the reference voltage V ref is a reference voltage determined by V tph , V tpl , K 101 , K 701 , and K 702 . Further, when the temperature characteristics are corrected, it is only necessary to adjust the values of K 101 , K 701 , and K 702 .

其中,係以電流鏡電路的K值設為相等,藉由調整各電晶體的K值來補正基準電壓的方式為例,但是亦可藉由改變電流鏡電路的鏡像對的K值來調節各電晶體的汲極端子電流比,來補正基準電壓值。 The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. The 汲 terminal current ratio of the transistor is used to correct the reference voltage value.

藉由以上,可得不會發生因電阻之製程變動所致之偏差,在補正溫度特性時,藉由僅調整K101、K701、K702的值,即可輕易進行補正的基準電壓。 According to the above, it is possible to prevent the variation due to the resistance variation of the process, and when the temperature characteristic is corrected, the reference voltage can be easily corrected by adjusting only the values of K 101 , K 701 , and K 702 .

[實施例4] [Example 4]

圖5係顯示第4實施形態之基準電壓電路的電路圖。 Fig. 5 is a circuit diagram showing a reference voltage circuit of the fourth embodiment.

第4實施形態之基準電壓電路係具備有:PMOS電晶 體101~104、701~703、NMOS電晶體201~206、輸出端子401、電源端子501、接地端子502、及電阻601、602。PMOS電晶體701、702的臨限值電壓的絕對值| Vtpl |係低於PMOS電晶體101、102的臨限值電壓的絕對值| Vtph |。PMOS電晶體101、102、701、702的K值係分別設為K101、K102、K701、K702。電阻601、602的電阻值係分別設為R601、R602。PMOS電晶體103、104係構成電流鏡電路,NMOS電晶體201與NMOS電晶體202、203、204係構成電流鏡電路。 The reference voltage circuit of the fourth embodiment includes PMOS transistors 101 to 104, 701 to 703, NMOS transistors 201 to 206, an output terminal 401, a power supply terminal 501, a ground terminal 502, and resistors 601 and 602. The absolute value of the threshold voltage | V tpl | of the PMOS transistors 701, 702 is lower than the absolute value of the threshold voltage | V tph | of the PMOS transistors 101, 102. The K values of the PMOS transistors 101 , 102 , 701 , and 702 are K101 , K102 , K701 , and K702, respectively . The resistance values of the resistors 601 and 602 are set to R 601 and R 602 , respectively. The PMOS transistors 103 and 104 constitute a current mirror circuit, and the NMOS transistor 201 and the NMOS transistors 202, 203, and 204 constitute a current mirror circuit.

接著,說明第4實施形態之基準電壓電路的連接。NMOS電晶體201~206的源極端子係被連接於接地端子502。NMOS電晶體202~204的閘極端子係被連接於NMOS電晶體201的閘極端子及汲極端子與PMOS電晶體701的汲極端子。PMOS電晶體101、701的閘極端子係被連接於PMOS電晶體101的汲極端子與NMOS電晶體202的汲極端子,源極端子係被連接於電源端子501。電阻601的一端係被連接於PMOS電晶體102的閘極端子與PMOS電晶體703的源極端子,另一端係被連接於PMOS電晶體104的汲極端子與PMOS電晶體702的閘極端子。PMOS電晶體102的汲極端子係被連接於NMOS電晶體203的汲極端子與PMOS電晶體703的閘極端子,源極端子係被連接於電源端子501。PMOS電晶體703的汲極端子係被連接於接地端子502。PMOS電晶體702的汲極端子係被連接於NMOS電晶體204的汲極端子與NMOS電 晶體205、206的閘極端子,源極端子係被連接於電源端子501。PMOS電晶體103、104的閘極端子係被連接於PMOS電晶體103的汲極端子與NMOS電晶體205的汲極端子,源極端子係被連接於電源端子501。電阻602的一端係被連接於NMOS電晶體206的汲極端子與輸出端子401,另一端係被連接於電源端子501。 Next, the connection of the reference voltage circuit of the fourth embodiment will be described. The source terminals of the NMOS transistors 201 to 206 are connected to the ground terminal 502. The gate terminals of the NMOS transistors 202-204 are connected to the gate terminal and the NMOS terminal 201 of the NMOS transistor 201 and the NMOS terminal of the PMOS transistor 701. The gate terminals of the PMOS transistors 101 and 701 are connected to the NMOS terminal of the PMOS transistor 101 and the NMOS terminal of the NMOS transistor 202, and the source terminal is connected to the power supply terminal 501. One end of the resistor 601 is connected to the gate terminal of the PMOS transistor 102 and the source terminal of the PMOS transistor 703, and the other end is connected to the gate terminal of the PMOS transistor 104 and the gate terminal of the PMOS transistor 702. The 汲 terminal of the PMOS transistor 102 is connected to the NMOS terminal of the NMOS transistor 203 and the gate terminal of the PMOS transistor 703, and the source terminal is connected to the power supply terminal 501. The 汲 terminal of the PMOS transistor 703 is connected to the ground terminal 502. The 汲 terminal of the PMOS transistor 702 is connected to the NMOS terminal of the NMOS transistor 204 and the NMOS The gate terminals of the crystals 205, 206 are connected to the power supply terminal 501. The gate terminals of the PMOS transistors 103 and 104 are connected to the NMOS terminal of the PMOS transistor 103 and the NMOS terminal of the NMOS transistor 205, and the source terminal is connected to the power supply terminal 501. One end of the resistor 602 is connected to the NMOS terminal of the NMOS transistor 206 and the output terminal 401, and the other end is connected to the power supply terminal 501.

接著,說明第4實施形態之基準電壓電路的動作。第4實施形態之基準電壓電路係成為使第2實施形態之PMOS電晶體與NMOS電晶體的作用反轉者。流至NMOS電晶體201~204的電流係第3實施形態中以前述Vtph、Vtpl、K101、K701所決定的一定電流(IB)。若將在PMOS電晶體102、702流通電流IB所需電壓VGS分別設為VGS102B、VGS702B時,出現在電阻601的兩端的電壓Vref5係成為Vref5=| VGS102B |-| VGS702B |,其值係以IB、Vtpl、Vtph、K102、K702決定。由於電流IB係以Vtph、Vtpl、K101、K701決定,因此藉由取出電壓Vref5,可得不會發生因以Vtph、Vtpl、K101、K102、K701、K702的值所決定之電阻所致之製程變動所致的偏差的基準電壓。此外,藉由調整K102、K702的值,可以相對於IB、VGS102B、VGS702B的溫度特性,電壓Vref5的溫度特性成為平緩的方式進行補正。 Next, the operation of the reference voltage circuit of the fourth embodiment will be described. The reference voltage circuit of the fourth embodiment reverses the action of the PMOS transistor and the NMOS transistor of the second embodiment. The current flowing to the NMOS transistors 201 to 204 is a constant current (I B ) determined by the above-described V tph , V tpl , K 101 , and K 701 in the third embodiment. When the voltage V GS required to flow the current I B in the PMOS transistors 102 and 702 is V GS102B and V GS702B , respectively, the voltage V ref5 appearing at both ends of the resistor 601 becomes V ref5 =| V GS102B |-| V GS702B |, the value is determined by I B , V tpl , V tph , K 102 , K 702 . Since the current I B is determined by V tph , V tpl , K 101 , and K 701 , by taking out the voltage V ref5 , it is possible to prevent V tph , V tpl , K 101 , K 102 , K 701 , K from occurring. The reference voltage of the deviation due to the process variation caused by the resistance determined by the value of 702 . Further, by adjusting the values of K 102 and K 702 , it is possible to correct the temperature characteristics of the voltages V ref5 with respect to the temperature characteristics of I B , V GS 102B , and V GS 702 B .

若所有電晶體在飽和領域進行動作,電壓Vref5係以下式表示。 If all of the transistors operate in the saturation region , the voltage V ref5 is expressed by the following equation.

其中,K101>K701Among them, K 101 >K 701 .

由(9)式可知,電壓Vref5的值係以Vtph、Vtpl、K101、K102、K701、K702所決定的基準電壓。此外,在補正溫度特性時,係僅調整K101、K102、K701、K702的值即可。 As can be seen from equation (9), the value of the voltage V ref5 is a reference voltage determined by V tph , V tpl , K 101 , K 102 , K 701 , and K 702 . Further, when the temperature characteristics are corrected, only the values of K 101 , K 102 , K 701 , and K 702 may be adjusted.

在PMOS電晶體104與NMOS電晶體206係流通相同的電流,因此輸出端子401的基準電壓Vref係成為Vref=VDD-Vref5×(R602/R601),可輸出將電壓Vref5形成R602/R601倍後的電源端子電壓基準的任意的基準電壓值。一般而言,同一晶片內的電阻比的偏離係可忽視般可減小,因此可得不會發生因電阻所致之製程變動的影響的任意的基準電壓。 Since the PMOS transistor 104 and the NMOS transistor 206 are connected to the same current, the reference voltage V ref of the output terminal 401 is V ref = VDD - V ref5 × (R 602 / R 601 ), and the output voltage V ref5 can be output. R 602 /R 601 times the power supply terminal voltage reference for any reference voltage value. In general, the deviation of the resistance ratio in the same wafer can be neglected, so that an arbitrary reference voltage which does not cause an influence of process variation due to resistance can be obtained.

第4實施形態之基準電壓電路係形成以電源端子電壓(VDD)為基準的基準電壓的電路,若使用N型基板時,基準電壓值不受背閘極偏壓效果的影響的電路。在第3實施形態之電路中,由於對圖4的PMOS電晶體702施加背閘極偏壓,因此在決定基準電壓值的要因加入PMOS電晶體702的背閘極偏壓效果,因製程變動所致之偏差要因會增加。但是,在第4實施形態中,即使在使用N型基板的情形下,亦不會對決定基準電壓值的電晶體施加背閘極偏壓,因此基準電壓值僅以Vtpl、Vtph、K101、K102、K701 、K702的值決定。因此,若採取本發明之第4實施形態之構成,即使在使用N型基板的情形下,亦使因製程變動所致之偏差要因較少,而且可減小基準電壓值或其溫度特性的補正值。 The reference voltage circuit of the fourth embodiment is a circuit that forms a reference voltage based on the power supply terminal voltage (VDD). When an N-type substrate is used, the reference voltage value is not affected by the back gate bias effect. In the circuit of the third embodiment, since the back gate bias is applied to the PMOS transistor 702 of FIG. 4, the effect of determining the reference voltage value is added to the back gate bias effect of the PMOS transistor 702 due to process variation. The cause of the deviation will increase. However, in the fourth embodiment, even when an N-type substrate is used, the back gate bias is not applied to the transistor that determines the reference voltage value, so the reference voltage value is only V tpl , V tph , K . The values of 101 , K 102 , K 701 , and K 702 are determined. Therefore, according to the configuration of the fourth embodiment of the present invention, even when the N-type substrate is used, the variation due to the process variation is less, and the correction of the reference voltage value or its temperature characteristic can be reduced. value.

在此,PMOS電晶體101~104係使用具有相同臨限值電壓Vtph的電晶體,但是若以PMOS電晶體103、104構成電流鏡電路,即使臨限值與PMOS電晶體101、102不同亦可。此外,PMOS電晶體701~703係使用具有相同臨限值電壓Vtpl的電晶體,但是PMOS電晶體703亦可使用按照動作電源電壓而具有與其他不同之適當臨限值電壓的電晶體。 Here, the PMOS transistors 101 to 104 use transistors having the same threshold voltage V tph , but if the PMOS transistors 103 and 104 constitute a current mirror circuit, even if the threshold value is different from the PMOS transistors 101 and 102 can. Further, the PMOS transistors 701 to 703 use a transistor having the same threshold voltage V tpl , but the PMOS transistor 703 may also use a transistor having an appropriate threshold voltage different from that according to the operating power supply voltage.

其中,係以電流鏡電路的K值設為相等,藉由調整各電晶體的K值來補正基準電壓的方式為例,但是亦可藉由改變電流鏡電路的鏡像對的K值來調節各電晶體的汲極端子電流比,來補正基準電壓值。 The method of correcting the reference voltage by adjusting the K value of each transistor is taken as an example, but the K value of the mirror image pair of the current mirror circuit is adjusted. The 汲 terminal current ratio of the transistor is used to correct the reference voltage value.

藉由以上,可得不會發生電阻之製程變動所致之偏差,在補正溫度特性時,藉由僅調整K101、K102、K701、K702的值,即可輕易進行補正的基準電壓。 With the above, can be obtained due to variation of the resistance of the process will not be changed, while correcting temperature characteristics, by adjusting only the K 101, K 102, K 701 , K 702 a value can be easily corrected reference voltage .

如以上說明所示,本發明之基準電壓電路若形成為以下構成即可:具備有:第1MOS電晶體;第2MOS電晶體,其係閘極端子被連接於第1MOS電晶體的閘極端子,且具有高於第1MOS電晶體的臨限值的絕對值與K值的臨限值的絕對值與K值;電流鏡電路,其係流通根據第1MOS電晶體與第2MOS電晶體的臨限值的絕對值的差的 電流;第3MOS電晶體,其係流通電流鏡電路的電流;及第4MOS電晶體,其係具有高於第3MOS電晶體的臨限值的絕對值與K值的臨限值的絕對值與K值,且流通電流鏡電路的電流,將根據第3MOS電晶體與第4MOS電晶體的臨限值的絕對值與K值的差的定電壓輸出作為基準電壓。 As described above, the reference voltage circuit of the present invention may be configured to include a first MOS transistor, and a second MOS transistor whose gate terminal is connected to the gate terminal of the first MOS transistor. And having an absolute value and a K value that are higher than a threshold value of a threshold value of the first MOS transistor and a K value; and a current mirror circuit that is based on a threshold value of the first MOS transistor and the second MOS transistor The absolute value of the difference a current; a third MOS transistor, which is a current flowing through the current mirror circuit; and a fourth MOS transistor having an absolute value of a threshold value higher than a threshold value of the third MOS transistor and a K value, and K The current flowing through the current mirror circuit is a constant voltage output based on the difference between the absolute value of the third MOS transistor and the fourth MOS transistor and the K value as the reference voltage.

因此,實施例所示之基準電壓電路的發生定電壓的電路或將該定電壓輸出作為基準電壓的電路為一例,並非為限定於該等電路者。 Therefore, the circuit for generating a constant voltage of the reference voltage circuit shown in the embodiment or the circuit for outputting the constant voltage as the reference voltage is not limited to the circuits.

101~106‧‧‧PMOS電晶體 101~106‧‧‧ PMOS transistor

201~206‧‧‧NMOS電晶體 201~206‧‧‧ NMOS transistor

301~303‧‧‧臨限值低的NMOS電晶體 301~303‧‧‧ NMOS transistor with low threshold

401‧‧‧輸出端子 401‧‧‧Output terminal

501‧‧‧電源端子 501‧‧‧Power terminal

502‧‧‧接地端子 502‧‧‧ Grounding terminal

601、602‧‧‧電阻 601, 602‧‧‧ resistance

701~703‧‧‧臨限值的絕對值低的PMOS電晶體 701~703‧‧‧ PMOS transistor with low absolute value

圖1係顯示第1實施形態之基準電壓電路的電路圖。 Fig. 1 is a circuit diagram showing a reference voltage circuit of the first embodiment.

圖2係顯示臨限值及K值不同的2個NMOS電晶體的閘極源極間電壓對汲極端子電流的曲線的圖表。 2 is a graph showing a curve of a gate-to-source voltage versus a terminal current of two NMOS transistors having different thresholds and K values.

圖3係顯示第2實施形態之基準電壓電路的電路圖。 Fig. 3 is a circuit diagram showing a reference voltage circuit of the second embodiment.

圖4係顯示第3實施形態之基準電壓電路的電路圖。 Fig. 4 is a circuit diagram showing a reference voltage circuit of the third embodiment.

圖5係顯示第4實施形態之基準電壓電路的電路圖。 Fig. 5 is a circuit diagram showing a reference voltage circuit of the fourth embodiment.

圖6係顯示習知之基準電壓電路的電路圖。 Figure 6 is a circuit diagram showing a conventional reference voltage circuit.

101、102‧‧‧PMOS電晶體 101, 102‧‧‧ PMOS transistor

201‧‧‧NMOS電晶體 201‧‧‧ NMOS transistor

301、302‧‧‧臨限值低的NMOS電晶體 301, 302‧‧‧ NMOS transistors with low threshold

401‧‧‧輸出端子 401‧‧‧Output terminal

501‧‧‧電源端子 501‧‧‧Power terminal

502‧‧‧接地端子 502‧‧‧ Grounding terminal

Claims (3)

一種基準電壓電路,其特徵為具備有:第1MOS電晶體,其係源極端子被連接於第1電源端子;第2MOS電晶體,其係源極端子被連接於第1電源端子,閘極端子被連接於前述第1MOS電晶體的閘極端子,且具有高於前述第1MOS電晶體的臨限值的絕對值與K值的臨限值的絕對值與K值;電流鏡電路,其係流通根據前述第1MOS電晶體與前述第2MOS電晶體的臨限值的絕對值的差的電流;第3MOS電晶體,其係流通前述電流鏡電路的電流;及第4MOS電晶體,其係具有高於前述第3MOS電晶體的臨限值的絕對值與K值的臨限值的絕對值與K值,且流通前述電流鏡電路的電流,將根據前述第3MOS電晶體與前述第4MOS電晶體的臨限值的絕對值與K值的定電壓輸出作為基準電壓。 A reference voltage circuit comprising: a first MOS transistor having a source terminal connected to a first power supply terminal; and a second MOS transistor having a source terminal connected to a first power supply terminal and a gate terminal And being connected to the gate terminal of the first MOS transistor, and having an absolute value and a K value which are higher than a threshold value of a threshold value and a K value of the threshold value of the first MOS transistor; and a current mirror circuit a current according to a difference between an absolute value of a threshold value of the first MOS transistor and the second MOS transistor; a third MOS transistor that is a current that flows through the current mirror circuit; and a fourth MOS transistor that has a higher value The absolute value of the threshold value of the third MOS transistor and the absolute value of the threshold value of the K value and the K value, and the current flowing through the current mirror circuit is based on the third MOS transistor and the fourth MOS transistor. The absolute value of the limit value and the constant voltage output of the K value are used as the reference voltage. 如申請專利範圍第1項之基準電壓電路,其中,前述電流鏡電路係具備有:第5MOS電晶體,其係汲極端子及閘極端子被連接於前述第1MOS電晶體的汲極端子;第6MOS電晶體,其係閘極端子被連接於前述第5MOS電晶體的閘極端子,汲極端子被連接於前述第2MOS電晶體的閘極端子與汲極端子; 第7MOS電晶體,其係閘極端子被連接於前述第5MOS電晶體的閘極端子,汲極端子被連接於前述第3MOS電晶體的汲極端子;第8MOS電晶體,其係閘極端子被連接於前述第5MOS電晶體的閘極端子,汲極端子被連接於前述第4MOS電晶體的汲極端子;及電阻,其係其中一方端子被連接於前述第3MOS電晶體的閘極端子,另一方端子被連接於前述第4MOS電晶體的閘極端子,將根據前述電阻的兩端的電壓的定電壓輸出作為基準電壓。 The reference voltage circuit according to claim 1, wherein the current mirror circuit includes: a fifth MOS transistor, wherein the 汲 terminal and the gate terminal are connected to the 汲 terminal of the first MOS transistor; a 6MOS transistor having a gate terminal connected to a gate terminal of the fifth MOS transistor, and a gate terminal connected to a gate terminal and a gate terminal of the second MOS transistor; In the seventh MOS transistor, the gate terminal is connected to the gate terminal of the fifth MOS transistor, the 汲 terminal is connected to the 汲 terminal of the third MOS transistor; and the eighth MOS transistor is connected to the gate terminal. a gate terminal connected to the fifth MOS transistor, a 汲 terminal connected to the 汲 terminal of the fourth MOS transistor; and a resistor, wherein one of the terminals is connected to the gate terminal of the third MOS transistor, and One terminal is connected to the gate terminal of the fourth MOS transistor, and a constant voltage output based on the voltage across the resistor is used as a reference voltage. 如申請專利範圍第1項之基準電壓電路,其中,前述電流鏡電路係具備有:第5MOS電晶體,其係汲極端子及閘極端子被連接於前述第1MOS電晶體的汲極端子;及第6MOS電晶體,其係閘極端子被連接於前述第5MOS電晶體的閘極端子,汲極端子被連接於前述第3MOS電晶體的閘極端子與汲極端子,將前述第3MOS電晶體形成為使閘極端子連接於前述第2MOS電晶體的閘極端子,且使源極端子連接於前述第2MOS電晶體的汲極端子的構成,使前述第4MOS電晶體與前述第2MOS電晶體為共通,藉此由前述第3MOS電晶體的源極端子與前述第2MOS電晶體的汲極端子的連接點輸出前述基準電壓。 The reference voltage circuit of claim 1, wherein the current mirror circuit includes: a fifth MOS transistor, wherein the 汲 terminal and the gate terminal are connected to the 汲 terminal of the first MOS transistor; In the sixth MOS transistor, the gate terminal is connected to the gate terminal of the fifth MOS transistor, and the gate terminal is connected to the gate terminal and the gate terminal of the third MOS transistor, and the third MOS transistor is formed. In order to connect the gate terminal to the gate terminal of the second MOS transistor and to connect the source terminal to the gate terminal of the second MOS transistor, the fourth MOS transistor and the second MOS transistor are common to each other. Thereby, the reference voltage is output from a connection point of the source terminal of the third MOS transistor and the gate terminal of the second MOS transistor.
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US20130076331A1 (en) 2013-03-28
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JP5782346B2 (en) 2015-09-24
JP2013073375A (en) 2013-04-22
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US8791686B2 (en) 2014-07-29
TW201333660A (en) 2013-08-16

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