TWI539610B - Solar cells and solar modules - Google Patents

Description

Solar battery and solar battery module

The invention relates to a solar cell and a solar cell module.

Conventionally, a carrier generated inside a solar cell by light irradiation is separated into electrons and holes by a built-in electric field in a pn junction, and is taken out from each of the positive and negative electrodes. The current is the movement of the carrier, thus causing a loss of resistance in the path of movement of the carrier. For example, when a p-type wafer solar cell is used, electrons separated by the Pn junction are collected by an emitter layer (n layer) to a grid electrode, and further collected by the gate electrode. A bus electrode. In addition, holes are collected through the wafer to the back electrode. The resistance loss of the above-mentioned current collecting path affects the curve factor (Fill Factor, hereinafter referred to as FF) of the solar cell, and decreases as the resistance loss increases. Therefore, in order to achieve high efficiency of the solar cell, it is important to reduce the resistance loss in the solar cell.

In particular, in the solar cell in which the back surface is fully polarized, the resistance loss caused by the diffusion layer and the surface electrode becomes large. When the back electrode of the solar cell to be completed has an electrode similar to the surface electrode, the loss of the back electrode is further increased. Reduce the above resistance loss. Reducing the sheet resistance of the diffusion layer is effective for reducing the resistance loss of the diffusion layer, but this does not effectively utilize the short-wavelength light to cause a decrease in current, so that the sheet resistance is not lowered. In the case, the resistance loss is reduced by narrowing the design or countermeasure of the surface electrode such as the pitch between the gates. For example, Patent Document 1 discloses that the increase rate of the cross-sectional area of the gate is formed by increasing the front end of the gate toward the current lead-out portion (the connection portion with the auxiliary electrode). Further, Patent Document 2 discloses a technique of increasing the number of bus electrodes to shorten the gate or the like.

An electrode pattern in which the connection between the auxiliary electrode and the gate electrode disposed on both sides thereof is not aligned is proposed (Patent Documents 3 and 4). In Patent Documents 3 and 4, similar electrode patterns are provided, and the number of gates on both sides of the auxiliary electrode is different. Further, in Patent Document 3, the gate is not disposed at the end of the wafer (CELL). In Patent Document 4, the gate electrode is disposed at the end of the wafer.

[First technical literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. Hei 6-283736

Patent Document 2: Japanese Patent No. 4953562

[Patent Document 3] Japanese Patent Laid-Open Publication No. 2007-324264

[Patent Document 4] Japanese Patent Laid-Open Publication No. 2013-171885

However, the above-mentioned prior art does not pay special attention to the auxiliary electrode. It is considered that the auxiliary electrode is connected to the interconnecting wire (TAB wire, Tabbing wire) when assembling the module. That is to say, the considerations are as follows: the TAB line is composed of a conductor such as tin-plated copper, and the printed electrode which is generally used as an electrode of a solar cell, that is, an electrode obtained by sintering of a paste, has a higher electrical conductivity. High, thick, so collected The current to the auxiliary electrode mainly flows into the TAB line, and the current flowing into the auxiliary electrode is less.

However, the auxiliary electrode and the TAB line are not fully connected, and only a few connections are made, and the current collected to the auxiliary electrode flows into the auxiliary electrode before reaching the junction of the TAB line, so the resistance loss at this point is the main cause of the increase of FF.

When the number of auxiliary electrodes is increased as in Patent Document 2, the current flowing into the auxiliary electrode can be dispersed, and the resistance loss of the auxiliary electrode can be reduced. However, when the number of auxiliary electrodes is simply increased, the resistance loss due to the current passing through the auxiliary electrode before reaching the junction of the TAB line cannot be reduced. Further, in the configurations of Patent Documents 3 and 4, the auxiliary electrode is inevitably lengthened, and the electrode area of the auxiliary electrode is increased. As a result, the effective area for photoelectric conversion is reduced based on the shadow loss, and the photoelectric conversion efficiency is lowered.

In Patent Documents 1, 2, 3, and 4, it is not always possible to reduce the resistance loss and the shadow loss of the auxiliary electrode, and it is not possible to sufficiently reduce the resistance loss due to the shape of the electrode. Therefore, further improvement in the shape of the electrode is required.

In view of the above problems, it is an object of the present invention to provide a solar cell and a solar cell module which can achieve high efficiency by reducing the resistance loss of the auxiliary electrode of the solar cell by a simple method such as changing the shape of the electrode.

In order to achieve the above object, in the present invention, the collector electrode formed on the light-receiving surface of the substrate having the photoelectric conversion portion has an auxiliary electrode formed on the photoelectric conversion portion and is arranged in parallel on both sides of the auxiliary electrode. Multiple gates. The gate is located at one end of the auxiliary electrode and is connected to the auxiliary electrode in a straight line. On one side of the auxiliary electrode, on one side of the auxiliary electrode, there is a diagonal portion on one side of the auxiliary electrode. Connected to the auxiliary electrode The joint has an offset.

According to the present invention, it is possible to disperse the current flowing into the auxiliary electrode and reduce the resistance loss of the auxiliary electrode.

10‧‧‧Solar cell chip

10p‧‧‧chip end

10p’‧‧‧virtual chip end

11‧‧‧1st conductive semiconductor substrate

12‧‧‧2nd conductive semiconductor layer

13‧‧‧Anti-reflective film

14‧‧‧Glossy gate

15‧‧‧Photon auxiliary electrode

16‧‧‧1st conductive semiconductor layer

17‧‧‧Anti-reflective film

18‧‧‧ back gate

19‧‧‧Back auxiliary electrode

20‧‧‧TAB line (interconnector)

30‧‧‧ glass plate

40‧‧‧Back film

50‧‧‧ sealing resin

Fig. 1 is a schematic view showing a solar cell according to a first embodiment of the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A' of (a).

Fig. 2 is an enlarged view of an important part of an electrode pattern of the solar cell.

Fig. 3 is a schematic view for explaining the resistance loss of the diffusion layer from the cell end to the gate of the terminal of the solar cell of the first embodiment.

Fig. 4 is a schematic view showing the calculation of the resistance loss of the light-receiving surface auxiliary electrode in the electrode pattern of the solar cell of the first embodiment.

Fig. 5(a) is a schematic view for explaining the resistance loss of the diffusion layer from the wafer end to the gate of the solar cell of Comparative Example 1, and Fig. 5(b) is the electrode of the solar cell of Comparative Example 1. A pattern diagram for calculating the resistance loss of the auxiliary electrode in the pattern.

Fig. 6(a) is a schematic view showing the resistance loss of the diffusion layer from the wafer end to the gate of the solar cell of Comparative Example 2, and Fig. 6(b) is the electrode pattern of the solar cell of Comparative Example 2. A pattern diagram for calculating the resistance loss of the auxiliary electrode.

Fig. 7(a) is a top view showing the structure of the solar battery module of the second embodiment, and Fig. 7(b) is a cross-sectional view showing the structure of the solar battery module of the second embodiment.

Fig. 8 is a perspective view showing a part of a string of a solar battery module of Embodiment 2.

Fig. 9 is a top view showing a part of a string of solar battery modules of the second embodiment.

Fig. 10(a) is a top view of the solar cell chip in the light-receiving surface side of the third embodiment, and Fig. 10(b) is a top view seen from the back side.

Fig. 11(a) is a top view of a modification of the third embodiment as seen from the light receiving surface side of the solar cell wafer, and Fig. 11(b) is a top view seen from the back side.

Fig. 12 is a top view of a solar cell wafer of the fourth embodiment.

Figure 13 is a top view of a solar cell wafer of Embodiment 5.

Fig. 14 is a top view of a solar cell wafer of a comparative example.

Embodiments of the solar cell of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following description, and may be modified as appropriate without departing from the scope of the invention. In addition, in the drawings shown below, the scale of each member may be different from the actual one for easy understanding, and the drawings are also the same. In addition, in the plan view, there is a case where hatching is added to facilitate the viewing of the drawing.

Embodiment 1.

Fig. 1 is a schematic view showing a first embodiment of a solar cell according to the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A' of (a). Fig. 2 is an enlarged view of an important part of an electrode pattern of the solar cell. The pair of left and right light-receiving surface gates 14 located on both sides of the light-receiving surface auxiliary electrode 15 are located on a straight line at one end of the substrate at the end of the light-receiving surface auxiliary electrode 15, and the light-receiving surface is provided at one end. The connection portion of the gate electrode 14 and the light-receiving surface auxiliary electrode 15 is not located on a straight line, and the oblique portion 14b is formed so as to be offset by a distance k. The main body portion 14a is configured to be disposed in parallel with each other at a predetermined interval except for the connection portion.

In the solar cell wafer 10 of the first embodiment, the light-receiving surface 11A, which is the first main surface of the first-conductivity-type semiconductor substrate 11, has a concavo-convex structure having a texture 11T for reducing light reflection. The second conductive semiconductor layer 12 is formed on the uneven structure, and the second conductive semiconductor layer 12 is laminated to form the antireflection film 13. The light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15 which are the first collector electrodes on the light-receiving surface 11A side are formed at any position of the anti-reflection film 13, the light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15 and the second conductivity type. The semiconductor layer 12 contacts. In the back surface 11B which is the second main surface of the first-conductivity-type semiconductor substrate 11 facing the light-receiving surface 11A, the texture 11T is formed in the same manner as the light-receiving surface 11A, and the first-conductivity-type semiconductor layer 16 and the anti-reflection film 17 are sequentially formed. The back surface auxiliary electrode 19 which is the second collecting electrode is formed at any position of the anti-reflection film 17. Although not shown in the first drawing, the back surface gate 18 is arranged at a predetermined interval so as to be orthogonal to the back surface auxiliary electrode 19.

As shown in the enlarged view of the important portion of Fig. 2, the light-receiving surface grid 14 is configured such that the main body portion 14a is formed in parallel with each other in the direction orthogonal to the light-receiving surface auxiliary electrode 15, and the oblique portion 14b is formed. The angle between the distance m between the light-receiving auxiliary electrode 15 and the light-receiving surface auxiliary electrode 15 is α < 90 degrees.

For the first conductive type semiconductor substrate 11 which is a solar cell substrate of the present embodiment, for example, an n-type single crystal or a polycrystalline silicon substrate can be used. When the n-type ruthenium substrate is used, the second-conductivity-type semiconductor layer 12 is a p-type impurity diffusion layer, and the light-receiving surface 11A of the first-conductivity-type semiconductor substrate 11 is, for example, an impurity diffusion layer formed by boron diffusion. Further, the light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15 constituting the light-receiving surface electrode are formed by, for example, screen printing using a mixture of aluminum and silver. The anti-reflection film 13 covering the surface on the side of the light-receiving surface 11A is, for example, a tantalum nitride film (SiN _x ) to which hydrogen is added. Further, the first conductive semiconductor layer 16 on the back surface is an n-type impurity diffusion layer, and is, for example, an impurity diffusion layer that performs diffusion of phosphorus ions. The anti-reflection film 17 is, for example, SiN _x . The back surface gate 18 and the back surface auxiliary electrode 19 are formed, for example, of silver. In addition, the first-conductivity-type semiconductor substrate 11 is not limited to the n-type ruthenium substrate, and a p-type ruthenium substrate may be used. Similarly, phosphorus diffusion is performed on the second conductivity type semiconductor layer 12, and the first conductivity type semiconductor layer 16 is implemented on the first conductivity type semiconductor layer 16. Boron can be diffused. The light-receiving surface 11A or the back surface 11B of the first-conductivity-type semiconductor substrate 11 is preferably a concavo-convex structure in order to reduce the reflectance. However, the present invention is not limited to the concavo-convex structure. For example, any of a flat structure or a combination of unevenness and flatness may be used.

As shown in Fig. 1(a), in the electrode pattern of the light-receiving surface side electrode of the solar cell of the first embodiment, two light-receiving surface auxiliary electrodes 15 are formed, but the number of auxiliary electrodes is not limited. The light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15 are formed at an acute angle α at the oblique portion 14b which is a connection portion with the light-receiving surface auxiliary electrode 15. In the light-receiving surface side electrode pattern of the present embodiment, a pair of left and right light-receiving surface gates 14 are disposed on a straight line on one end side of the substrate, and one end of the substrate is provided on one end side of the substrate. In addition to the side, one of the light-receiving surface gates 14 on one side of the light-receiving surface auxiliary electrode 15 is inclined, so that the junctions of the light-receiving surface gates 14 on both sides are not located on the straight line, and the distance k is offset.

Fig. 3 is a schematic view showing a region where the current is collected by the light-receiving surface grid 14. Generally, the light-receiving surface gates 14 are arranged at equal intervals, and the light-receiving surface gates 14 are collected by the region Rg of the light-receiving surface gates 14 and the lower light-receiving surface gates 14 surrounded by the intermediate line. Current, this also applies to the gate at the end. When the electrode is disposed on the wafer end as in the electrode pattern of Patent Document 4, when the light-receiving surface grid 14 is provided at the wafer end, the resistance loss can be reduced. However, the wafer end 10 is moved to the position shown by the broken line 10p', which means that the region R ₀ at which the light-receiving surface electrode 14 of the original end can collect current disappears, and the shadow loss is relatively increased. In other words, the light-receiving surface gate 14 has the ability to collect current from the wafer end 10p. However, when the wafer end is located at the virtual wafer end 10p' indicated by the dashed line, the current collecting capability of the gate electrode 14 becomes excessively large, and the electrode area can be reduced by an appropriate electrode design, that is, the shadow loss can be reduced. Here, the wafer end refers to an end portion of a region where the photoelectric conversion portion is formed to have a generator, and is set to be at the same position as the substrate end. The shadow loss is a loss caused by the light-receiving area due to the electrode area, and it is preferable to reduce the shadow loss as much as possible. Therefore, in the actual solar cell system, as in Patent Document 4, the electrode is not disposed at the end of the wafer, and the electrode of the practical solar cell becomes the pattern of Patent Document 3.

On the other hand, as shown in FIG. 14, the light-receiving surface side electrode pattern of the conventional solar cell, which is generally used, is connected to the pair of right and left light-receiving surface gates 14 on both sides of the light-receiving surface auxiliary electrode 15. The light-receiving surface electrode pattern of the above-described FIG. 14 was used as Comparative Example 1, and the electrode pattern of Patent Document 3 was used as Comparative Example 2 for comparison.

The effectiveness of the electrode pattern of the solar cell of the present embodiment is shown in comparison with the electrode pattern shown in Fig. 14 of Comparative Example 1 and the electrode pattern of Patent Document 3 of Comparative Example 2.

Fig. 4 is a view showing the electrode pattern of the solar cell of the first embodiment A pattern diagram for calculating the resistance loss of the light-receiving auxiliary electrode 15. It is assumed that the current flowing into the light-receiving surface auxiliary electrode 15 by one light-receiving surface grid 14 is I, and the electric resistance of the light-receiving surface auxiliary electrode 15 between the oblique portion 14b of the light-receiving surface gate 14 and the oblique portion 14b is R. Further, in the electrode pattern of the solar cell of the first embodiment (Patent Document 3) and the first embodiment, the light-receiving surface auxiliary electrode 15 located between the light-receiving surface grids 14 is divided into a: 1-a (0). A single-sided light-receiving surface electrode 14 is connected at <a<1>. The collected current is taken out from the lowermost end of the light-receiving surface auxiliary electrode 15 which is one end of the wafer in the drawing. Therefore, it is assumed that the resistance loss of the light-receiving surface auxiliary electrode 15 due to the current collected by the lowermost light-receiving surface electrode 14 does not exist. Fig. 5 (a), (b) and Fig. 6 (a) and (b) show the light-receiving surface grid 14 in the electrode pattern of the conventional electrode pattern (Comparative Example 1) and Patent Document 3 (Comparative Example 2), respectively. A pattern diagram of the region where the current is collected and a pattern diagram for calculating the resistance loss of the auxiliary electrode. L is the width of the wafer, and b is the length of the light-receiving surface electrode 14 from the light-receiving surface auxiliary electrode 15. The current flowing into the light-receiving surface auxiliary electrode 15 by the one light-receiving surface grid 14 is I, and the electric resistance of the light-receiving surface auxiliary electrode 15 between the inclined portion 14b of the light-receiving surface electrode 14 and the oblique portion 14b is R. Further, in Comparative Example 2, in the electrode pattern of the solar cell of the present embodiment, the auxiliary electrode located between the light-receiving surface grids 14 is divided into a: 1-a (0 < a < 1). The light receiving surface gate 14 on the side. The collected current is taken out from the lowermost end of the light-receiving surface auxiliary electrode 15 in the figure. Therefore, it is assumed that the resistance loss of the light-receiving surface auxiliary electrode 15 due to the current collected by the lowermost light-receiving surface electrode 14 does not exist.

Here, the resistance losses of the auxiliary electrodes of the electrode patterns of Comparative Example 1 and Comparative Example 2 of the present embodiment are as follows.

[Numerical 1] Pattern of Comparative Example 1: (2I) ² R+(4I) ² R=20I ² R Pattern of Comparative Example 2: I ² aR+4I ² (1-a)R+9I ² aR+16I ² ( 1-a) R+25I ² aR=20I ² R+15I ² Ar Electrode pattern of the embodiment: I ² aR+4I ² (1-a)R+9I ² aR+16I ² (1-a)R=20I ² R-10I ² aR..(1)

From this, it is understood that the electrode pattern of the solar cell of the first embodiment has the smallest resistance loss of the auxiliary electrode, and the solar cell of the first embodiment has the superiority. In the pattern of Comparative Example 2 and the first embodiment, the gate on one side was shifted and connected to the auxiliary electrode, but the resistance loss of the auxiliary electrode was not different. This is because the electrode pattern of Comparative Example 2 necessarily lengthens the auxiliary electrode and increases the resistance loss. The extension of the auxiliary electrode also results in an increase in the cost of the electrode material.

In the electrode pattern of the first embodiment, as shown in FIG. 6(b), when the connection position of the light-receiving surface auxiliary electrode 15 is shifted to the lowermost light-receiving surface grid 14, the resistance loss due to the auxiliary electrode and the comparative example 2 is the same, but not good.

The difference in resistance loss also occurs from the diffusion layer from the wafer end to the terminal gate. As shown in FIGS. 5(a) and 6(a), the electrode pattern of Comparative Example 1 and the electrode pattern of Comparative Example 2 were placed on the same size wafer. In the electrode pattern of the solar cell of the first embodiment, only the connection position of the gate electrode to the auxiliary electrode is different from the normal electrode pattern, and therefore it is considered to be equal to the electrode pattern of the solar cell of Comparative Example 1.

When the gate interval is S, as shown in FIG. 3, the distance from the wafer end 10p to the uppermost light receiving surface grid 14 and the wafer end to the lowermost light receiving surface grid 14 is S/2, respectively. The distance from the wafer end to the uppermost light-receiving surface gate 14 is set to r, and the light-receiving surface grating from the wafer end to the end is attempted for current. The pole 14 is calculated by the resistance loss of the diffusion layer when passing through the diffusion layer.

When the distance from the wafer end to the uppermost light receiving surface grid 14 is r, the distance from the lowermost light receiving surface gate 14 to the wafer end becomes Sr. When the current density is J and the sheet resistance of the diffusion layer is ρ _s , the resistance loss P _loss1 when the current passes through the diffusion layer from the wafer end to the uppermost light-receiving surface gate 14 becomes the following [number 2].

Similarly, the resistance loss P _loss2 when the current passes through the diffusion layer from the wafer end to the lowermost light-receiving surface gate becomes the following [3].

The total is the following [number 4].

The resistance loss becomes a minimum value (1/6) J ² bρ _s S ³ at r = (1/2) S.

Further, in the electrode pattern of Comparative Example 2 (Patent Document 3), the distance from the wafer end to the gate of the uppermost stage is as shown in Fig. 6(b). Further, the misalignment of the left and right auxiliary electrodes is one half of the gate interval described as the optimum value in Comparative Example 2. When the offset between the left and right gates is one half of the optimum gate interval described in Comparative Example 2, the resistance loss when the current flows into the diffusion layer from the wafer end to the gate becomes the following [5].

The resistance loss becomes a minimum value (7/24) J ² bρ _s S ³ at r = (1/4) S.

The comparison between the electric resistance loss obtained by the above formula (4) and the electric resistance loss obtained in (5) shows that the electrode pattern of the normal electrode pattern and the electrode pattern of the present embodiment is caused by the diffusion layer from the wafer end to the end gate. The loss was smaller than that of Comparative Example 2, that is, the electrode pattern of the present embodiment was better than that of Comparative Example 2.

As described above, by using the electrode pattern of the solar cell of the present embodiment, it is possible to reduce the resistance loss of the auxiliary electrode and improve the FF. There are high efficiency solar cells.

Further, from the calculation of the resistance loss of the auxiliary electrode, it can be seen that the closer the a is to 1, the more the resistance loss of the auxiliary electrode can be reduced. However, the electrodes of the solar cell are formed by screen printing a metal paste, so that the connection angle of the gate electrode and the auxiliary electrode is too small, and it is possible that the gate cannot be connected based on the spread of the printing.

The thickness of the gate is about 10, the penetration of the printing is about 20% of the width of the mask, and the maximum gate spacing is only about 3 mm. Therefore, the inclined portion 14b of the light-receiving surface gate 14 of FIG. 2 is along As long as the distance in the direction of the gate body portion 14a is 500 μm, the gate electrode and the auxiliary electrode can be connected to a desired place as designed by screen printing. When the gate interval is set to 3 mm and the distance m is set to 500 um, tan α = 0.5 / 3 = 0.16, and the minimum value of α is about 9 degrees. Further, in the present embodiment, since the light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15 are not vertically connected, α is a value in the range of 9° ≦ α < 90°. When the α is too small, the material cost of the gate-lengthening electrode increases, so it is actually preferable to design α as much as possible.

Embodiment 2.

Next, a solar cell module 100 according to the second embodiment will be described, and the solar cell wafer 10 described in the first embodiment will be used. Fig. 7(a) is a view showing a configuration example of the solar battery module 100 according to the second embodiment, which is seen from the side of the light receiving surface of the sunlight. Fig. 7(b) is a cross-sectional view showing the structure of the solar cell module 100 of the second embodiment, which is a cross section taken along the line A-B of Fig. 7(a). Fig. 8 is a perspective view showing the end surface of the TAB wire 20 constituting the interconnector on the light-receiving surface auxiliary electrode 15 of the solar cell wafer 10 of the first embodiment, and the back surface auxiliary electrode adjacent to the back surface of the wafer. (not shown) The other end of the TAB wire 20 is welded, and the string S is formed by being connected in series, and the solar cell module 100 is constructed by sealing the string with a resin. As described in the first embodiment, the current flowing into the light-receiving surface auxiliary electrode 15 is dispersed by bending the oblique portion 14b of the curved surface of the light-receiving surface electrode 14 to reduce the resistance loss of the auxiliary electrode. In this manner, the TAB line 20 can be connected without expanding the width of the light-receiving surface auxiliary electrode 15, and the shadow loss can be reduced.

In the solar cell module 100, a plurality of solar cell wafers 10 are connected to each other by a TAB wire 20, and a glass plate 30 which is a light-transmitting substrate as a light-receiving surface side protective member and a back film which is a back side protective member (back) Between the films 40, they are sealed by the sealing resin 50. The solar cell wafer 10 is provided with first and second collector electrodes on the surface on the light-receiving surface 11A side and the surface on the back surface 11B side. The TAB wires 20 are connected in series between the electrodes of the adjacent solar cell wafers 10, and are sealed in a state in which the strings S are formed as shown in the oblique view of Fig. 8 and the upper view of Fig. 9. Here, only three wafer points are shown in Fig. 8 based on the relationship between the paper sheets, and only two wafer points are shown in Fig. 9. The first collector electrode on the light-receiving surface 11A side is composed of the light-receiving surface grid 14 and the light-receiving surface grid 15, and the back surface gate 18 and the second collector electrode are also formed on the back surface 10B of the solar cell wafer 10 Back auxiliary electrode 19. The TAB line 20 is electrically connected to the light-receiving surface auxiliary electrode 15 and the back surface auxiliary electrode 19 adjacent to the wafer. Further, reference numeral 21 is a lead for external extraction.

Further, as shown in Figs. 8 and 9, the TAB line 20 extends in the direction indicated by the arrow D1 from the side where the junction of the light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15 is on the straight line. Further, in Fig. 9, in order to make the light-receiving surface auxiliary electrode 15 visible, the TAB line 20 is omitted from the wafer on the right side.

Further, Fig. 7(a) is a view showing a solar cell module 100 in which twelve solar cell wafers 10 are connected in series, but the number and arrangement thereof may be arbitrarily changed, or may be a combination of parallel connections.

As the glass plate 30, a material such as calcium soda glass can be used. For solar cell modules used outside the house, heat-strengthened or chemically strengthened glass plates can be used for the light-receiving side protective material. The size of the glass plate 30 can be variously changed depending on the number of the solar cell wafer 10, and the typical thickness is 0.5 to 3 mm. The back film 40 is a film having a low moisture permeability or a glass plate similar to the front side in order to prevent deterioration of the solar cell wafer 10 by intrusion of moisture or the like. In order to reflect the light passing through the gap between the solar cell wafer 10 and the solar cell wafer 10 to the solar cell wafer 10 side, the back film 40 may use a white or metallic light reflective material. As the sealing resin 50, a light-transmitting EVA, a silicone resin, or the like can be used. As the TAB wire 20 constituting the interconnector, for example, a copper wire covered with solder or the like can be used.

In the calculation of the electric resistance loss of the light-receiving surface auxiliary electrode of the first embodiment, it is necessary to observe the direction in which the wafers using the electrode patterns of the present embodiment are connected to each other, that is, as shown in Figs. The current is taken out in the direction indicated by the arrow D1 by the side where the connection between the left and right light-receiving surface gates 14 and the light-receiving surface auxiliary electrode 15 is on the straight line. When the mutually connected directions of the wafers are opposite to each other, the current from the first light-receiving surface grid 14 cannot be dispersed and flows into the light-receiving surface auxiliary electrode 15 at a time, resulting in a reduction in the effect of reducing the resistance loss.

Moreover, when the auxiliary electrodes of the adjacent solar cell wafers are connected by the interconnector (TAB line 20), the current between the solar cell wafers flows into both the auxiliary electrode and the TAB line, but the resistance of the auxiliary electrode and the TAB line are The composite value of the resistance is set to R, and the consideration shown in the first embodiment can be directly applied.

Embodiment 3.

Further, in the solar cell wafer of the first embodiment, only one of the light-receiving surface gates 14 is inclined to the surface electrode of the collector electrode on the light-receiving surface side, so that the junctions of the light-receiving surface gates 15 on both sides are not connected. Although it is a structure which is formed by the offset on the straight line, it is also applicable to the solar cell which has the electrode pattern of the back surface gate 18 and the back surface auxiliary electrode 19 like a back surface and surface electrode. Fig. 10(a) is a top view of the solar cell wafer 10 of the third embodiment as seen from the light receiving surface side, and Fig. 10(b) is a top view of the solar cell wafer 10 of the third embodiment as seen from the back side. . In Fig. 10 (a) and (b), the positions of A and A' are respectively set to correspond. In the present embodiment, the electrode pattern of the solar cell wafer 10 of the third embodiment is not only the surface electrode but also the pair of left and right back gates 18 on both sides of the back surface auxiliary electrode 19 for the back surface electrode of the solar cell. It is disposed on a straight line, but one side of the back side gate 18 of one side is inclined so that the joints of the back side gates 18 on both sides are not located in a straight line, and are formed by offsetting a certain distance. The other portions such as the collector electrode on the light-receiving surface side are the same as those of the solar cell wafer of the first embodiment.

According to this configuration, the resistance loss of the solar cell can be further reduced. As described in the second embodiment, in the present embodiment, the TAB line 20 as the interconnector on the light-receiving surface side is located on the side of the line connecting the light-receiving surface grid 14 and the light-receiving surface auxiliary electrode 15, toward the arrow D1. The direction shown extends. Further, on the back side, the TAB line 20 also extends in the direction indicated by the arrow D1 from the side where the connection of the back surface gate 18 and the back surface auxiliary electrode 19 is on the straight line.

Further, the shape of the gate on the take-out side of the TAB line is determined, and the TAB line of the back surface electrode is taken out from the opposite side of the TAB line of the surface electrode by 180 degrees. The electrode arrangement in the case of the solar battery module of the embodiment is as shown in Fig. 10 (a) and (b), and the deformation thereof can be reversed left and right, as shown in Fig. 11 (a) and (b), for example.

Embodiment 4.

Fig. 12 shows a solar cell wafer 10 of the fourth embodiment. In the first embodiment shown in FIG. 1, the two light-receiving surface auxiliary electrodes 15 are each inclined to one side of the right-side light-receiving surface grid 14 so that the junctions of the light-receiving surface gates 14 on both sides are not in a straight line, and are offset. In the fourth embodiment, the light-receiving surface auxiliary electrode 15 on the right side of the fourth embodiment is inclined by the light-receiving surface electrode 14 on the right side, and the light-receiving surface auxiliary electrode 15 on the left side is inclined by the light-receiving surface electrode 14 on the left side.

According to the solar cell wafer of the first embodiment, similarly to the solar cell wafer of the first embodiment, the current flowing into the auxiliary electrode can be dispersed, and the resistance loss of the auxiliary electrode can be reduced.

Embodiment 5.

Fig. 13 shows a solar cell wafer 10 of the fifth embodiment. In the fifth embodiment, the light-receiving surface auxiliary electrode 15 on the right side slantes the light-receiving surface grid 14 on the left side, and the light-receiving surface auxiliary electrode 15 on the left side slantes the light-receiving surface grid 14 on the right side.

According to the solar cell wafer of the first embodiment, similarly to the solar cell wafer of the first embodiment, the current flowing into the auxiliary electrode can be dispersed, and the resistance loss of the auxiliary electrode can be reduced.

As described above, among the gates connected to the left and right of the auxiliary electrode, only one of the gates is inclined from one position, and only the connection portion with the auxiliary electrode is not located on the straight line, and the offset is determined in advance. The distance k, so, is not affected by the combination of left and right. For example, when N auxiliary electrodes are applied, for N Each of the auxiliary electrodes may be connected to the auxiliary electrode by obliquely connecting any of the left and right gates.

In each of the embodiments, the collector electrode on the back side is described as being composed of the back surface auxiliary electrode and the back surface electrode. However, the present invention is not limited to the above configuration, and may be, for example, a full-surface electrode covering the entire back surface.

Further, the solar cell wafer described in each embodiment can be applied to the solar cell module of the second embodiment.

The embodiments of the present invention have been described above, but the embodiments are merely examples and are not intended to limit the scope of the invention. The implementation of the new rules can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The invention and its modifications are intended to be included within the scope and spirit of the invention.

10‧‧‧Solar cell chip

11‧‧‧1st conductive semiconductor substrate

12‧‧‧2nd conductive semiconductor layer

13‧‧‧Anti-reflective film

14‧‧‧Glossy gate

15‧‧‧Photon auxiliary electrode

16‧‧‧1st conductive semiconductor layer

17‧‧‧Anti-reflective film

19‧‧‧Back auxiliary electrode

11A‧‧‧Glossy surface

11B‧‧‧Back

11T‧‧‧ textured

K‧‧‧ distance

Claims (6)

A solar cell having a collector electrode formed on a light receiving surface of a substrate having a photoelectric conversion portion, wherein: an auxiliary electrode is formed on the photoelectric conversion portion; and a plurality of gate electrodes are arranged in parallel on both sides of the auxiliary electrode The gate electrode is located on a straight line at one end of the auxiliary electrode and connected to the auxiliary electrode, and the gate has an oblique line on one side of the auxiliary electrode except one end of the auxiliary electrode. a portion of the gate in the same row as the side of the auxiliary electrode, wherein the connection portion between the gate and the auxiliary electrode on one side of the auxiliary electrode is opposite to the other side of the auxiliary electrode The oblique portion of the gate and the connecting portion of the auxiliary electrode have a shift along the extending direction of the auxiliary electrode. The solar cell according to claim 1, wherein a configuration angle between the oblique portion of the gate and the auxiliary electrode is 9 degrees or more and less than 90 degrees. The solar cell according to claim 1 or 2, further comprising: a first conductive type semiconductor substrate having a first main surface and a second main surface facing each other; and a second conductive type semiconductor layer formed on the above The first main surface of the first conductive semiconductor substrate has a conductivity type opposite to that of the first conductive semiconductor substrate; and the first electrode is in contact with at least a portion of the second conductive semiconductor layer; The second electrode is in contact with at least a portion of the second main surface of the first conductive semiconductor substrate, and the collector electrode is located on both surfaces of the first main surface and the second main surface. A solar cell module having: at least one solar cell; and at least one interconnecting wire connected to the auxiliary electrode; the interconnecting wire is led out from one end; and the solar cell has a photoelectric conversion portion a collector electrode formed on a light receiving surface of the substrate: the auxiliary electrode is formed on the photoelectric conversion portion; and a plurality of gate electrodes are arranged in parallel on both sides of the auxiliary electrode; and the gate electrode is in the auxiliary electrode The one end portion is connected to the auxiliary electrode in a straight line, and the gate has a diagonal portion on one side of the auxiliary electrode, in addition to the one end portion of the auxiliary electrode, and the auxiliary electrode In the gates of the same row on both sides, the connection portion between the gate on one side of the auxiliary electrode and the auxiliary electrode is connected to the oblique portion of the gate and the auxiliary electrode on the other side of the auxiliary electrode The portion has an offset along the extending direction of the auxiliary electrode. The solar cell module according to claim 4, wherein a configuration angle between the oblique portion of the gate and the auxiliary electrode is 9 degrees or more and less than 90 degrees. The solar cell module of claim 4 or 5, wherein the solar cell has: The first conductive semiconductor substrate has a first main surface and a second main surface facing each other, and the second conductive semiconductor layer is formed on the first main surface of the first conductive semiconductor substrate. a first conductivity type semiconductor substrate having a reverse conductivity type; a first electrode contacting at least a portion of the second conductivity type semiconductor layer; and a second electrode and at least a second main surface of the first conductivity type semiconductor substrate a part of the contact; the collector electrode is located on both sides of the first main surface and the second main surface.