TWI536452B - Method of fabricating dielectric layer and shallow trench isolation - Google Patents

Description

Method of fabricating dielectric layer and shallow trench isolation

The invention relates to a method for fabricating a dielectric layer, in particular to a surface treatment process applicable to a dielectric layer of shallow trench isolation.

In the semiconductor process, in order to have good isolation between the various electronic components on the wafer to avoid short-circuit phenomenon caused by mutual interference of components, generally used localized oxidation isolation (LOCOS) or shallow trench isolation (shallow trench isolation) , STI) method for isolation and protection. Since the area of the wafer occupied by the field oxide generated in the LOCOS process is too large, and the generation process is accompanied by the occurrence of a bird's beak phenomenon, it has a small-sized isolation line width and a clear active area division. The shallow trench isolation method, which has the advantages of uniform isolation depth, scalable size, and excellent isolation flat structure, has gradually become the mainstream of semiconductor component isolation technology.

The method of fabricating shallow trench isolation is generally to create a trench between the components on the surface of the wafer and fill the insulating material to produce an electrical isolation effect. However, as semiconductors move toward miniaturization and high integration, a dielectric layer is formed on the surface of the semiconductor wafer by chemical vapor deposition (CVD) and fills the trench. At the time, it is very easy because of the excessive aspect ratio of the trench, and the overhang of the corner portion at the top of the trench occurs. The phenomenon is such that there is a void in the shallow trench isolation formed.

In addition, in the process of manufacturing a semiconductor device, a plurality of etching and cleaning processes are performed, for example, an etching process for removing the cap layer and the hard mask layer of each transistor, and etching of the spacer layer. The subsequent cleaning process, the cleaning process performed after the source/drain formation in the active region, the pre-cleaning process performed before the formation of the metal telluride layer, and finally the etching of the unreacted metal layer is removed. Processes, etc., while performing these etching processes and cleaning processes, tend to cause damage to the exposed shallow trenches, causing recesses in the shallow trench isolation surface, or forming voids at the interface between the substrate and the shallow trenches.

Therefore, how to improve the shallow trench isolation process to avoid the occurrence of the above defects and avoid the formation of leakage current is a problem that the related art desires to improve.

One of the objects of the present invention is to provide a method for fabricating a dielectric layer and shallow trench isolation to avoid defects in the dielectric layer and shallow trench isolation during fabrication or subsequent processing.

A preferred embodiment of the present invention provides a method of fabricating a dielectric layer, the steps of which are as follows. First, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Then, after performing the chemical mechanical polishing process, a surface treatment process is performed on the dielectric layer, wherein the surface treatment process is performed. The process involves the introduction of an oxygen plasma.

Another preferred embodiment of the present invention provides a method of making shallow trench isolation, the steps of which are as follows. First, at least one trench is formed in a substrate, and a dielectric layer is formed to fill the trench. Subsequently, a chemical mechanical polishing process is performed on the dielectric layer. Next, after performing the chemical mechanical polishing process, a surface treatment process is performed on the dielectric layer, wherein the surface treatment process includes passing an oxygen plasma.

The invention uses a flow chemical vapor deposition (FCVD) process to form a dielectric layer, so that the dielectric layer can completely cover the substrate and fill the trench without generating holes or voids, thereby achieving good trench filling. (gap filling) effect. In addition, the oxygen plasma treatment process is performed on the surface of the dielectric layer, so that oxygen radicals cause a dangling bond of the surface of the dielectric layer to improve the density of the dielectric layer. To avoid damage to the dielectric layer during subsequent etching and cleaning processes, to help maintain the structural integrity and insulation of the dielectric layer.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figures 1 to 6. 1 to 6 are schematic views showing a method of fabricating shallow trench isolation in accordance with a preferred embodiment of the present invention. As shown in Figure 1, prior to the base A silicon oxide 12 is formed on the bottom 10 by, for example, a thermal oxidation process, and a silicon nitride 14 is formed, for example, by a low pressure chemical vapor deposition (LPCVD) process. The substrate 10 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. The silicon oxide layer 12 is a pad oxide layer, which can be used as a stress buffer layer of the nitrogen germanium layer 14 to increase the adhesion of the nitrogen germanium layer 14 to the substrate; and the nitrogen germanium layer 14 can be used as a subsequent etching. A hard mask or a stop layer of a chemical mechanical polishing (CMP) process. The process for forming each of the above-mentioned film layers is not limited to the above-described thermal oxidation process and low-pressure chemical vapor deposition process, and may be a wet chemical oxidation process, another chemical vapor deposition process, or the like.

Next, as shown in FIG. 2, at least one trench R is formed in a predetermined region of the substrate 10 by a process such as photolithography and etching, and the trench R is passed through the silicon oxide layer 12 and The yttrium nitride layer 14 penetrates the substrate 10 to a predetermined depth. For example, a photoresist layer (not shown) is formed on the ytterbium layer 14 and a lithography process is performed to form a patterned photoresist layer (not shown), and the photoresist is patterned. The layer can roughly define a pattern of recesses R, and then, by patterning the photoresist layer as a patterned mask layer, performing an etching process such as reactive ion etching (reactive-ion-etching, RIE) The process removes a portion of the nitrogen ruthenium layer 14, a portion of the ruthenium oxide layer 12, and a portion of the substrate 10 to form trenches R in the substrate 10, and subsequently, removes the patterned photoresist layer. In addition, the pattern of the patterned photoresist layer may be transferred to the opening of the exposed portion of the substrate 10 by the nitrogen layer 14 and the silicon oxide layer 12, and then the patterned photoresist layer is removed. The nitride layer 14 and the germanium oxide layer 12 are collectively used as a patterned mask layer, and an etching process is performed to remove a portion of the substrate 10 to form the trench R. The manner of defining the patterned mask layer of the trench R pattern and forming the trench R is not limited thereto. Further, after the trench R is formed in the substrate 10, the patterned mask layer may be selectively performed. The process is pulled back to adjust the shape of the patterned mask layer.

Next, a liner 16 is formed to cover the substrate 10, particularly the surface of the trench R to repair damage to the surface of the substrate 10 when the trench R is formed. The lining layer 16 may be a single layer structure composed of a tantalum nitride layer, a ruthenium oxide layer or a ruthenium oxynitride layer, or a two-layer structure composed of a tantalum oxide layer and a tantalum nitride layer. For example, a ruthenium oxide layer can be formed by a process such as thermal oxidation or chemical vapor deposition (CVD) and then selectively nitrided. In this embodiment, the lining layer 16 may be a ruthenium oxide layer formed by an in situ steam generation (ISSG) process, but is not limited thereto.

Subsequently, as shown in FIG. 3, a dielectric layer 18 is formed to fill the trenches R. In order to enable the dielectric layer 18 to completely fill the trench R having a high aspect ratio and prevent the formation of voids, it is preferred to perform a flowable chemical vapor deposition (FCVD) process, including the following steps. First, a deposition process is performed to form a layer of flowable dielectric material (not shown) on the substrate 10. The flowable dielectric material layer is generally in a liquid state to completely cover the bottom of the trench R and sufficiently fill the trench R, the material of which comprises, but is not limited to, trisilylamine (TSA). Next, a curting process is performed on the flowable dielectric material layer, and the curing process can include performing an ozone (O ₃ ) plasma processing process to convert the flowable dielectric material layer into the dielectric layer 18 For example, a layer of cerium oxide The process temperature range of the curing process is substantially between 100 degrees Celsius (°C) and 250°C. The curing process is preferably performed once after the deposition process to save process time, but is not limited thereto, and the curing process may be alternated with the deposition process. In other embodiments, the method of converting the flowable dielectric material layer into the dielectric layer 18 can also include direct oxidation of oxygen, ozone, or water vapor by performing an oxidation process.

The dielectric layer 18 is not limited to being formed by an FCVD process, and may also be subjected to high-density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD) or spin. A process such as a spin-on dielectric (SOD) is used to form a dielectric layer 18 to fill the trenches R.

In addition, in order to further strengthen the density of the dielectric layer 18, a heat treatment process P1 may be performed on the dielectric layer 18 after the above curing process. The heat treatment process P1 comprises a steam heat treatment process and a nitrogen heat treatment process, wherein a process temperature range of the steam heat treatment process is substantially between 600 ° C and 800 ° C, and a process temperature of the nitrogen heat treatment process is substantially greater than 1000 ° C . In more detail, the steam heat treatment process is steamed into a reaction chamber having a temperature range substantially between 600 ° C and 800 ° C; and the nitrogen heat treatment process is passed through a nitrogen atmosphere at a temperature substantial In a reaction chamber greater than 1000 ° C.

Next, as shown in FIG. 4, a planarization process such as chemical mechanical polishing (CMP) is performed on the dielectric layer 18 by using the yttrium nitride layer 14 as a polishing stop layer, and a portion of the dielectric layer 18 is removed. Part of the liner 16 to flatten the dielectric Layer 18 forms dielectric layer 18' and the surface of dielectric layer 18' is approximately flush with the surface of nitride layer 14. After the chemical mechanical polishing process, a surface treatment process P2 is performed on the dielectric layer 18', and the process temperature range of the surface treatment process P2 is preferably smaller than the process temperature range of the heat treatment process P1, and the process time of the surface treatment process P2 is also It is preferably less than the process time of the above heat treatment process P1 to avoid accumulating excessive thermal budget. In this embodiment, the surface treatment process P2 includes the introduction of an oxygen plasma, such as an oxygen-containing high density plasma (HDP), and the process temperature range is substantially between 300 ° C and 400 ° C. Between, and the process time is substantially no more than 1 minute.

It should be noted that the surface treatment process P2 of the present embodiment is for providing oxygen radicals to penetrate into the partial dielectric layer 18' for dangling bonds of the surface of the dielectric layer. The junction further increases the density of the dielectric layer 18', wherein the depth of oxygen radical penetration can be adjusted by radio frequency (RF) power and process time. At this time, the structure of the upper half of the dielectric layer 18' (penetrated by oxygen radicals) is denser than the structure of the lower half of the dielectric layer 18' (not penetrated by oxygen radicals), and thus can be avoided. The etchant or cleaning agent in the subsequent etching and cleaning process destroys the exposed surface of the dielectric layer 18', or even causes loss of the substrate 10 on both sides of the dielectric layer 18', thereby helping to maintain the dielectric layer 18'. Structural integrity and insulation effects. Further, the surface treatment process P2 is not limited to an oxygen plasma, and oxygen radicals may be obtained by dissolving an oxygen-containing gas such as oxygen (O ₂ ) or ozone (O ₃ ) by heating or ultraviolet irradiation.

Subsequently, as shown in FIG. 5, after the surface treatment process P2, the above-mentioned heat treatment process P1 may be selectively performed on the dielectric layer 18' based on the process requirements, that is, the heat treatment process P1 of the same condition may be used again. The steam heat treatment process and the nitrogen heat treatment process further increase the density of the dielectric layer 18', wherein the process temperature range of the heat treatment process P1 is substantially greater than the process temperature range of the surface treatment process P2, of course, the heat treatment process here is also It may be different from the parameter conditions of the previous heat treatment process P1. Then, a dry or wet etching process is selectively performed to remove portions of the dielectric layer 18' to adjust the upper surface height of the dielectric layer 18'; in another embodiment of the invention, after chemical mechanical polishing, An etching process for adjusting the surface height is selectively performed on the dielectric layer 18' before the surface treatment process P2. Finally, as shown in FIG. 6, performing a stripping step may include, for example, removing the remaining nitrogen ruthenium layer 14 using a hot phosphoric acid solution and diluting the hydrofluoric acid solution to remove the remaining ruthenium oxide layer 12 or protruding from the surface of the substrate. The electrical layer 18' is either subjected to a dry etching process to remove the remaining layer of nitrogen nitride 14 and the remaining layer of germanium oxide 12. At this point, the shallow trench isolation 20 is completed.

In more detail, when the surface of the dielectric layer 18' of the shallow trench isolation 20 has been exposed to the oxygen plasma, that is, the surface of the dielectric layer 18' has been treated with oxygen plasma, a portion of the dielectric layer 18' will be The density is increased, that is, the etch rate of the surface of the dielectric layer 18' can be reduced. Therefore, when the stripping step described above is performed, the dielectric layer 18' can be effectively prevented from being excessively removed. The extent to which the trench R is completely filled, for example, is that the top surface T1 of the dielectric layer 18' is lower than the top surface T2 of the substrate 10, whereby the surface treatment process P2 of the present invention helps maintain shallow trench isolation 20 and shallow trenches. The structure of the substrate 10 on both sides of the isolation 20 is complete, in particular, the structure of the substrate 10 adjacent to the top corner of the shallow trench isolation 20 is completed. whole.

The invention is also applicable to the dielectric layer process of shallow trench isolation of non-planar transistors, please refer to Figures 7 to 8. 7 to 8 are schematic views showing a method of fabricating shallow trench isolation according to another preferred embodiment of the present invention. As shown in FIG. 7, a patterned hard mask 22 is first formed on the substrate 10 to define at least one fin structure 24. An etching process is then performed to remove portions of the substrate 10 while forming a plurality of fin structures 24 and a plurality of trenches R therebetween in the substrate 10. Then, according to the above-described flowable chemical vapor deposition (FCVD) process, high-density plasma chemical vapor deposition (HDPCVD) process, sub-atmospheric chemical vapor deposition (sub-atmosphere CVD). The SACVD process or spin-on dielectric (SOD) process is equivalent to forming at least one dielectric material layer (not shown) on the substrate 10, covering the fin structures 24 and filling the trenches R. The dielectric material layer is then planarized by a chemical mechanical polishing process (CMP) to form the dielectric layer 26, and after the chemical mechanical polishing process (CMP), the dielectric layer 26 is subjected to a surface treatment process P2, wherein the surface treatment Process P2 includes the introduction of an oxygen plasma. Finally, as shown in FIG. 8, the patterned hard mask 22 and a portion of the dielectric layer 26 are removed by at least one etching process to form corresponding shallow trench isolations 28 in the substrate 10 between the fin structures 24.

Features of the present invention, such as the first to sixth and seventh to eighth embodiments described above, are those in which a planarization process such as a chemical mechanical polishing process is followed by a surface treatment. Process such as an oxygen plasma processing process in which a dielectric The layer can serve as an element isolation structure for any semiconductor device. Moreover, the present invention is applicable to other element isolation structure processes, such as an inter-layer dielectric layer (ILD), in addition to the dielectric layer process of the shallow trench isolation described above for a planar transistor or a non-planar transistor. Process or inter-metal dielectric layer (IMD) process.

Take the interlayer dielectric layer as an example. Please refer to Figure 9 and Figure 10. 9 to 10 are schematic views showing a method of fabricating a metal interconnect structure according to a preferred embodiment of the present invention. As shown in FIG. 9, a substrate 10 is first provided, and then planar or non-planar elements are formed thereon, for example, a gate structure 30 is formed on the substrate 10 between the source drain doping regions 31, and the gate structure is formed. 30 includes a gate dielectric layer 32, a gate conductive layer 34, a cap layer (not shown), and a sidewall spacer 38. The process and materials of the gate structure 30 are well known to those of ordinary skill in the art, and thus will not be described again. . When the gate conductive layer 34 is composed of polysilicon, after the cap layer is removed, a self-aligned metal telluride process is performed to form the metal telluride layer 36 in the gate conductive layer 34 and the source drain doping region 31. on. Then, a chemical vapor deposition process is sequentially performed to form a contact etching stop layer (CESL) 40 and a dielectric layer 42 is formed on the substrate 10. The dielectric layer 42 may include a low dielectric constant. (dielectric constant, k) material (dielectric constant value less than 3.9), ultra low dielectric constant (ultra low-k, hereinafter referred to as ULK) material (dielectric constant value less than 2.6), or porous ultra low dielectric constant (porous ULK) material, and the method of forming the dielectric layer 42 includes performing an FCVD, a plasma enhanced chemical vapor deposition (PECVD), an atmospheric pressure chemical vapor deposition (APCVD). ) or less often Process of sub-atmospheric pressure chemical vapor deposition (SACVD).

Next, the dielectric layer 42 is subjected to a planarization process such as a chemical mechanical polishing process, and after the chemical mechanical polishing process, the planarized dielectric layer 42 is further subjected to a surface treatment process P2, wherein the surface treatment process P2 includes An oxygen plasma is introduced to cause the dangling bonds in the dielectric layer 42 to be linked to each other due to the entry of oxygen radicals. Similarly, the structure of the upper half of the dielectric layer 42 (penetrated by oxygen radicals) will The structure of the lower half of the dielectric layer 42 (not penetrated by oxygen radicals) is denser, so that the density of the surface of the dielectric layer 42 can be increased, and etching or cleaning in the subsequent etching and cleaning processes can be avoided. The agent destroys the surface of the dielectric layer 42 or even causes loss of the dielectric layer 42 to maintain the structural integrity and insulating effect of the dielectric layer 42.

Subsequently, as shown in FIG. 10, over the planarized dielectric layer 42, a cap layer 44 is formed in its entirety, the cap layer 44 comprising a dielectric material. In other embodiments, after the continuous deposition process of the dielectric layer and the cap layer, a planarization process and a surface treatment process P2 are applied to the cap layer composed of the dielectric material to make the dangling bonds in the cap layer interlock with each other. The structure, in turn, allows the structure of the upper half of the cover layer (penetrated by oxygen radicals) to be denser than the structure of the lower half of the cover layer (not penetrated by oxygen radicals). Then, a process such as lithography and etching is performed to remove a portion of the cap layer 44, a portion of the dielectric layer 42 and a portion of the contact etch stop layer 40 to form at least one contact opening O in the dielectric layer 42 and the metal telluride layer. 36 will be exposed to the bottom of the contact window opening O, and then, a barrier layer (not shown), a seed layer (not shown) and a layer are further sequentially formed in the contact window opening O. The conductive layer 48 of the contact window opening O is filled, and finally the surface of the conductive layer 48 is aligned with the surface of the cover layer 44 by a planarization step, and thus the fabrication of the metal interconnect structure is completed. The above-described metal interconnecting process is well known to those skilled in the art and will not be described in detail in this embodiment.

In addition, the present invention can be further applied to various semiconductor processes having a high-k dielectric layer, for example, a gate-gate process including a gate first process and a gate last process. The high-k first process and the high-k last process after the gate process.

For example, after the gate process, the gate dielectric layer process is taken as an example. Please refer to Figure 11 to Figure 13, and please refer to Figure 9 together. 11 to 13 are schematic views showing a method of fabricating a metal gate structure according to a preferred embodiment of the present invention. As shown in Figure 11. First, a substrate 10 is provided, and a dielectric layer 50 is disposed on the substrate 10 to cover a dummy gate structure such as the gate structure 30 shown in FIG. 9. Then, a planarization process such as a chemical mechanical polishing process is performed. To remove a portion of the dielectric layer 50 and the cap layer to expose the gate conductive layer 34, similarly, to improve the structural strength of the dielectric layer 50, the dielectric layer 50 is subjected to a surface treatment after the chemical mechanical polishing process. The process P2 is, for example, an oxygen plasma treatment process such that the structure of the upper half of the dielectric layer 50 (penetrated by oxygen radicals) is smaller than the structure of the lower half of the dielectric layer 50 (not penetrated by oxygen radicals). Dense. Then, as shown in FIG. 12, the gate conductive layer 34 is removed and the gate dielectric layer 32 is selectively removed to form an opening surrounded by the sidewalls 38, and a high-k dielectric layer 52 is sequentially formed. The work function metal layer 54 and the metal conductive layer 56 are filled in the opening, and finally, another planarization system is performed. The surface of the remaining high-k dielectric layer 52, the surface of the work function metal layer 54 and the surface of the metal conductive layer 56 are both aligned with the surface of the dielectric layer 50 to complete the metal gate structure 58. The materials and processes of the metal gate structure are well known to those skilled in the art and will not be described in detail in this embodiment.

Subsequently, as shown in FIG. 13, a capping layer 60 is formed over the planarized dielectric layer 50, and the capping layer 60 comprises a dielectric material. In other embodiments, the planarization process and the surface treatment process P2 may be applied to the cover layer composed of the dielectric material in order, so that the upper half of the cover layer (penetrated by oxygen radicals) is more than the cover layer. The structure of the lower half (not penetrated by oxygen radicals) is denser. Thereafter, a process such as lithography and etching is performed to remove a portion of the cap layer 60 and a portion of the dielectric layer 50 to form at least one contact opening O' in the cap layer 60 and the dielectric layer 50. Next, a self-aligned metal telluride process is performed to form a metal telluride layer 62 at the bottom of the contact opening O'. Next, as in the foregoing embodiment, a barrier layer (not shown), a seed layer (not shown), and a conductive layer filling the contact opening O' are further sequentially formed in the contact opening O'. 64. Finally, the surface of the conductive layer 64 is aligned with the surface of the cover layer 60 by a planarization step, and thus the fabrication of the metal interconnect structure is completed. The above-described metal interconnecting process is well known to those skilled in the art and will not be described in detail in this embodiment.

In summary, the present invention uses a flowable chemical vapor deposition (FCVD) process to form a dielectric layer, so that the dielectric layer can completely cover the substrate and fill the trench without creating voids or voids. A good gap filling effect is achieved. Then, after completing the planarization process of the dielectric layer, oxygen is applied to the surface of the dielectric layer. The plasma treatment process can cause oxygen radicals to cause a dangling bond in the dielectric layer to increase the density of the dielectric layer, especially to improve the upper half of the dielectric layer. The density of the part makes the structure of the upper half of the dielectric layer (penetrated by oxygen radicals) denser than the lower part of the dielectric layer (not penetrated by oxygen radicals), thereby effectively avoiding The electrical layer is damaged during subsequent etching and cleaning processes to help maintain the structural integrity and insulation of the dielectric layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base

12‧‧‧Oxygen layer

14‧‧‧Nitrate layer

16‧‧‧ lining

18,18’,26,42,50‧‧‧ dielectric layer

20,28‧‧‧Shallow trench isolation

22‧‧‧ patterned hard mask

24‧‧‧Fin structure

30‧‧‧ gate structure

31‧‧‧ source bungee doped area

32‧‧‧ gate dielectric layer

34‧‧‧ gate conductive layer

36,62‧‧‧metal telluride layer

38‧‧‧ Sidewall

40‧‧‧Contact window etch stop layer

44, 60‧‧‧ cover

46‧‧‧metal telluride layer

48,64‧‧‧ Conductive layer

52‧‧‧High dielectric constant dielectric layer

54‧‧‧Work function metal layer

56‧‧‧Metal conductive layer

58‧‧‧Metal gate structure

R‧‧‧ trench

P1‧‧‧ Heat treatment process

P2‧‧‧ surface treatment process

T1, T2‧‧‧ top surface

O, O’‧‧‧Contact window opening

1 to 6 are schematic views showing a method of fabricating shallow trench isolation in accordance with a preferred embodiment of the present invention.

7 to 8 are schematic views showing a method of fabricating shallow trench isolation according to another preferred embodiment of the present invention.

9 to 10 are schematic views showing a method of fabricating a metal interconnect structure according to a preferred embodiment of the present invention.

11 to 13 are schematic views showing a method of fabricating a metal gate structure according to a preferred embodiment of the present invention.

10‧‧‧Base

12‧‧‧Oxygen layer

14‧‧‧Nitrate layer

16‧‧‧ lining

18'‧‧‧ dielectric layer

P2‧‧‧ surface treatment process

Claims (20)

A method of fabricating a dielectric layer, comprising: forming a dielectric layer on a substrate; performing a heat treatment step on the dielectric layer; performing a chemical mechanical polishing (CMP) process on the dielectric layer to Flattening a surface of the dielectric layer; and performing a surface treatment process on the surface of the planarized dielectric layer after performing the chemical mechanical polishing process, wherein the surface treatment process includes introducing an oxygen ( Oxygen) plasma. A method of fabricating a dielectric layer according to claim 1, wherein the oxygen plasma comprises oxygen radicals. A method of fabricating a dielectric layer according to claim 1, wherein a process temperature range of the surface treatment process is substantially between 300 ° C and 400 ° C. The method of fabricating a dielectric layer according to claim 1, wherein the method of forming the dielectric layer comprises performing a flowable chemical vapor deposition (FCVD) process, the step comprising: forming a flowable medium An electrically material layer is applied to the substrate; a curting process is performed on the layer of flowable dielectric material; and the heat treatment process is performed. A method of fabricating a dielectric layer according to claim 4, wherein the material of the flowable dielectric material layer comprises trisilylamine (TSA). The method of fabricating a dielectric layer of claim 4, wherein the curing process comprises performing an ozone (O ₃ ) plasma treatment process. The method of fabricating a dielectric layer according to claim 4, wherein the heat treatment process comprises: a steam heat treatment process, wherein a process temperature range of the steam heat treatment process is substantially between 600 ° C and 800 ° C; A nitrogen heat treatment process in which a process temperature of the nitrogen heat treatment process is substantially greater than 1000 °C. The method for fabricating a dielectric layer according to claim 1, after performing the surface treatment process, further comprising performing the heat treatment process, and a process temperature range of the surface treatment process is substantially smaller than a process temperature range of the heat treatment process . The method of fabricating a dielectric layer according to claim 1, further comprising forming a liner on the substrate before forming the dielectric layer on the substrate. The method of fabricating a dielectric layer according to claim 9, wherein the liner layer comprises a single layer structure composed of a tantalum nitride layer, a hafnium oxide layer or a hafnium oxynitride layer, or a tantalum oxide layer and a tantalum nitride layer. A two-layer structure. A method for fabricating shallow trench isolation includes: forming at least one trench in a substrate; forming a dielectric layer to fill the trench; performing a heat treatment step on the dielectric layer; performing a chemical mechanical process on the dielectric layer a chemical mechanical polishing (CMP) process for planarizing a surface of the dielectric layer; and performing a surface treatment process on the surface of the planarized dielectric layer after performing the chemical mechanical polishing process Wherein the surface treatment process comprises introducing an oxygen plasma. A method of making shallow trench isolation as described in claim 11, wherein the oxygen plasma comprises oxygen radicals. A method of fabricating shallow trench isolation as described in claim 11, wherein a process temperature range of the surface treatment process is substantially between 300 ° C and 400 ° C. The method of fabricating shallow trench isolation according to claim 11, wherein the method of forming the dielectric layer comprises performing a flowable chemical vapor deposition (FCVD) process, the step comprising: forming a flowable dielectric An electrically material layer is disposed on the substrate; a curting process is performed on the flowable dielectric material layer; and the heat treatment process is performed on the flowable dielectric material layer. A method of fabricating shallow trench isolation as described in claim 14, wherein the curing process comprises performing an ozone (O ₃ ) plasma treatment process. The method of fabricating shallow trench isolation as described in claim 14, wherein the heat treatment process comprises: a steam heat treatment process, wherein a process temperature range of the steam heat treatment process is substantially between 600 ° C and 800 ° C; A nitrogen heat treatment process in which a process temperature of the nitrogen heat treatment process is substantially greater than 1000 °C. The method for fabricating shallow trench isolation according to claim 11, after performing the surface treatment process, further comprising performing the heat treatment process, and a process temperature range of the heat treatment process is substantially greater than a process temperature range of the surface treatment process . The method of fabricating shallow trench isolation according to claim 11, wherein the method of forming the trench comprises: forming a patterned mask layer on the substrate; performing an etching process to form the trench; and forming a liner Covering the surface of the trench. The method for fabricating shallow trench isolation according to claim 18, wherein the liner comprises a single layer structure consisting of a tantalum nitride layer, a tantalum oxide layer or a hafnium oxynitride layer, or a tantalum oxide layer and a nitride layer. A two-layer structure composed of enamel layers. The method of fabricating shallow trench isolation according to claim 11, wherein at least one fin structure is disposed on the substrate, and the trench is formed on at least one side of the fin structure.