TWI805666B - Method for forming a semeconductor device - Google Patents

Abstract

A method for forming a semiconductor device includes providing a structure having an interconnection formed on a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers, wherein the structure has a first area and a second area; forming a memory cell structure in the first area, and the memory cell structure formed above one of the interconnect layers; depositing an inter-metal dielectric (IMD) layer above the interconnection, and the IMD layer covering the memory cell structure; forming a photo-resist layer on the IMD layer; patterning the photo-resist layer to expose a protruding portion of the IMD layer above the memory cell structure in the first area and remain a resist portion in the second area; hardening the resist portion to form a resist mask in the second area; and etching the protruding portion of the IMD layer using the resist mask.

Description

Method of forming semiconductor device

The present invention relates to a method of forming a semiconductor device, and in particular to a method of forming, so that the dielectric layer covered by regions with different element distribution densities in the manufactured semiconductor device has a flat surface after planarization.

In recent years, semiconductor devices have been increasingly reduced in size. For semiconductor technology, it is an important development goal of semiconductor technology to continuously reduce the size of semiconductor structures, improve speed, increase performance, increase density and reduce the cost per unit circuit. As the size of the semiconductor device shrinks, its electronic characteristics must still be maintained or even further improved in order to meet the requirements of the applied electronic products in the market. For example, if the structure of each layer in a semiconductor device and its components are damaged or the surface is uneven, it will have a non-negligible impact on the electronic characteristics of the device. Therefore, this is one of the important issues that semiconductor manufacturers need to pay attention to.

In the current post-planarization process of the back-end process, for some areas with no or almost no structure, there is usually a problem of dishing due to over-polishing or erosion. As known to those skilled in the art, unwanted metal residues can remain on In the dishing area of the structure, this will cause short circuit problems in the subsequent metal interconnection process. Therefore, it is necessary to develop a method that can make the forming element have a complete profile without defects such as dents and residues, so as to meet the requirements of application products.

The present invention relates to a method of forming a semiconductor device, which uses hardening photoresist and related removal steps, so that the dielectric layer covered by the regions with different component distribution densities in the semiconductor device produced has a flattening after the planarization step flat surface.

According to an embodiment, a method of forming a semiconductor device is provided, including: providing a structure including an interconnection formed on a substrate, and the interconnection includes a plurality of interconnection layers (interconnect layers) respectively buried in the dielectric layer, wherein the structure has a first area and a second area; a memory structure is formed in the first area, and the memory structure is formed in one of the interconnection layers above; deposit an inter-metal dielectric layer (inter-metal dielectric layer, IMD) above the interconnection line, and the inter-metal dielectric layer covers the memory structure; form a photoresist layer on the inter-metal dielectric layer; patterning the photoresist layer to expose a protruding portion of the IMD layer above the memory structure in the first region, and leave a resist portion in the second region; hardening the photoresist part to form a photoresist mask in the second region; and etching the protruding part of the intermetal dielectric layer through the photoresist mask.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

10: Substrate

11: Inner connection

12: Dielectric layer

13: Inner layer

131: wire

132: conductive hole

14: Memory structure

141: Bottom electrode

142:Magnetic Tunneling Junction Stacking

143: top electrode

145: gap wall

15: Inter-metal dielectric layer

151: overhang

151', 151C: Part I

152, 152C: Part Two

151a: Upper surface of the protrusion

151'-a, 151C-a: the upper surface of the first part

152a, 152C-a: the upper surface of the second part

16: Photoresist layer

161: Photoresist part

161a: the upper surface of the photoresist part

162, 162': photoresist mask

162a: Top surface of photoresist mask

A1: The first area

A2: Second area

△H ₀ : initial height difference

H ₁ : first height

H ₂ : second height

H _d : Height difference between the first part and the second part

1A-1G are diagrams illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure.

In an embodiment of the present disclosure, a method for forming a semiconductor device is proposed. According to an embodiment, before removing the dielectric layer (such as the inter-metal dielectric layer) covering the densely distributed area, first cover the dielectric layer in the area that does not contain components or where the component distribution density is sparse with a hardened photoresist. layer, so as to avoid the problem of dishing caused by over-etching of the dielectric layer corresponding to the region without components or with sparse distribution of components. Therefore, according to the method proposed in the embodiment, the dielectric layer covered by the regions with different component distribution densities in the manufactured semiconductor device can be placed on a flat surface. It has a flat surface after tanning. The method proposed in the embodiment can be applied to a planarization process (post-planarization process) in the back-end process (BEOL) of the wafer, so as to easily and effectively complete the structure of the components of the manufactured semiconductor device, especially It is a flat surface to maintain the electronic properties of the associated components.

The relevant embodiments are presented below, and the forming method proposed in this disclosure is described in detail with the aid of figures. However, the present disclosure is not limited to this example. It should be noted that this disclosure does not show all possible embodiments, so other implementations not mentioned in this disclosure may also be applicable. Those in the relevant art can make changes and modifications to the structure and process of the examples without departing from the spirit and scope of the present disclosure, so as to meet the needs of practical applications. Furthermore, the drawings have been simplified to clearly illustrate the content of the embodiments, and the size ratios in the drawings are not drawn according to the proportion of the actual product. Therefore, the specification and illustrations are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure.

Furthermore, the ordinal numbers used in the description and claims, such as "first", "second", etc., are used to modify the elements of the claims, which do not imply and represent that the claimed elements have any previous ordinal numbers. , nor does it represent the order of a certain requested element with another requested element, or the order of the manufacturing method. Can make a clear distinction. Furthermore, words related to the space that may be used in the description and the claim, such as "beneath" (beneath), "below," (below), "lower" (lower), "above" (above) , "higher" (upper) or similar words are used for convenience of description and reference to one element or feature as drawn with another The spatial relationship between elements or features. Therefore, those with ordinary knowledge can understand that these space-related terms not only include the orientation of the components shown in the figure, but also include the orientation of the component when it is used or operated differently from the figure. Therefore, the terms used in the specification and claims are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure.

1A-1G are diagrams illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure.

As shown in FIG. 1A, a structure including an interconnection 11 formed on a substrate 10 is proposed. In this example, the structure includes a first area A1 such as a memory area and a second area A2 such as a logic area. In one example, at least one memory cell structure (memory cell structure) 14 is formed in the first area A1, and the second area A2 is, for example, an area without components, or a component distribution compared to the first area A1 In terms of density, the distribution density of its related components is relatively sparse. In practical applications, the first area A1 may include a plurality of memory structures, and the second area A2 is, for example, embedded with a logic circuit in the insulating layer. In the following embodiments and the referenced drawings, only two memory structures are formed in the first area A1 and no components are shown in the second area A2 as an example for illustration.

In this example, the method proposed in the embodiment is applied to the planarization process in the back end of line (BEOL) of the wafer. As shown in FIG. 1A, the interconnection 11 on the substrate 10 includes a plurality of interconnection layers (interconnect layers) 13 respectively embedded in the dielectric layer (dielectric layers) 12, and forms a mark in the first area A1. The memory structure 14 is formed above an interconnect layer. Each interconnection layer includes, for example, a conductive hole (such as a contact hole filled with tungsten) 132 and a wire (such as a metal line) 131 , and the memory structure 14 is formed on the contact hole 132 . In order to simplify the illustration and facilitate the clear description of the formation method of the embodiment, only the second interconnection layer 13 in the dielectric layer 12 is briefly depicted in Figures 1A-1G, and two memory structures 14 are formed in the first region Above the second interconnection layer 13 of A1 (for example, the memory structure 14 is located above the conductive hole 132 such as the second contact hole V2 ), for non-limiting illustration.

Although, the memory structure 14 as drawn in Figure 1A (and subsequent drawings) is described as being formed on the second interconnection layer 13, wherein the second interconnection layer 13 is formed, for example, by a pair of The conductive hole 132 such as the second contact hole (abbreviated as "V2") and a wire 131 such as the second metal line (abbreviated as "M2") are formed, but the formation position of the memory structure 14 applicable to this disclosure is not limited to as position in the diagram. The memory structure 14 of the embodiment can be formed on any interconnection layer, or formed between any two adjacent interconnection layers; for example, the memory structure 14 can be formed on the third, fourth, or fifth interconnection layer, or formed between the third interconnection layer and the fourth interconnection layer, or formed between the fourth interconnection layer and the fifth interconnection layer, etc.

Furthermore, as shown in FIG. 1A , an inter-metal dielectric layer (IMD) 15 is deposited on the interconnection 11 and covers the memory structure 14 . Since the memory structure 14 is formed in the first area A1, and the second area A2 does not contain components (or in other embodiments, the second area A2 contains a relatively small number or sparsely distributed related components), the metal deposited at this time There is a relatively large step height ΔH ₀ between the uppermost surface corresponding to the first region A1 and the uppermost surface corresponding to the second region A2 of the interlayer dielectric layer 15 .

In addition, it is worth noting that the memory structure 14 of the embodiment can be appropriately changed and determined according to the requirements of components in practical applications. As the example presented in the text, the memory with magnetic tunnel junction (magnetic tunnel junction, MTJ) is used as an example of the memory structure 14 for illustration, but the present disclosure does not limit the aspect of the applicable memory structure 14 . As shown in FIG. 1A, a memory structure 14 includes a bottom electrode 141, a top electrode 143, and a magnetic tunnel junction stack (MTJ stacks) 142 disposed on the bottom electrode 141. and the top electrode 143. And the spacers 145 are formed on the sidewalls of the bottom electrode 141, the magnetic tunnel junction stack 142 and the top electrode 143, for example, the spacers 145 shown in FIG. 1A cover the bottom electrode 141 and the magnetic tunnel junction All sidewalls 142 of the stack, and at least a portion of the sidewalls covering the top electrode 143 .

After that, as shown in FIG. 1B , a resist material is covered on the inter-metal dielectric layer 15 ; for example, a photoresist layer 16 is formed on the inter-metal dielectric layer 15 . The photoresist layer 16 is deposited on the IMD layer 15 at a first temperature. In an example, the first temperature is lower than 170° C., for example. In another example, the first temperature ranges from 100° C. to 170° C., for example.

Afterwards, as shown in FIG. 1C, the photoresist layer 16 is patterned to expose a part of the inter-metal dielectric layer 15 above the memory structure 14 in the first region A1, such as one of the protruding parts in FIG. 1C. Part (protruding portion) 151, And a resist portion 161 is left in the second area A2. That is, after patterning, the portion of the photoresist layer 16 corresponding to the first area A1 is removed, and a resist portion 161 of the photoresist layer corresponding to the second area A2 is left. The patterning method can process the photoresist material through a polishing method such as Chemical-Mechanical Polishing (CMP).

50。 According to an embodiment, when the photoresist layer 16 is patterned, the removal rate of the photoresist layer 16 is greater than the removal rate of the IMD layer 15 . In one example, when the photoresist layer 16 is patterned, the removal rate (remove rate, RR) of the photoresist layer 16 (for example, denoted as RR _PR ) is relative to the removal rate of the inter-metal dielectric layer 15 ( For example, the ratio denoted as RR _ULK ) is equal to or greater than 50; that is, the ratio of the removal rate can be expressed as: RR _PR /RR _ULK

50.

Moreover, after the photoresist layer 16 is patterned, the upper surface 161a of the photoresist portion 161 left in the second area A2 is lower than the IMD layer above the memory structure 14 in the first area A1 The upper surface 151a of the protruding portion 151 of 15. As shown in FIG. 1C, the photoresist portion 161 left in the second area A2 has a first height (first height) H ₁ , and the IMD located above the memory structure 14 in the first area A1 The protruding portion 151 of the layer 15 has a second height (second height) H ₂ , and the first height H ₁ is smaller than the second height H ₂ . In addition, in an example, the first height H ₁ is equal to or greater than 1/2 of the second height H ₂ .

Afterwards, as shown in FIG. 1D, the photoresist portion 161 left in the second area A2 is hardened to form a photoresist in the second area. Resist mask 162 . Wherein, the photoresist portion 161 can be cured by baking the photoresist material through heating. The photoresist portion 161 is hardened at a second temperature. In an example, the second temperature is higher than 200° C., for example. In another example, the second temperature is, for example, in the range of 200°C to 350°C. Compared to the aforementioned first temperature for depositing the photoresist layer 16 on the IMD layer 15 (FIG. 1B), the second temperature for curing the photoresist portion 161 is higher than the first temperature for depositing the photoresist layer 16 .

10。蝕刻後，如第1E圖所示，光阻遮罩162’的上表面162a係高於位於記憶體結構14上方之金屬層間介電層15之一第一部份151’(first portion)的上表面151’-a。 Then, the protruding portion 151 of the IMD layer 15 is etched through the photoresist mask 162 . According to an embodiment, when etching is performed, the etching rate for the protruding portion 151 of the IMD layer 15 is greater than the etching rate for the photoresist mask 162 . In one example, the ratio of the etch rate (ER) of the protruding portion 151 of the IMD layer 15 (for example, denoted as ER _ULK ) relative to the etch rate of the photoresist mask 162 (for example, denoted as ER _PR ) is equal to or greater than 10; that is, the ratio of etch rates can be expressed as: ER _ULK /ER _PR

10. After etching, as shown in FIG. 1E, the upper surface 162a of the photoresist mask 162' is higher than that of a first portion 151' (first portion) of the IMD layer 15 above the memory structure 14. Surface 151'-a.

100Å)。 Thereafter, the photoresist mask 162' is removed, as shown in FIG. 1F. After removing the photoresist mask 162', a first portion 151' of the inter-metal dielectric layer 15 above the memory structure 14 in the first region A1 and a portion 151' of the inter-metal dielectric layer 15 in the second region A2 There is a step-height difference H _d between a second portion 152 . As shown in FIG. 1F , in one example, the upper surface 151 ′-a of the first portion 151 ′ is slightly higher than the upper surface 152 a of the second portion 152 . Furthermore, in one example, the height difference H _d between the first part 151' and the second part 152 is not more than 100 Å (ie

100Å).

After the photoresist mask 162' is removed, a planarization step is performed on the inter-metal dielectric layer, so that the upper surfaces of the inter-metal dielectric layers in the first region A1 and the second region A2 are substantially flush, as shown in Figure 1G. In the planarization step, the material of the inter-metal dielectric layer can be planarized by grinding methods, such as chemical mechanical polishing (CMP) which combines chemical etching and mechanical force. In one embodiment, the planarization of the inter-metal dielectric layer can be performed until the upper electrode of the memory structure 14 is exposed, so that the wires or vias in the subsequent process can be electrically connected to the memory through the contact with the electrode. body structure14. Taking this exemplary memory structure 14 including the bottom electrode 141, the magnetic tunnel junction stack 142 and the top electrode 143 as an example, the first portion 151' and the second portion 152 of the IMD layer are planar Thinning stops at the top electrode 143 (such as metal tantalum) of the memory structure, and exposes the upper surface 143 a of the top electrode 143 . As shown in FIG. 1G, after the planarization step, the inter-metal dielectric layer includes a first portion 151C in the first region A1 and a second portion 152C in the second region A2, and the top of the first portion 151C The surface 151C-a is substantially flush with the upper surface 152C-a of the second portion 152C.

According to the above, the method proposed in the embodiment can be applied to the planarization process of a back-end process, so that the dielectric layer covered by the regions with different component distribution densities in the manufactured semiconductor device has a flat surface after planarization. Therefore, according to the method proposed in the embodiment, in addition to avoiding the corresponding The dielectric layer in the sparse area is prone to the problem of dishing during the etching process, and it is not necessary to use an additional mask in the traditional method such as Reverse Mask Etch-back (RME), which can be easily The dielectric layer covered by the regions with different component distribution densities in the manufactured semiconductor device has a flat surface after planarization. Moreover, the method is compatible with the existing manufacturing process and has substantial economic benefits.

The structures and steps shown above are used to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the above structures and steps. Embodiments of other different structural forms, such as known components different from the illustrated memory structure or other memory structural forms are applicable, and the structures and steps of the examples can be adjusted according to actual application requirements. Therefore, the structure shown in the figure is only for illustration, not for limitation. Those with ordinary knowledge should know that the relevant structures and steps of the application of the present disclosure, such as the arrangement and location of the relevant components and layers in the semiconductor device, or the details of the manufacturing steps, etc., may be different according to the needs of the actual application. Adjust and change accordingly. Furthermore, those with ordinary knowledge should know that the values such as height, temperature, and ratio mentioned in the above examples are only for illustration rather than limitation.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Substrate

11: Inner connection

12: Dielectric layer

13: Inner layer

131: wire

132: conductive hole

14: Memory structure

141: Bottom electrode

142:Magnetic Tunneling Junction Stacking

143: top electrode

145: gap wall

151: overhang

152: Part Two

151a: Upper surface of the protrusion

152a: the upper surface of the second part

162: Photoresist mask

A1: The first area

A2: Second area

H ₁ : first height

H ₂ : second height

Claims (12)

A method of forming a semiconductor device, comprising: providing a structure comprising an interconnection (interconnection) formed on a substrate, and the interconnection includes a plurality of interconnection layers (interconnect layers) respectively embedded in dielectric layer, wherein the structure has a first region and a second region; a memory structure (memory cell structure) is formed in the first region, and the memory structure is formed in one of the interconnection layers Above, the memory structure includes a bottom electrode, a top electrode, and magnetic tunnel junction (MTJ) stacks disposed between the bottom electrode and the top electrode; depositing an intermetal dielectric layer (inter-metal dielectric layer, IMD) is above the interconnection line, and the inter-metal dielectric layer covers the memory structure; forming a photoresist layer on the inter-metal dielectric layer; patterning the photoresist layer, to expose a protruding portion (protruding portion) of the inter-metal dielectric layer above the memory structure in the first region, and leave a photoresist portion in the second region; harden the photoresist part to form a photoresist mask in the second region; and etching the protruding part of the inter-metal dielectric layer through the photoresist mask. The method according to claim 1, wherein after patterning the photoresist layer, an upper surface of the photoresist portion left in the second region The surface is lower than an upper surface of the protruding portion of the IMD layer above the memory structure in the first region. The method as described in claim 1, wherein after patterning the photoresist layer, the photoresist portion left in the second region has a first height (first height), the first The protruding portion of the IMD layer above the memory structure in the region has a second height, and the first height is equal to or greater than 1/2 of the second height. The method according to claim 1, wherein when patterning the photoresist layer, the ratio of the removal rate of the photoresist layer to the removal rate of the inter-metal dielectric layer is equal to or greater than 50. The method described in claim 1, wherein the photoresist layer is deposited on the inter-metal dielectric layer at a first temperature, and the photoresist portion is hardened at a second temperature, wherein the second temperature higher than the first temperature. The method described in claim 5, wherein the first temperature is in the range of 100°C to 170°C, and the second temperature is in the range of 200°C to 350°C. The method of claim 1, wherein a ratio of an etching rate of the protruding portion of the IMD layer to an etching rate of the photoresist mask is equal to or greater than 10. The method described in claim 1 further includes: removing the photoresist mask; and planarizing the inter-metal dielectric layer. The method as described in claim 8, wherein after removing the photoresist mask, a first portion (first) of the inter-metal dielectric layer above the memory structure in the first region portion) and a second portion of the IMD layer in the second region is no more than 100 Å. The method described in claim 8, wherein the inter-metal dielectric layer is planarized until it stops at the top electrode of the memory structure and exposes the top surface of the top electrode. The method described in item 1 of the scope of the patent application, wherein the first area is a memory area, and the second area is a logic area. The method described in claim 1, wherein the interconnection includes a wire and a contact via connected to the wire embedded in the dielectric layers, wherein the memory structure is formed on the contact hole.

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