TWI528523B - Overlay mark and manufacturing method thereof - Google Patents

Description

Overlap mark and its manufacturing method

The present invention relates to a pattern of a semiconductor process and a method of fabricating the same, and more particularly to a stacked mark and a method of fabricating the same.

In semiconductor processes, overlay marks are typically formed on the wafer to check the alignment between the front and back layers. For lithography processes below 40 nm resolution, the self-aligned double patterning process is now the dominant process. Especially for NAND flash memory and DRAM, it is more necessary to use the width of the spacer to define the minimum lithography size. However, for the double gap process, the standard type of overlap mark can only leave a slight pattern after the lithography process, and the pattern density and intensity of the micro pattern are very low, and In the subsequent planarization process, the insulating layer on the open area left around the mark tends to cause a dishing effect to cause damage to the overlap mark.

The invention provides a stacking mark and a manufacturing method thereof, which can improve the double room The pattern density and intensity of the micropatterns in the gap process, thereby improving the damage of the overlay marks caused by the pitting effect in the subsequent planarization process.

The present invention provides a stacked pair of indicia comprising a core indicia pattern and at least one protective pattern. The core marking pattern has a plurality of protrusions, and the first two protrusions have a first trench therebetween. The protection pattern is located around the core marking pattern, and there is at least one second trench between the protection pattern and the core pattern.

According to an embodiment of the present invention, in the above-mentioned overlapping mark, the width of the second trench is, for example, 75 times to 227 times or less than 5 μm of the width of the first trench.

According to an embodiment of the present invention, in the above-mentioned overlapping mark, the width of the protection pattern may be larger than the width of each of the protrusions.

According to an embodiment of the present invention, in the above-described overlapping mark, the width of the protection pattern is, for example, 400 to 818 times the width of each of the protrusions.

According to an embodiment of the present invention, in the above-mentioned overlapping mark, the protection pattern and the core mark pattern are, for example, located in the substrate, in the conductor layer, or in the multilayer structure.

According to an embodiment of the invention, the overlapping mark further comprises a filling layer, for example, filled in the first trench and in the second trench.

According to an embodiment of the present invention, in the above-mentioned overlapping mark, the protection pattern includes a first protection pattern portion and a second protection pattern portion, and the outlines of the first protection pattern portion and the second protection pattern portion are, for example, a frame shape. And the first protection pattern The portion may be disposed outside of the second protection pattern portion. The outline of the core mark pattern is, for example, a frame shape, and the core mark map may be disposed between the first protection pattern portion and the second protection pattern portion.

According to an embodiment of the present invention, in the above-mentioned overlapping mark, the outline of the core mark pattern and the protection pattern is, for example, a frame shape, and the core mark pattern may be disposed within the protection pattern.

According to an embodiment of the present invention, in the above-described overlapping mark, the protection pattern includes a plurality of protection pattern portions, and the plurality of protection pattern portions may be disposed around the core mark pattern.

According to an embodiment of the present invention, in the above-mentioned overlapping mark, the core mark pattern includes a plurality of core mark pattern portions, and a plurality of core mark pattern portions may be disposed around the protection pattern.

The present invention provides a method of manufacturing a stacked pair of marks comprising the following steps. A material layer is provided, the material layer including a memory cell region, a peripheral circuit region, and a stacked pair of marking regions, wherein the overlapping pair of marking regions includes a core marking pattern region and a protective pattern region. A plurality of sacrificial patterns are formed on the material layers of the memory cell region and the core mark pattern region. A plurality of spacers are formed on the sidewalls of the sacrificial patterns. Remove the sacrificial pattern. A sacrificial layer and a patterned mask layer are formed on the material layer, and the patterned mask layer covers at least a portion of the material layer of the protection pattern region and a portion of the material layer on the peripheral circuit region. Forming a layer of material with a patterned mask layer and a spacer as a mask to form a core marking pattern in the core marking pattern region and forming at least one protective pattern in the protective pattern region, wherein a plurality of protrusions in the core marking pattern a first trench between two adjacent protrusions, And a second trench is formed between the protection pattern and the core mark pattern.

According to an embodiment of the present invention, in the method for manufacturing a stacked mark, the patterned mask layer and the spacer are used as a mask, and the patterned material layer further includes the following steps. A plurality of third trenches may be formed in the memory cell region and a plurality of fourth trenches may be formed in the peripheral circuit region.

According to an embodiment of the invention, the method for manufacturing the overlay mark further includes the following steps. A filling layer is formed on the material layer, and the filling layer can fill the first trench, the second trench, the third trench, and the fourth trench.

According to an embodiment of the present invention, in the method of fabricating the stacked mark, the step of forming the filling layer includes a planarization process, and the planarization process may include a chemical mechanical polishing method or an etch back method.

According to an embodiment of the present invention, in the method for fabricating the stacked mark, the filling layer includes an insulating layer, and each of the filling layers formed in the third trench and the fourth trench may be respectively used as an isolation structure.

According to an embodiment of the present invention, in the method of manufacturing the stacked mark, the width of the second trench is, for example, 75 times to 227 times or less than 5 μm of the first trench.

According to an embodiment of the present invention, in the above method of manufacturing the stacked mark, the width of the protective pattern is, for example, greater than the width of each of the protrusions.

According to an embodiment of the present invention, in the above method of manufacturing the stacked mark, the width of the protective pattern is, for example, 400 to 818 times the width of each of the protrusions.

Fabrication of the above-described stacked mark in accordance with an embodiment of the present invention In the method, the material layer may comprise a substrate, a conductor layer or a multilayer structure.

Based on the above, in the overlay mark produced by the manufacturing method of the present invention, since a protective pattern having a large width is formed around the core mark pattern, it is possible to provide sufficient strength of the overlap mark in the subsequent planarization process. The result of preventing the damage of the overlay marks caused by the depression effect to smoothly perform the subsequent alignment process or measurement process.

The above described features and advantages of the invention will be apparent from the following description.

10, 70, 80, 90, 100 ‧ ‧ overlapping pairs of marks

11, 24‧‧‧ material layer

12, 72, 82, 92, 102‧‧‧ core marking patterns

14, 74, 84, 94, 104‧‧‧protective patterns

16‧‧‧Filling layer

18‧‧‧ protrusion

20‧‧‧First ditches

22‧‧‧Second ditches

26‧‧‧ memory area

28‧‧‧ peripheral circuit area

30‧‧‧Stacked marking area

32‧‧‧core marking pattern area

34‧‧‧protection pattern area

36, 37‧‧‧ Sacrifice pattern

38‧‧‧ spacer material layer

40‧‧‧ spacer

42‧‧‧sacrificial layer

43‧‧‧Anti-reflective layer

44‧‧‧ patterned mask layer

46‧‧‧pattern layer

48‧‧‧ Third Ditch

50‧‧‧fourth ditches

60‧‧‧矽Base

61‧‧‧Oxide layer

62‧‧‧Polysilicon layer

63‧‧‧矽 nitride layer

64‧‧‧hard mask layer

65‧‧‧Bottom anti-reflection layer

66‧‧‧carbon layer

67‧‧‧Nitrogen oxide layer

76,78,98‧‧‧protection pattern section

96, 106‧‧‧ core marking pattern section

D1, D2, D3, D4, D5, D6, D7, D8, D9, D10‧‧‧ width

1 is a schematic cross-sectional view of a stacked pair of marks in an embodiment of the present invention.

2A to 2G are cross-sectional views showing the flow of a method of manufacturing a stack of marks in an embodiment of the present invention.

3A to 3D are top views of overlapping pairs of marks according to an embodiment of the present invention, respectively.

1 is a schematic cross-sectional view of a stacked pair of marks in an embodiment of the present invention.

Referring to FIG. 1 , the overlapping mark 10 includes a core mark pattern 12 and a protection pattern 14 . The overlapping pairs of marks 10 are located in the material layer 11. The material layer 11 is, for example, a substrate, a conductor layer or an arbitrary multilayer structure. The above substrate is, for example, a germanium substrate and an insulator overlying 矽 substrate, or any other suitable substrate. The conductor layer is, for example, a polysilicon layer, a doped layer doped with an N-type dopant or a P-type dopant, a metal layer, or any other suitable conductor layer. In one embodiment, the material layer 11 is, for example, a multilayer structure including a ruthenium substrate 60, a ruthenium oxide layer 61, a polysilicon layer 62, and a tantalum nitride layer 63 in order from bottom to top.

The core marking pattern 12 has a plurality of projections 18 with a first trench 20 between each two adjacent projections 18. In the present embodiment, the width D10 of the protrusion 18 is approximately 22 nm to 40 nm, and the width D10 of the protrusion 18 represents a minute pattern size in the double spacer process. The width D1 of the first trench 20 is approximately 22 nm to 40 nm.

The protection pattern 14 is located around the core marking pattern 12, and there is a second trench 22 between the protection pattern 14 and the core pattern 12. In one embodiment, the width D9 of the protection pattern 14 is greater than the width D10 of the protrusion 18, and the width D9 of the protection pattern 14 is, for example, 16 μm to 18 μm, that is, the width D9 of the protection pattern 14 is, for example, the width D10 of the protrusion 18. 400 times to 818 times. Therefore, the protective pattern 14 is disposed in the overlap mark 10 such that the pattern density of the overlap mark 10 is increased from the original "protrusion 18" by the "protective pattern 14". The width D2 of the second trench 22 is, for example, 3 μm to 5 μm, that is, the width D2 of the second trench 22 is, for example, 75 times to 227 times or less than 5 μm of the width D1 of the first trench 20. When the width D2 of the second trench 22 is smaller, the pattern density of the overlap mark 10 is larger, and thus the stress from the flattening process which can be supported is larger.

In the present embodiment, the overlapping mark 10 further includes a filling layer 16. Fill layer 16 is filled in the first trench 20 and the second trench 22 of the stacked pair of marks 10 and subjected to a planarization process. However, the invention is not limited thereto, and in another embodiment, the filling layer 16 may cover the surface of the material layer 11. The material of the filling layer 16 is, for example, cerium oxide, polycrystalline germanium or other suitable insulating material, and the filling layer 16 is formed by a chemical vapor deposition method or a physical vapor deposition method, for example.

Since the protective pattern 14 is disposed in the stacked pair of marks 10, the pattern density of the stacked pairs of marks 10 is increased, so that more protruding portions in the planarization process for forming the filled layer 16 can support stress from the planarization process, providing sufficient The strength and prevent the occurrence of dent effects. Therefore, the arrangement of the protection pattern 14 can reduce the damage of the overlapping marks caused by the recession effect in the planarization process, so as to smoothly perform the alignment process or the measurement process of the subsequent film layer.

Based on the above embodiments, it can be known that the protection pattern is disposed in the overlapping mark pattern, and the pattern can be provided with sufficient strength in the planarization process to prevent damage of the overlapping marks caused by the concave effect, thereby increasing the overlapping pattern on the flat The reliability of the process is to smoothly carry out the subsequent alignment process or measurement process of the film.

2A-2G are cross-sectional views showing the flow of a method of fabricating a stack of marks in accordance with an embodiment of the present invention.

Referring to FIG. 2A, first, a material layer 24 is provided. The material layer 24 includes a memory cell region 26, a peripheral circuit region 28, and a stacked pair of marking regions 30. The stacked pair of marking regions 30 includes a core marking pattern region 32 and a protective pattern region 34. The material layer 24 is, for example, a substrate, a conductor layer or an arbitrary multilayer structure. The substrate is, for example, a germanium substrate, an insulator overlying substrate, or any other suitable substrate. The above conductor layer is, for example, A germanium layer, a doped layer doped with an N-type dopant or a P-type dopant, a metal layer, or any other suitable conductor layer. In one embodiment, the material layer 24 is, for example, a multilayer structure including a ruthenium substrate 60, a ruthenium oxide layer 61, a polysilicon layer 62, and a tantalum nitride layer 63 in order from bottom to top. Next, a hard mask layer 64 is formed on the material layer 24. The material of the hard mask layer 64 is, for example, tetraethoxy decane (TEOS). Thereafter, a bottom anti-reflection layer 65, a carbon layer 66, and a hafnium oxynitride layer 67 are formed on the hard mask layer 64.

Next, referring to FIG. 2B, the carbon layer 66 of the memory cell region 26 and the core mark pattern region 32 and the yttrium oxynitride layer 67 are patterned to be on the material layer 24 of the memory cell region 26 and the core mark pattern region 32. A plurality of sacrificial patterns 36 and sacrificial patterns 37 are formed. Next, a spacer material layer 38 is formed, and the spacer material layer 38 covers the top surface and sidewalls of each of the sacrificial patterns 36 and the sacrificial patterns 37. The material of the spacer material layer 38 is, for example, tantalum oxide or tantalum nitride, and the formation method of the spacer material layer 38 is, for example, a chemical vapor deposition method.

Referring to FIG. 2C, an anisotropic etching process is performed to remove a portion of the spacer material layer 38 and the sacrificial pattern 37 to form a plurality of spacers 40 on the sidewalls of the sacrificial pattern 36 while exposing a portion of the bottom anti-reflection. Layer 65.

Next, please refer to FIG. 2D, after which the sacrificial pattern 36 is removed. The method of removing the sacrificial pattern 36 may be performed by an etching process such as an isotropic etching process. Thereafter, a sacrificial layer 42, an anti-reflection layer 43, and a patterned mask layer 44 are sequentially formed on the bottom anti-reflection layer 65. The material of the sacrificial layer 42 is, for example, carbon, photoresist or other suitable material. The patterned mask layer 44 is, for example, a patterned photoresist layer. The patterned mask layer 44 covers not only the portion of the sacrificial layer 42 in the peripheral circuit region 28, but also the protective pattern. A portion of the sacrificial layer 42 on the region 34, and the core mark pattern region 32 and the sacrificial layer 42 on the spacers 40 in the memory cell region 26 are exposed. In other words, the present invention can perform a photolithography process on the photoresist layer (not shown) of the protection pattern region 34 and the peripheral circuit region 28 by using the same mask, so that no additional photoresist layer is needed to form the protection pattern region 34. The mask layer 44 is patterned.

Referring to FIG. 2E, the sacrificial layer 42 and the anti-reflective layer 43 are etched by patterning the mask layer 44 as a mask. When the spacer 40 is exposed, the peripheral circuit region 28 and the protection pattern region 34 continue to mask the mask layer 44, while the core mark pattern region 32 and the memory cell region 26 are shielded by the spacers 40, The bottom anti-reflective layer 65 is patterned, such as a lithography and etching process, to pattern the bottom anti-reflective layer 65 into a patterned layer 46. Thereafter, the patterned mask layer 44, the anti-reflective layer 43, and the sacrificial layer 42 are removed.

Next, referring to FIG. 2F, the pattern layer 46 is used as a mask to pattern the hard mask layer 64, and then the patterned hard mask layer 64 is used as a mask to pattern the material layer 24, for example, A lithography and etching process to form the core mark pattern 12 in the core mark pattern region 32 and form the protection pattern 14 in the protective pattern region 34 while forming the first trench 20 and the second trench 22 in the overlap mark region 30. A third trench 48 is formed in the memory cell region 26, and a fourth trench 50 is formed in the peripheral circuit region 28.

Referring again to FIG. 2F, the core marking pattern 12 has a plurality of projections 18 with a first trench 20 between the two adjacent projections 18. A second trench 22 is defined between the protective pattern 14 and the core marking pattern 12. The width D9 of the protection pattern 14 can be greater than The width D10 of each protrusion 18, and the width D9 of the protection pattern 14 may be 400 times to 818 times the width D10 of the protrusion 18, so in the subsequent planarization process, the protection pattern 14 can provide the protrusion 18 sufficiently large Strength to prevent damage to the overlay marks caused by the sag effect. Further, the width D2 of the second trench 22 is, for example, 75 times to 227 times or less than 5 μm of the width D1 of the first trench 20 to increase the pattern density of the overlapping marks.

Next, referring to FIG. 2G, an insulating layer (for example, a polysilicon layer or a hafnium oxide layer) is formed on the patterned hard mask layer 64 by chemical oxygen phase deposition, and then the tantalum nitride layer 63 is used as a polishing stop layer. The insulating layer is subjected to a planarization process such as a chemical mechanical polishing method or an etch back method to form the filling layer 16. The filling layer 16 is filled in the first trench 20, the second trench 22, the third trench 42 and the fourth trench 50. The filling layers 16 formed in the third trench 42 and the fourth trench 50 respectively can be used as an isolation structure. Referring to FIG. 2B, since the present invention uses the same mask to form the sacrificial pattern 36 and the sacrificial pattern 37 in the memory cell region 26 and the core mark pattern region 32, and the same mask is used in the process of FIG. 2D. The patterned mask layer 44 in the peripheral circuit region 28 and the protection pattern region 34 is formed, so that the first trench 20, the second trench 24, the third trench 48, and the fourth trench 50 can be simultaneously formed without an additional mask. In other words, the embodiment method of the embodiment does not require an additional mask, and can simultaneously form the core mark pattern 12 in the core mark pattern area 32, the protection pattern 14 in the protection pattern area 32, and the memory cell area 26 and The isolation structure in the peripheral circuit area 28.

Based on the above embodiments, the process method of the embodiment can be combined with the process of the normal memory to form the overlay mark, and the created overlap mark can be further The patterning process provides sufficient strength to prevent damage to the overlay marks caused by the embossing effect. More specifically, the overlay marks manufactured in accordance with the present embodiment do not require an additional mask to protect the pattern, thereby improving the reliability of the overlay pair marks during the planarization process.

3A to 3D are respectively top views of overlapping pairs of marks according to an embodiment of the present invention, but the present invention is not limited thereto.

3A is a top view of an overlay mark in accordance with an embodiment of the present invention. Referring to FIG. 3A, the overlapping pattern 70 is, for example, a stacked pattern of a box in box type. The overlay pattern 70 includes a protection pattern 74 and a core marking pattern 72. The width D3 of the stacked pair pattern 70 is, for example, about 40 μm to 50 μm. The protection pattern 74 includes a first protection pattern portion 76 and a second protection pattern portion 78, wherein the contours of the first protection pattern portion 76 and the second protection pattern portion 78 are, for example, frame shapes, respectively. The width of the first protective pattern portion 76 is the width D3 of the overlapping pattern 70, and the width D8 of the frame side of the first protective pattern portion 76 is, for example, 6 μm to 13 μm. The width D4 of the second protection pattern portion 78 is, for example, about 15 μm to 17 μm. The second protection pattern portion 78 is disposed within the first protection pattern portion 76, and the width D5 of the distance between the first protection pattern portion 76 and the second protection pattern portion 78 is, for example, about 7 μm to 12 μm. The core mark pattern 72 is disposed between the first protection pattern portion 76 and the second protection pattern portion 78. The outline of the core mark pattern 72 is, for example, a frame shape, and the width D6 of the frame side of the frame shape is, for example, 3 μm to 5 μm. The width D7 of the core mark pattern 72 is, for example, 23 μm to 25 μm.

Figure 3B is a top plan view of an overlay mark in accordance with an embodiment of the present invention. Please refer to 3B, the overlay pattern 80 is, for example, a box-type mark pattern, and the overlay pattern 80 includes a core mark pattern 82 and a protection pattern 84. The width of the stacked pair pattern 80 is, for example, 40 μm to 50 μm. The outline of the protection pattern 84 is, for example, a frame shape. The core marking pattern 82 is disposed within the protective pattern 84. The outline of the core mark pattern 82 is, for example, a frame shape, and the width of the frame side of the protection pattern 84 is larger than the width of the frame side of the core mark pattern 82.

3C is a top view of an overlay mark in accordance with an embodiment of the present invention. Referring to FIG. 3C, the overlay pattern 90 is, for example, a mark pattern of the AIMS type. The overlay pattern 90 includes a core marking pattern 92 and a protective pattern 94, wherein the core marking pattern 92 includes a plurality of core marking pattern portions 96, and the protective pattern 94 includes a plurality of protective pattern portions 98. As shown in FIG. 3C, the outline of the plurality of core mark pattern portions 96 is, for example, an elongated shape, and a plurality of core mark pattern portions 96 are distributed at the corners of the overlap pattern 90. The outline of each of the protection pattern portions 98 is, for example, a square shape, and each of the protection pattern portions 98 is disposed around the core mark pattern 92 constituted by the plurality of core mark pattern portions 96. The width of the protective pattern portion 98 is greater than the width of the core marking pattern portion 96.

3D is a top view of an overlay mark in accordance with an embodiment of the present invention. Referring to FIG. 3D, the marking pattern 100 is, for example, an AIMS type marking pattern. The overlay pattern 100 includes a core marking pattern 102 and a protective pattern 104, the core marking pattern 102 includes a plurality of core marking pattern portions 106, and the protective pattern 104 is disposed between the plurality of core marking pattern portions 106. As shown in FIG. 3D, the outline of each core mark pattern portion 106 is, for example, an elongated shape, and each core mark pattern portion 106 is disposed at the edge of the mark pattern 100. The outline of the protection pattern 104 is, for example, a cross-shaped square shape and is provided Mark the center of the pattern.

In summary, the overlapping marks proposed by the above embodiments of the present invention include a protection pattern located around the core marking pattern, so that sufficient pattern density and strength of the overlapping marks can be provided in the planarization process to prevent the concave effect from overlapping. The damage caused by the mark increases the reliability of the overlap mark in the flattening process. In addition, the overlapping marks of the above embodiments can be formed by changing and designing the reticle to match the process of the existing memory, so that the fabricated overlapping marks can be formed in the overlapping marks without an additional reticle. Protection pattern.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Overlap mark

11‧‧‧Material layer

12‧‧‧ core mark pattern

14‧‧‧Protection pattern

16‧‧‧Filling layer

18‧‧‧ protrusion

20‧‧‧First ditches

22‧‧‧Second ditches

60‧‧‧矽Base

61‧‧‧Oxide layer

62‧‧‧Polysilicon layer

63‧‧‧矽 nitride layer

D1, D2, D9, D10‧‧‧ width

Claims (19)

A stacked pair mark comprising: a core mark pattern having a plurality of protrusions in the core mark pattern, a first groove between two adjacent protrusions; and at least one protection pattern located around the core mark pattern The protective pattern and the core patterns have at least one second trench therebetween. The overlapping mark according to claim 1, wherein the width of the second trench is 75 times to 227 times or less than 5 μm of the width of the first trench. The overlay mark according to claim 1, wherein the width of the protection pattern is greater than the width of each of the protrusions. The overlapping mark according to claim 3, wherein the width of the protective pattern is 400 to 818 times the width of each of the protrusions. The overlay mark according to claim 1, wherein the overlap mark is located in a substrate, in a conductor layer, or in a multilayer structure. The overlay mark according to claim 1 further includes a filling layer filled in the first trenches and among the second trenches. The overlay mark according to claim 1, wherein the protection pattern comprises a first protection pattern portion and a second protection pattern portion, and the contours of the first protection pattern portion and the second protection pattern portion are frame-shaped And the first protection pattern portion is disposed outside the second protection pattern portion; and the outline of the core mark pattern is a frame shape, and the core mark pattern is disposed in the first protection pattern portion and the second protection pattern portion between. The overlay mark according to claim 1, wherein the core mark pattern and the outline of the protection pattern are frame-shaped, and the core mark pattern is disposed within the protection pattern. The overlay mark according to claim 1, wherein the protection pattern includes a plurality of protection pattern portions, and the protection pattern portions are disposed around the core mark pattern. The overlay mark according to claim 1, wherein the core mark pattern includes a plurality of core mark pattern portions, and the core mark pattern portions are disposed around the protection pattern. A method of fabricating a stack of marks, comprising: providing a material layer, the material layer comprising a memory cell region, a peripheral circuit region, and a stack of mark regions, wherein the stack of mark regions includes a core mark pattern region and a protection a pattern region; forming a plurality of sacrificial patterns on the material layer of the memory cell region and the core mark pattern region; forming a plurality of spacers on sidewalls of the sacrificial patterns; removing the sacrificial pattern; forming a sacrifice on the material layer a layer and a patterned mask layer covering at least a portion of the material layer of the protective pattern region and a portion of the material layer on the peripheral circuit region; and the patterned mask layer and the The spacers are masks, and the material layer is patterned to form a core mark pattern in the core mark pattern area and in the protection map Forming at least one protection pattern in the case, wherein a plurality of protrusions in the core mark pattern, a first trench between two adjacent protrusions, and a first between the protection pattern and the core mark pattern Two ditches. The method for manufacturing a stacked mark according to claim 11, wherein the patterning mask layer and the spacers are masks, and the step of patterning the material layer further comprises: forming in the memory cell region. A plurality of third trenches and a plurality of fourth trenches are formed in the peripheral circuit region. The method for manufacturing the stacked mark according to claim 12, further comprising: forming a filling layer on the material layer, the filling layer filling the first trenches, the second trenches, and the third Ditch and the fourth ditch. The method of manufacturing the stacked mark according to claim 13, wherein the step of forming the filling layer comprises a planarization process, and the planarization process comprises a chemical mechanical polishing method or an etch back method. The method of manufacturing the stacked mark according to claim 13, wherein the filling layer comprises an insulating layer, and each of the filling layers formed in the third trench and the fourth trench is respectively used as an isolation structure. The method of manufacturing the stacked mark according to claim 11, wherein the width of the second trench is 75 times to 227 times or less than 5 μm of the width of the first trench. The method of manufacturing the stacked mark according to claim 11, wherein the width of the protective pattern is larger than the width of each of the protrusions. The method of manufacturing the stacked mark according to claim 11, wherein the width of the protective pattern is 400 to 818 times the width of each of the protrusions. The method of manufacturing a stacked mark according to claim 11, wherein the material layer comprises a substrate, a conductor layer or a multilayer structure.