TWI525806B - Semiconductor structure and manufacturing method of the same - Google Patents

Semiconductor structure and manufacturing method of the same Download PDF

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TWI525806B
TWI525806B TW103100913A TW103100913A TWI525806B TW I525806 B TWI525806 B TW I525806B TW 103100913 A TW103100913 A TW 103100913A TW 103100913 A TW103100913 A TW 103100913A TW I525806 B TWI525806 B TW I525806B
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strip
conductive
stacked structure
strips
shaped stacked
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TW103100913A
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TW201528493A (en
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賴二琨
李冠儒
魏安祺
呂函庭
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旺宏電子股份有限公司
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Description

半導體結構及其製造方法Semiconductor structure and method of manufacturing same

本揭露內容是有關於一種半導體結構及其製造方法,且特別是有關於一種具有穩定的條狀堆疊結構之半導體結構及其製造方法。 The present disclosure relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a stable strip-like stacked structure and a method of fabricating the same.

近年來半導體元件的結構不斷地改變,且元件的記憶體儲存容量也不斷增加。記憶裝置係使用於許多產品之中,例如MP3播放器、數位相機、電腦檔案等等之儲存元件中。隨著應用的增加,對於記憶裝置的需求也趨向較小的尺寸、較大的記憶容量。因應這種需求,係需要製造高元件密度及具有小尺寸的記憶裝置。 In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density and a small size.

因此,設計者們無不致力於開發一種三維記憶裝置,不但具有許多堆疊平面而達到更高的記憶儲存容量,具有更微小的尺寸,同時具備良好之特性與穩定性。 Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has good characteristics and stability.

本揭露內容係有關於一種半導體結構及其製造方法。實施例中,半導體結構的伸張性材料條形成於條狀堆疊結構上,使得條狀堆疊結構的壓應力可以經由伸張性材料條的拉應力獲得適當補償,如此一來,可降低條狀堆疊結構彎曲(bending)的情形,進而提高半導體結構的穩定度及可靠性。 The disclosure relates to a semiconductor structure and a method of fabricating the same. In an embodiment, the strip of stretch material of the semiconductor structure is formed on the strip stack structure, so that the compressive stress of the strip stack structure can be appropriately compensated by the tensile stress of the strip of stretch material, so that the strip stack structure can be reduced. In the case of bending, the stability and reliability of the semiconductor structure are improved.

根據本揭露內容之一實施例,係提出一種半導體結構。半導體結構包括一基板、一條狀堆疊結構以及一伸張性材料條(tensile material strip)。條狀堆疊結構垂直形成於基板上,條狀堆疊結構具有壓應力(compressive stress)。條狀堆疊結構包括複數個導電條及複數個絕緣條,導電條與絕緣條係交錯設置(interlaced)。伸張性材料條形成於條狀堆疊結構上,伸張性材料條具有拉應力(tensile stress)。 In accordance with an embodiment of the present disclosure, a semiconductor structure is proposed. The semiconductor structure includes a substrate, a strip-like stacked structure, and a tensile material strip. The strip-like stacked structure is formed vertically on the substrate, and the strip-shaped stacked structure has compressive stress. The strip-shaped stacked structure includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The strip of stretch material is formed on the strip stack structure, and the strip of stretch material has tensile stress.

根據本揭露內容之另一實施例,係提出一種半導體結構的製造方法。半導體結構的製造方法包括以下步驟。提供一基板;垂直形成一條狀堆疊結構於基板上,條狀堆疊結構具有壓應力;以及形成一伸張性材料條於條狀堆疊結構上,伸張性材料條具有拉應力。條狀堆疊結構包括複數個導電條及複數個絕緣條,導電條與絕緣條係交錯設置。 In accordance with another embodiment of the present disclosure, a method of fabricating a semiconductor structure is presented. The method of fabricating a semiconductor structure includes the following steps. Providing a substrate; vertically forming a strip-like stacked structure on the substrate, the strip-shaped stacked structure has compressive stress; and forming a strip of stretchable material on the strip-shaped stacked structure, the strip of the stretchable material having tensile stress. The strip-shaped stacked structure includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are alternately arranged.

為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下: In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

110‧‧‧基板 110‧‧‧Substrate

120‧‧‧條狀堆疊結構 120‧‧‧ strip stack structure

120a‧‧‧表面 120a‧‧‧Surface

120s、130s‧‧‧側邊 120s, 130s‧‧‧ side

120t、130t‧‧‧厚度 120t, 130t‧‧‧ thickness

121‧‧‧導電條 121‧‧‧ Conductive strip

121a‧‧‧導電層 121a‧‧‧ Conductive layer

123‧‧‧絕緣條 123‧‧‧Insulation strip

123a‧‧‧絕緣層 123a‧‧‧Insulation

130‧‧‧伸張性材料條 130‧‧‧Extension strips

130a‧‧‧伸張性材料層 130a‧‧‧Stretchable material layer

140‧‧‧底氧化層 140‧‧‧ bottom oxide layer

140a‧‧‧底氧化材料層 140a‧‧‧Bottom oxidized material layer

150‧‧‧蓋氧化層 150‧‧‧ cover oxide layer

160‧‧‧介電元件 160‧‧‧Dielectric components

170‧‧‧導電線 170‧‧‧Flexible wire

170a‧‧‧導電材料層 170a‧‧‧layer of conductive material

A‧‧‧區域 A‧‧‧ area

D1、D2‧‧‧方向 D1, D2‧‧‧ direction

L1、L2‧‧‧長度 L1, L2‧‧‧ length

PR1、PR2‧‧‧圖案化光阻 PR1, PR2‧‧‧ patterned photoresist

T‧‧‧拉應力 T‧‧‧ tensile stress

W1、W2‧‧‧寬度 W1, W2‧‧‧ width

第1圖繪示本揭露內容之一實施例之半導體結構之立體示意 圖。 1 is a perspective view of a semiconductor structure of an embodiment of the present disclosure. Figure.

第2圖~第8圖繪示依照本發明之一實施例之一種半導體結構之製造方法示意圖。 2 to 8 are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

第9A圖及第9B圖分別繪示根據本揭露內容之實施例及比較例的半導體結構之掃描式電子顯微圖(SEM)之示意圖。 9A and 9B are schematic views respectively showing a scanning electron micrograph (SEM) of a semiconductor structure according to an embodiment of the present disclosure and a comparative example.

在此揭露內容之實施例中,係提出一種半導體結構及其製造方法。實施例中,半導體結構的伸張性材料條形成於條狀堆疊結構上,使得條狀堆疊結構的壓應力可以經由伸張性材料條的拉應力獲得適當補償,如此一來,可降低條狀堆疊結構彎曲(bending)的情形,進而提高半導體結構的穩定度及可靠性。然而,實施例僅用以作為範例說明,並不會限縮本發明欲保護之範圍。此外,實施例中之圖式係省略部份要之元件,以清楚顯示本發明之技術特點。 In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. In an embodiment, the strip of stretch material of the semiconductor structure is formed on the strip stack structure, so that the compressive stress of the strip stack structure can be appropriately compensated by the tensile stress of the strip of stretch material, so that the strip stack structure can be reduced. In the case of bending, the stability and reliability of the semiconductor structure are improved. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

請參照第1圖,其繪示本揭露內容之一實施例之半導體結構100之立體示意圖。半導體結構100包括一基板110、一條狀堆疊結構120以及一伸張性材料條130。如第1圖所示,條狀堆疊結構120垂直形成於基板110上,條狀堆疊結構120具有壓應力(compressive stress)。條狀堆疊結構120包括複數個導電條121及複數個絕緣條123,導電條121與絕緣條123係交錯設置(interlaced)。伸張性材料條130形成於條狀堆疊結構120上,伸張性材料條130具有拉應力(tensile stress)。根據本揭露內容之實施例,伸張性材料條130形成於條狀堆疊結構120上,如此一 來,條狀堆疊結構120的壓應力可以經由伸張性材料條130的拉應力獲得適當補償,可以減少條狀堆疊結構120朝向寬度方向彎曲(bending)的程度,進而提高條狀堆疊結構120的結構穩定度,降低條狀堆疊結構120與鄰近元件發生不當接觸的機率,並提高半導體結構100作為元件的可靠性。 Please refer to FIG. 1 , which is a perspective view of a semiconductor structure 100 in accordance with an embodiment of the present disclosure. The semiconductor structure 100 includes a substrate 110, a strip-like stacked structure 120, and a strip of extensible material 130. As shown in FIG. 1, the strip-like stacked structure 120 is vertically formed on the substrate 110, and the strip-shaped stacked structure 120 has compressive stress. The strip-shaped stacked structure 120 includes a plurality of conductive strips 121 and a plurality of insulating strips 123. The conductive strips 121 and the insulating strips 123 are interlaced. A strip of extensible material 130 is formed on the strip stack structure 120, and the strip of extensible material 130 has tensile stress. According to an embodiment of the present disclosure, the strip of extensible material 130 is formed on the strip stack structure 120, such that The compressive stress of the strip-shaped stacked structure 120 can be appropriately compensated by the tensile stress of the strip of tensile material 130, and the degree of bending of the strip-shaped stacked structure 120 toward the width direction can be reduced, thereby improving the structure of the strip-shaped stacked structure 120. The stability reduces the probability of improper contact of the strip stack structure 120 with adjacent components and improves the reliability of the semiconductor structure 100 as an component.

如第1圖所示(請同時參考第5圖),一實施例中,條狀堆疊結構120的長寬比大約為5~200;另一實施例中,條狀堆疊結構120的長寬比大約為15~50。舉例而言,當條狀堆疊結構120的寬度W1例如是40奈米,則條狀堆疊結構120的長度L1例如是800~1200奈米。實施例中,導電條121包括多晶矽,絕緣條123包括氧化矽,兩者皆具有壓應力。 As shown in FIG. 1 (please refer to FIG. 5 at the same time), in an embodiment, the strip-shaped stacked structure 120 has an aspect ratio of about 5 to 200; in another embodiment, the aspect ratio of the strip-shaped stacked structure 120 It is about 15~50. For example, when the width W1 of the strip-shaped stacked structure 120 is, for example, 40 nm, the length L1 of the strip-shaped stacked structure 120 is, for example, 800 to 1200 nm. In the embodiment, the conductive strip 121 comprises polysilicon, and the insulating strip 123 comprises yttrium oxide, both of which have compressive stress.

於一些實施例中,條狀堆疊結構120例如可以包括大約8~12對導電條121及絕緣條123,各個導電條121和各個絕緣條的厚度大約為300埃(Å)。本實施例中,如第1圖所示,條狀堆疊結構120包括交錯設置的8個導電條121及8個絕緣條123,條狀堆疊結構120的厚度120t大約為4800埃。然而,導電條121及絕緣條123的數量及厚度可以依照實際應用做適當選擇,並不以前述數量及厚度為限。 In some embodiments, the strip stack structure 120 may include, for example, about 8 to 12 pairs of conductive strips 121 and insulating strips 123, each of the strips 131 and each of the strips having a thickness of about 300 angstroms (Å). In this embodiment, as shown in FIG. 1, the strip-shaped stacked structure 120 includes eight conductive strips 121 and eight insulating strips 123 which are staggered, and the strip-shaped stacked structure 120 has a thickness of 120t of about 4800 angstroms. However, the number and thickness of the conductive strips 121 and the insulating strips 123 can be appropriately selected according to practical applications, and are not limited to the foregoing amounts and thicknesses.

於一些實施例中,條狀堆疊結構120例如更可包括一底氧化層140以及一蓋氧化層150。底氧化層140位於最下層的導電條121與基板110之間,蓋氧化層150位於伸張性材料條130之下。本實施例中,底氧化層140以及蓋氧化層150例如是由氧化矽所製成。實施例中,底氧化層140的厚度大約是500~2500埃(Å),根據條狀堆疊結構120中導電條121及絕緣條123的數量 不同而會有所不同。一實施例中,底氧化層140的厚度例如大約是1000埃。實施例中,蓋氧化層150的厚度大約是300~2000埃,根據條狀堆疊結構120中導電條121及絕緣條123的數量不同而會有所不同。一實施例中,蓋氧化層150的厚度例如大約是1000埃。然而,底氧化層140及蓋氧化層150的材質及厚度可以依照實際應用做適當選擇,並不以前述材質及厚度為限。 In some embodiments, the strip stack structure 120 may further include a bottom oxide layer 140 and a cap oxide layer 150. The bottom oxide layer 140 is located between the lowermost conductive strip 121 and the substrate 110, and the cap oxide layer 150 is located under the strip of extensible material 130. In the present embodiment, the bottom oxide layer 140 and the cap oxide layer 150 are made of, for example, hafnium oxide. In the embodiment, the thickness of the bottom oxide layer 140 is about 500 to 2500 angstroms (Å), according to the number of the conductive strips 121 and the insulating strips 123 in the strip-shaped stacked structure 120. It will be different. In one embodiment, the thickness of the bottom oxide layer 140 is, for example, about 1000 angstroms. In the embodiment, the thickness of the cap oxide layer 150 is about 300-2000 angstroms, which varies according to the number of the conductive strips 121 and the insulating strips 123 in the strip-shaped stacked structure 120. In one embodiment, the thickness of the cap oxide layer 150 is, for example, about 1000 angstroms. However, the material and thickness of the bottom oxide layer 140 and the cap oxide layer 150 may be appropriately selected according to practical applications, and are not limited to the above materials and thicknesses.

實施例中,如第1圖所示,伸張性材料條130形成於條狀堆疊結構120的頂表面120a上。於一些實施例中,伸張性材料條130包括介電材料,例如包括氮化矽層或碳化矽層。一實施例中,伸張性材料條130的厚度例如是100~1000埃;另一實施例中,伸張性材料條130的厚度例如是200~500埃(Å);根據條狀堆疊結構120中導電條121及絕緣條123的數量不同而會有所不同。 In an embodiment, as shown in FIG. 1, a strip of extensible material 130 is formed on the top surface 120a of the strip stack 120. In some embodiments, the strip of extensible material 130 comprises a dielectric material, for example comprising a tantalum nitride layer or a tantalum carbide layer. In one embodiment, the thickness of the strip of extensible material 130 is, for example, 100 to 1000 angstroms; in another embodiment, the thickness of the strip of extensible material 130 is, for example, 200 to 500 angstroms (Å); conductive according to the strip-shaped stacked structure 120 The number of strips 121 and the strips 123 may vary.

於一些實施例中,伸張性材料條130的厚度130t相對於條狀堆疊結構120的厚度120t之比例係為約1:5~1:100。換言之,當條狀堆疊結構120的厚度越大時,伸張性材料條130的厚度亦需相應增大,以對應提供足夠的應力補償。舉例而言,一實施例中,當伸張性材料條130的厚度約為500埃(Å),條狀堆疊結構120包括8對導電條121及絕緣條123而具有的厚度約為4800埃,底氧化層140的厚度約為500埃,蓋氧化層150的厚度約為500埃,則伸張性材料條130的厚度相對於條狀堆疊結構120的厚度之比例約為:500/(4800+500+500)=1:11。另一實施例中,當伸張性材料條130的厚度約為200埃(Å),條狀堆疊結構120包括12對導電條121及絕緣條123而具有的厚度約為7200埃, 底氧化層140的厚度約為1000埃,蓋氧化層150的厚度約為800埃,則伸張性材料條130的厚度相對於條狀堆疊結構120的厚度之比例約為:200/(7200+1000+800)=1:45。 In some embodiments, the ratio of the thickness 130t of the strip of extensible material 130 to the thickness 120t of the strip stack 120 is about 1:5 to 1:100. In other words, as the thickness of the strip-like stack 120 is greater, the thickness of the strip of extensible material 130 also needs to be increased to provide sufficient stress compensation. For example, in one embodiment, when the strip of extensible material 130 has a thickness of about 500 angstroms (Å), the strip-shaped stacked structure 120 includes eight pairs of conductive strips 121 and insulating strips 123 having a thickness of about 4,800 angstroms. The oxide layer 140 has a thickness of about 500 angstroms and the cap oxide layer 150 has a thickness of about 500 angstroms. The ratio of the thickness of the strip of stretchable material 130 to the thickness of the strip stack 120 is about 500/(4800+500+). 500) = 1:11. In another embodiment, when the strip of extensible material 130 has a thickness of about 200 angstroms (Å), the strip-shaped stacked structure 120 includes 12 pairs of conductive strips 121 and insulating strips 123 having a thickness of about 7,200 angstroms. The thickness of the bottom oxide layer 140 is about 1000 angstroms, and the thickness of the cap oxide layer 150 is about 800 angstroms. The ratio of the thickness of the strip of the stretch material strip 130 to the thickness of the strip stack structure 120 is about: 200/(7200+1000). +800) = 1:45.

一實施例中,如第1圖所示(請同時參考第5圖),伸張性材料條130的長度L2與條狀堆疊結構120的長度L1實質上係相同,伸張性材料條130的兩側邊130s與條狀堆疊結構120的兩側邊120s實質上係對齊。本實施例中,如第1圖所示,伸張性材料條130覆蓋條狀堆疊結構120的頂表面120a,並且伸張性材料條130的圖案與條狀堆疊結構120的圖案實質上係相同。 In one embodiment, as shown in FIG. 1 (please refer to FIG. 5 at the same time), the length L2 of the strip of stretch material 130 is substantially the same as the length L1 of the strip stack 120, and both sides of the strip of stretch material 130 The sides 130s are substantially aligned with the two sides 120s of the strip stack 120. In the present embodiment, as shown in FIG. 1, the strip of extensible material 130 covers the top surface 120a of the strip-shaped stacked structure 120, and the pattern of the strip of extensible material 130 is substantially the same as the pattern of the strip-like stacked structure 120.

如第1圖所示,半導體結構100更可包括一介電元件160和一導電線170。介電元件160形成於條狀堆疊結構120上,導電線170形成於介電元件160上。介電元件160可以是ONO結構、ONONO結構或由穿隧材料(tunneling material)/捕捉材料(trapping material)/阻擋材料(blocking material)構成的材料層,應用於反及閘(NAND)之儲存材料。導電線170的延伸方向D1係垂直於條狀堆疊結構120的延伸方向D2。一實施例中,半導體結構100例如是三維垂直閘極記憶裝置(3D vertical gate memory device),則導電線170係用作字元線,條狀堆疊結構120係用作位元線。另一實施例中,半導體結構100例如是具有超薄U形通道(ultra-thin U-shaped channels)的三維記憶裝置,導電線170可用作位元線,條狀堆疊結構120則用作字元線。 As shown in FIG. 1, the semiconductor structure 100 further includes a dielectric member 160 and a conductive line 170. The dielectric element 160 is formed on the strip stack structure 120, and the conductive line 170 is formed on the dielectric element 160. The dielectric element 160 may be an ONO structure, an ONONO structure, or a material layer composed of a tunneling material/trapping material/blocking material, and is applied to a NAND storage material. . The extending direction D1 of the conductive line 170 is perpendicular to the extending direction D2 of the strip-shaped stacked structure 120. In one embodiment, the semiconductor structure 100 is, for example, a 3D vertical gate memory device, and the conductive lines 170 are used as word lines, and the strip stacked structure 120 is used as bit lines. In another embodiment, the semiconductor structure 100 is, for example, a three-dimensional memory device having ultra-thin U-shaped channels, the conductive lines 170 can be used as bit lines, and the strip-shaped stacked structure 120 can be used as words. Yuan line.

第2圖~第8圖繪示依照本發明之一實施例之一種半導體結構之製造方法示意圖。 2 to 8 are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

請參照第2~5圖,提供基板110,垂直形成條狀堆 疊結構120於基板110上,以及形成伸張性材料條130於條狀堆疊結構120上。實施例中,條狀堆疊結構120和伸張性材料條130的製造方法例如包括以下步驟。 Please refer to Figures 2~5 to provide a substrate 110 which is vertically formed into a strip pile. The stacked structure 120 is on the substrate 110, and a strip of extensible material 130 is formed on the strip-like stacked structure 120. In the embodiment, the method of manufacturing the strip-shaped stacked structure 120 and the strip of stretchable material 130 includes, for example, the following steps.

如第2圖所示,形成複數個導電層121a及複數個絕緣層123a於基板110上,導電層121a與絕緣層123a係交錯設置。實施例中,如第2圖所示,在形成導電層121a及絕緣層123a之前,可選擇性地形成底氧化材料層140a於基板110上;以及在形成導電層121a及絕緣層123a之後,可選擇性地形成蓋氧化材料層150a於導電層121a及絕緣層123a之上。 As shown in FIG. 2, a plurality of conductive layers 121a and a plurality of insulating layers 123a are formed on the substrate 110, and the conductive layer 121a and the insulating layer 123a are alternately arranged. In the embodiment, as shown in FIG. 2, the bottom oxide material layer 140a may be selectively formed on the substrate 110 before the conductive layer 121a and the insulating layer 123a are formed; and after the conductive layer 121a and the insulating layer 123a are formed, A cap oxide material layer 150a is selectively formed over the conductive layer 121a and the insulating layer 123a.

接著,如第3圖所示,形成伸張性材料層130a於導電層121a及絕緣層123a之上。本實施例中,伸張性材料層130a例如是氮化矽層。實施例中,伸張性材料層130a可以是任何具有拉應力的介電材料層,例如是碳化矽層。一些實施例中,伸張性材料層130a例如是以低溫化學氣相沈積法或物理氣相沈積法形成。一實施例中,以物理氣相沈積法形成伸張性材料層130a時,經由沈積製程中的參數之調整,例如是氣體來源的比例等,可以調控伸張性材料層130a的拉應力。實施例中,伸張性材料層130a的厚度例如是100~1000埃。 Next, as shown in Fig. 3, a stretchable material layer 130a is formed over the conductive layer 121a and the insulating layer 123a. In the present embodiment, the stretchable material layer 130a is, for example, a tantalum nitride layer. In an embodiment, the layer of extensible material 130a can be any layer of dielectric material having tensile stress, such as a layer of tantalum carbide. In some embodiments, the layer of extensible material 130a is formed, for example, by low temperature chemical vapor deposition or physical vapor deposition. In one embodiment, when the stretchable material layer 130a is formed by physical vapor deposition, the tensile stress of the stretchable material layer 130a can be adjusted by adjusting the parameters in the deposition process, for example, the ratio of the gas source. In the embodiment, the thickness of the stretchable material layer 130a is, for example, 100 to 1000 angstroms.

接著,如第4圖所示,形成圖案化光阻PR1於導電層121a及絕緣層123a上,圖案化光阻PR1具有導電條121以及絕緣條123之預定圖案。也就是說,圖案化光阻PR1具有條狀堆疊結構120之預定圖案。 Next, as shown in FIG. 4, the patterned photoresist PR1 is formed on the conductive layer 121a and the insulating layer 123a, and the patterned photoresist PR1 has a predetermined pattern of the conductive strip 121 and the insulating strip 123. That is, the patterned photoresist PR1 has a predetermined pattern of the strip-like stacked structure 120.

接著,如第5圖所示,圖案化伸張性材料層130a以形成伸張性材料條130,以及圖案化導電層121a及絕緣層123a 以形成導電條121以及絕緣條123。實施例中,例如是根據圖案化光阻PR1(導電條121以及絕緣條123之預定圖案),蝕刻導電層121a及絕緣層123a以形成導電條121及絕緣條123,以及蝕刻伸張性材料層130a以形成伸張性材料條130。 Next, as shown in FIG. 5, the stretchable material layer 130a is patterned to form a strip of extensible material 130, and the patterned conductive layer 121a and the insulating layer 123a. The conductive strip 121 and the insulating strip 123 are formed. In the embodiment, for example, according to the patterned photoresist PR1 (the predetermined pattern of the conductive strip 121 and the insulating strip 123), the conductive layer 121a and the insulating layer 123a are etched to form the conductive strip 121 and the insulating strip 123, and the extensible material layer 130a is etched. To form a strip of extensible material 130.

一實施例中,條狀堆疊結構120及伸張性材料條130例如是於同一個製程中形成。本實施例中,如第2~5圖所示,圖案化伸張性材料層130a以及圖案化導電層121a和絕緣層123a例如是同時進行。 In one embodiment, the strip stack structure 120 and the strip of extensible material 130 are formed, for example, in the same process. In the present embodiment, as shown in FIGS. 2 to 5, the patterned stretchable material layer 130a and the patterned conductive layer 121a and the insulating layer 123a are simultaneously performed, for example.

請參照第6圖,形成介電元件160於條狀堆疊結構120上。實施例中,介電元件160可包括至少穿隧材料、捕捉材料及阻擋材料。舉例而言,介電元件160可具有多層結構,例如是ONO複合層或ONONO複合層或BE-SONOS複合層,或是包括例如由氧化矽與氮化矽交錯堆疊形成的ONO結構。 Referring to FIG. 6, a dielectric member 160 is formed on the strip stack structure 120. In an embodiment, the dielectric component 160 can include at least a tunneling material, a capture material, and a barrier material. For example, the dielectric component 160 can have a multilayer structure, such as an ONO composite layer or an ONONO composite layer or a BE-SONOS composite layer, or an ONO structure including, for example, a stack of yttrium oxide and tantalum nitride.

請參照第7~8圖,形成導電線170於介電元件160上。實施例中,導電線170的製造方法例如包括以下步驟。 Referring to FIGS. 7-8, a conductive line 170 is formed on the dielectric member 160. In the embodiment, the method of manufacturing the conductive line 170 includes, for example, the following steps.

如第7圖所示,形成導電材料層170a於介電元件160上。 As shown in FIG. 7, a conductive material layer 170a is formed on the dielectric member 160.

接著,如第8圖所示,圖案化導電材料層170a以形成導電線170,導電線170的延伸方向D1垂直於條狀堆疊結構120的延伸方向D2。實施例中,例如是根據圖案化光阻PR2蝕刻導電材料層170a以形成導電線170。本實施例中,伸張性材料條130例如是氮化矽層,如此一來,伸張性材料條130不僅可以提供應力舒緩,在導電材料層170a的蝕刻製程中,尚具有硬遮罩層的功效。 Next, as shown in FIG. 8, the conductive material layer 170a is patterned to form the conductive lines 170, and the extending direction D1 of the conductive lines 170 is perpendicular to the extending direction D2 of the strip-shaped stacked structure 120. In an embodiment, the conductive material layer 170a is etched, for example, according to the patterned photoresist PR2 to form the conductive lines 170. In this embodiment, the strip of extensible material 130 is, for example, a tantalum nitride layer. Thus, the strip of extensible material 130 can not only provide stress relaxation, but also has the effect of a hard mask layer in the etching process of the conductive material layer 170a. .

另一實施例中,亦可先形成絕緣層(未繪示)於介電元件160上,接著在絕緣層中形成至少一個溝槽,並將導電材料填入溝槽中以形成導電線170。本實施例中,伸張性材料條130例如是氮化矽層,在形成導電線170之前的絕緣層的平坦化製程中,伸張性材料條130亦具有硬遮罩層的功效。至此,形成於第8圖所示之半導體結構100。 In another embodiment, an insulating layer (not shown) may be formed on the dielectric member 160, then at least one trench is formed in the insulating layer, and a conductive material is filled into the trench to form the conductive line 170. In the present embodiment, the strip of extensible material 130 is, for example, a tantalum nitride layer. In the planarization process of the insulating layer before forming the conductive line 170, the strip of extensible material 130 also has the effect of a hard mask layer. Thus far, the semiconductor structure 100 shown in FIG. 8 is formed.

為讓本發明之上述內容能更明顯易懂,下文特舉實施例作詳細說明如下。以下係列出實施例與比較例之半導體結構的示意圖。然而以下之實施例為例示說明之用,而不應被解釋為本揭露內容實施之限制。 In order to make the above description of the present invention more apparent, the following specific embodiments are described in detail below. The following is a series of schematic diagrams of semiconductor structures of the examples and comparative examples. However, the following examples are for illustrative purposes and are not to be construed as limiting the implementation of the disclosure.

第9A圖及第9B圖分別繪示根據本揭露內容之實施例及比較例的半導體結構之掃描式電子顯微圖之示意圖,其中實施例之半導體結構中之條狀堆疊結構120包括複數對導電條121及絕緣條123,並且具有伸張性材料條130;比較例之半導體結構則僅具有條狀堆疊結構120,不具有伸張性材料條。實施例與比較例中的導電條121係為具有-200MPa的壓應力之多晶矽,絕緣條123係為具有-300MPa的壓應力之氧化矽,而實施例中的伸張性材料條130例如是具有1000MPa的拉應力之氮化矽。。 9A and 9B are schematic views respectively showing a scanning electron micrograph of a semiconductor structure according to an embodiment of the present disclosure and a comparative example, wherein the strip-shaped stacked structure 120 in the semiconductor structure of the embodiment includes a plurality of pairs of conductive The strip 121 and the insulating strip 123 have a strip of extensible material 130; the semiconductor structure of the comparative example has only a strip-like stacked structure 120 and does not have a strip of extensible material. The conductive strip 121 in the embodiment and the comparative example is a polycrystalline silicon having a compressive stress of -200 MPa, and the insulating strip 123 is a cerium oxide having a compressive stress of -300 MPa, and the strip of the stretching material 130 in the embodiment has, for example, 1000 MPa. The tensile stress of the tantalum nitride. .

如第9A圖及第9B圖所示,實施例之半導體結構的伸張性材料條130具有沿條狀堆疊結構120的長度方向往外拉伸的拉應力T,可有效地舒緩整體的應力,因此條狀堆疊結構120並未發生彎曲或變形。相對地,比較例之半導體結構不具有伸張性材料條,因此條狀堆疊結構120的壓應力無法獲得補償,如第9B圖中的區域A及卡通圖所示,條狀堆疊結構120發生彎曲變 形的情形,特別是朝向寬度方向,甚至使得鄰近的條狀堆疊結構120之間已發生不當接觸。 As shown in FIGS. 9A and 9B, the tensile material strip 130 of the semiconductor structure of the embodiment has a tensile stress T stretched outward in the longitudinal direction of the strip-shaped stacked structure 120, which can effectively relieve the overall stress, and thus the strip The stacked structure 120 does not bend or deform. In contrast, the semiconductor structure of the comparative example does not have a strip of extensible material, and therefore the compressive stress of the strip-shaped stacked structure 120 cannot be compensated. As shown in the area A and the cartoon figure in FIG. 9B, the strip-shaped stacked structure 120 is bent. The shape of the shape, particularly toward the width direction, even causes improper contact between the adjacent strip-like stack structures 120.

據此,根據本揭露內容之實施例,半導體結構中,伸張性材料條形成於條狀堆疊結構上,使得條狀堆疊結構的壓應力可以經由伸張性材料條的拉應力獲得適當補償,可以大幅降低條狀堆疊結構朝向寬度方向彎曲(bending)的情形,使條狀堆疊結構具有良好且直線形的位元線(或字元線)之外型結構,進而提高半導體結構的結構穩定度,並提高半導體結構作為元件的可靠性。 Accordingly, according to an embodiment of the present disclosure, in the semiconductor structure, the strip of stretch material is formed on the strip stack structure, so that the compressive stress of the strip stack structure can be appropriately compensated by the tensile stress of the strip of stretch material, which can be substantially Reducing the case where the strip-shaped stacked structure is bent toward the width direction, so that the strip-shaped stacked structure has a good and linear shape of the bit line (or word line), thereby improving the structural stability of the semiconductor structure, and Improve the reliability of semiconductor structures as components.

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

110‧‧‧基板 110‧‧‧Substrate

120‧‧‧條狀堆疊結構 120‧‧‧ strip stack structure

120a‧‧‧表面 120a‧‧‧Surface

120t、130t‧‧‧厚度 120t, 130t‧‧‧ thickness

121‧‧‧導電條 121‧‧‧ Conductive strip

123‧‧‧絕緣條 123‧‧‧Insulation strip

130‧‧‧伸張性材料條 130‧‧‧Extension strips

140‧‧‧底氧化層 140‧‧‧ bottom oxide layer

150‧‧‧蓋氧化層 150‧‧‧ cover oxide layer

160‧‧‧介電元件 160‧‧‧Dielectric components

170‧‧‧導電線 170‧‧‧Flexible wire

D1、D2‧‧‧方向 D1, D2‧‧‧ direction

Claims (8)

一種半導體結構,包括:一基板;一條狀堆疊結構,垂直形成於該基板上,該條狀堆疊結構具有壓應力(compressive stress),該條狀堆疊結構包括:複數個導電條;及複數個絕緣條,該些導電條與該些絕緣條係交錯設置(interlaced);以及一伸張性材料條(tensile material strip),形成於該條狀堆疊結構上,該伸張性材料條具有拉應力(tensile stress),其中該伸張性材料條的長度與該條狀堆疊結構的長度實質上係相同。 A semiconductor structure comprising: a substrate; a strip-like stacked structure vertically formed on the substrate, the strip-shaped stacked structure having compressive stress, the strip-shaped stacked structure comprising: a plurality of conductive strips; and a plurality of insulating layers Strips, the conductive strips are interlaced with the insulating strips; and a tensile material strip formed on the strip stack structure, the strip of tensile material having tensile stress And wherein the length of the strip of stretch material is substantially the same as the length of the strip stack. 如申請專利範圍第1項所述之半導體結構,其中該條狀堆疊結構具有一長寬比約為5~200。 The semiconductor structure of claim 1, wherein the strip-shaped stacked structure has an aspect ratio of about 5 to 200. 如申請專利範圍第1項所述之半導體結構,其中該伸張性材料條的兩側邊與該條狀堆疊結構的兩側邊實質上係對齊。 The semiconductor structure of claim 1, wherein the two sides of the strip of stretch material are substantially aligned with the sides of the strip stack. 如申請專利範圍第1項所述之半導體結構,更包括:一介電元件,形成於該條狀堆疊結構上;以及一導電線,形成於該介電元件上,該導電線的延伸方向係垂直於該條狀堆疊結構的延伸方向;其中該伸張性材料條包括氮化矽層或碳化矽層,該伸張性材料條的厚度相對於該條狀堆疊結構的厚度之比例係為約 1:5~1:100,該伸張性材料條的厚度係為100~1000埃(Å),該些導電條包括多晶矽,該些絕緣條包括氧化矽。 The semiconductor structure of claim 1, further comprising: a dielectric element formed on the strip-shaped stacked structure; and a conductive line formed on the dielectric element, the extending direction of the conductive line A direction perpendicular to the extending direction of the strip-shaped stacked structure; wherein the strip of stretchable material comprises a tantalum nitride layer or a tantalum carbide layer, and a ratio of a thickness of the strip of the stretchable material to a thickness of the strip-shaped stacked structure is about 1:5~1:100, the strip of the stretchable material has a thickness of 100~1000 angstroms (Å), and the conductive strips comprise polycrystalline germanium, and the insulating strips comprise yttrium oxide. 一種半導體結構之製造方法,包括:提供一基板;垂直形成一條狀堆疊結構於該基板上,該條狀堆疊結構具有壓應力,該條狀堆疊結構包括:複數個導電條;及複數個絕緣條,該些導電條與該些絕緣條係交錯設置;以及形成一伸張性材料條於該條狀堆疊結構上,該伸張性材料條具有拉應力,其中該條狀堆疊結構及該伸張性材料條係於同一個製程中形成。 A method for fabricating a semiconductor structure, comprising: providing a substrate; vertically forming a strip-shaped stacked structure on the substrate, the strip-shaped stacked structure having compressive stress, the strip-shaped stacked structure comprising: a plurality of conductive strips; and a plurality of insulating strips The conductive strips are staggered with the insulating strips; and a strip of stretchable material is formed on the strip-shaped stacked structure, the strip of stretchable material has tensile stress, wherein the strip-shaped stacked structure and the strip of stretchable material It is formed in the same process. 如申請專利範圍第5項所述之半導體結構之製造方法,其中形成該些導電條以及形成該些絕緣條之步驟包括:形成複數個導電層及複數個絕緣層,該些導電層與該些絕緣層係交錯設置;以及圖案化該些導電層及該些絕緣層以形成該些導電條以及該些絕緣條。 The manufacturing method of the semiconductor structure of claim 5, wherein the forming the conductive strips and forming the insulating strips comprises: forming a plurality of conductive layers and a plurality of insulating layers, the conductive layers and the conductive layers The insulating layers are staggered; and the conductive layers and the insulating layers are patterned to form the conductive strips and the insulating strips. 如申請專利範圍第6項所述之半導體結構之製造方法,其中形成該伸張性材料條之步驟包括:形成一伸張性材料層於該些導電層及該些絕緣層之上;以及 根據該些導電條以及該些絕緣條之一預定圖案,圖案化該伸張性材料層以形成該伸張性材料條。 The method of fabricating a semiconductor structure according to claim 6, wherein the step of forming the strip of extensible material comprises: forming a layer of a stretchable material over the conductive layer and the insulating layers; The layer of extensible material is patterned to form the strip of extensible material according to the conductive strips and a predetermined pattern of one of the insulating strips. 如申請專利範圍第7項所述之半導體結構之製造方法,更包括:形成一介電元件於該條狀堆疊結構上;以及形成一導電線於該介電元件上,該導電線的延伸方向係垂直於該條狀堆疊結構的延伸方向;其中係以物理氣相沈積法形成該伸張性材料條,該伸張性材料條的厚度相對於該條狀堆疊結構的厚度之比例係為約1:5~1:100,該伸張性材料條的厚度係為100~1000埃(Å),圖案化該伸張性材料層以及圖案化該些導電層及該些絕緣層係同時進行。 The manufacturing method of the semiconductor structure of claim 7, further comprising: forming a dielectric element on the strip-shaped stacked structure; and forming a conductive line on the dielectric element, the extending direction of the conductive line And extending perpendicular to the extending direction of the strip-shaped stacked structure; wherein the strip of stretchable material is formed by physical vapor deposition, and the ratio of the thickness of the strip of the stretchable material to the thickness of the strip-shaped stacked structure is about 1: 5~1:100, the thickness of the stretch strip is 100~1000 angstroms (Å), patterning the stretchable material layer and patterning the conductive layers and the insulating layers simultaneously.
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