TWI722816B - Three dimensional memory device - Google Patents

Abstract

A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure on a first region of a semiconductor substrate. The multi-layer stacked structure includes a stair structure and a non-stair structure. A plurality of memory structures are located in the non-stair structure to form a memory array region, and each memory structure passes through the conductive layers and the insulating layers. A plurality of bow-height adjustment features are located in a second region of the semiconductor substrate.

Description

Three-dimensional memory device

The present disclosure relates to a memory device and its manufacturing method, and more particularly to a three-dimensional memory device with high memory density and its manufacturing method.

Memory components are important data storage components in portable electronic devices, such as MP3 players, digital cameras, notebook computers, smart phones, etc. With the increase of various applications and the improvement of functions, the demand for memory components also tends to be smaller in size and larger in memory capacity. In response to this demand, current designers have turned to develop a three-dimensional memory device that includes a stack of multiple memory cells, such as a vertical-channel three-dimensional NAND flash memory device.

However, as the critical size of the device shrinks to the limit of the general memory cell technology, how to obtain a higher memory storage capacity in a smaller device size while also being able to adjust the wafer warpage height during the manufacturing process? It has become an important issue facing this technical field. Therefore, there is a need to provide an advanced three-dimensional memory device and a manufacturing method thereof to solve the problems faced by the conventional technology.

An embodiment of this specification discloses a three-dimensional memory device, which includes a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked to form a multi-layer stack structure in a first region of a semiconductor substrate. The multi-layer stack structure has a stepped structure and a non-stepped structure. A plurality of memory structures are located in a non-step structure to form a memory array area, and each memory structure passes through the conductive layers and the insulating layers. The plurality of warping height adjustment features are located in the second region of the semiconductor substrate.

In other embodiments of this specification, the warpage height adjustment features include polysilicon plugs.

In other embodiments of this specification, the warpage height adjustment features include polysilicon pads.

In other embodiments of this specification, the stepped structure is closer to the second region than the non-stepped structure.

In other embodiments of this specification, the warped height adjustment features occupy at least 10% of the area of the second zone.

In other embodiments of this specification, each memory structure includes a memory layer and a channel layer, and the warpage height adjustment features and the channel layer include the same material.

In other embodiments of this specification, the warpage height adjustment features are electrically insulated from each other.

In other embodiments of this specification, the warpage height adjustment features are electrically insulated from the memory structures.

In other embodiments of this specification, the warpage height adjustment features are located on the same side of the semiconductor substrate as the multilayer stack structure.

In other embodiments of this specification, a three-dimensional memory device includes a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked to form a multi-layer stack structure in a first region of a semiconductor substrate. The multi-layer stack structure has a stepped structure and a non-stepped structure. A plurality of memory structures are located in a non-step structure to form a memory array area, and each memory structure passes through the conductive layers and the insulating layers. The semiconductor substrate further includes a second region, wherein the first region and the second region are adjacent and located on the same side of the semiconductor substrate. The plurality of warpage height adjustment features are located in the third area of the semiconductor substrate, wherein the third area is located on the opposite side of the first area and the second area on the semiconductor substrate.

In summary, the three-dimensional semiconductor memory device is provided with a warpage height adjustment feature in the peripheral area to compensate for the height of the wafer level difference caused by the wafer warpage. The warpage height adjustment feature can be a polysilicon plug or a polysilicon pad, and can be located on the front side or the back side of the peripheral area of the semiconductor substrate (ie, the second region or the third region of the semiconductor substrate).

Hereinafter, the above description will be described in detail by way of implementation, and a further explanation will be provided for the technical solution of the present invention.

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the description of the attached symbols is as follows:

100: Semiconductor memory element

101: Substrate

103: District 1

107: Insulation layer

108: conductive layer

109: Insulation layer

110: Memory array area

112: Hole

114: Memory structure

114a: memory layer

114b: Channel layer

114c: oxide layer

115: protective layer

116: bottom anti-reflective coating

118: photoresist layer

118a: Through hole

118b: Through hole

120a: pad area

120b: Pad area

122: order

124: epitaxial silicon layer

130a: surrounding area

130b: Surrounding area

130c: surrounding area

150: Warp height adjustment feature

150a: hole

152: Warp height adjustment feature

In order to make the above and other objectives, features, advantages and embodiments of the present invention more comprehensible, the description of the accompanying drawings is as follows:

FIG. 1 is a top view of a semiconductor memory device according to an embodiment of the disclosure;

FIGS. 2-7 are cross-sectional views (along the cross-sectional line A-A' in FIG. 1) of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure in multiple steps; and

FIG. 8 is a cross-sectional view of a semiconductor memory device according to another embodiment of the disclosure.

This specification provides a method for manufacturing a three-dimensional memory device, which can obtain a higher memory storage capacity in a smaller device size, and at the same time, adjust the wafer warpage height during the manufacturing process. In order to make the above-mentioned embodiments and other purposes, features and advantages of this specification more comprehensible, a memory device and a manufacturing method thereof are specially cited as a preferred embodiment, and will be described in detail in conjunction with the accompanying drawings.

However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The preferred embodiments are only used to illustrate the technical features of the present invention, and not to limit the scope of the patent application of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description in the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Referring to FIG. 1, it shows a top view of a semiconductor memory device according to an embodiment of the disclosure. The semiconductor memory device 100 includes a memory array area 110, a pad area (120a, 120b), and a peripheral area (130a, 130b). The warpage height adjustment features 150 are densely formed in the peripheral area (130a, 130b) to minimize the wafer level drop height caused by wafer warpage. In this embodiment, each peripheral area (130a or 130b) is located between adjacent pad areas (120a, 120b), but it is not limited thereto. The surrounding area may be the area where the word line decoder, bit line decoder, page buffer, charge pump, microcontroller, etc. are located.

Referring to FIGS. 2-7, which illustrate a cross-sectional view (along the cross-sectional line A-A' in FIG. 1) of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure in multiple steps. The semiconductor memory device 100 forms a multilayer stack structure by alternately depositing two different insulating layers (107, 109) on the active region (ie, the first region 103) of the semiconductor substrate 101.

In this embodiment, the two different insulating layers (107, 109) can be a silicon nitride layer and a silicon oxide layer, respectively. In other embodiments of the present invention, the two different insulating layers may be two dielectric materials, such as two dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicate. In some embodiments of this specification, the two different insulating layers (107, 109) are selected from two dielectric materials, which have relatively strong etch resistance and relatively weak resistance to the predetermined etchant. Etching rate.

Referring to FIG. 2, the multilayer stack structure above the first region 103 of the substrate is etched to form a stepped structure (located in the pad area 120a) and a non-stepped structure (located in the memory array area 110). The stepped structure includes a plurality of steps 122. Each stage 122 includes two adjacently different insulating layers (107, 109). Next, an insulating protective layer 115 is formed to cover all areas (110, 120a, 130a), and then a planarization process (such as a CMP process) is performed. In some embodiments, the stepped structure is closer to the peripheral region 130a (or called the second region of the semiconductor substrate) than the non-stepped structure, and the first region 103 and the peripheral region 130a are located on the same side of the semiconductor substrate 101.

A plurality of holes 112 are formed in the non-stepped structure, and each hole 112 penetrates two different insulating layers (107, 109) in the non-stepped structure. From the top view, each hole 112 may have an O-shaped, egg-shaped, oval, or circular appearance, but is not limited thereto.

A memory layer 114 a and a channel layer 114 b are deposited in each hole 112 to form a vertical memory structure 114. In some embodiments of this specification, the memory layer 114a may be a composite layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (that is, an ONO structure), but the structure of the memory layer is not Limit this. In other embodiments of the present specification, the composite layer of the memory layer can also be selected from oxide-nitride-oxide-nitride-oxide (oxide-nitride-oxide-nitride-oxide). , Namely ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a band gap engineering silicon-silicon oxide-nitride Silicon-silicon oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon, BE-SONOS) structure, tantalum nitride-alumina-silicon nitride-silicon oxide- Silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and a metal-high-k dielectric band-gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k Bandgap-engineered silicon-oxide-nitride-oxide-silicon (MABE-SONOS) structure is a group. In this embodiment, the memory layer 114a may be an ONO composite layer, and the channel layer 114b may be a polysilicon layer.

Referring to FIG. 3, a bottom anti-reflective coating 116 and a photoresist layer 118 are formed on all areas (110, 120a, 130a). Then, the photoresist layer 118 is patterned to form the through holes 118a in the peripheral region 130a and the through holes 118b in the non-step structure. The through hole 118b is aligned with the hole 112 below.

Referring to FIG. 4, the patterned photoresist layer 118 is used to perform an etching step to cut through the bottom of the memory layer 114a and the channel layer 114b, and to form a hole 150a in the peripheral area 130a. Then, the bottom anti-reflective coating 116 and the photoresist layer 118 are removed. In some embodiments, the hole 150a is shallower than the hole 112.

Referring to Figure 5, a planarization process (such as a CMP process) is performed to remove the excess memory layer 114a and channel layer 114b material outside the hole 112, and polysilicon is further deposited to fill the bottom and the periphery of the cut through the memory layer 114a and the channel layer 114b Hole 150a in area 130a. Therefore, the channel layer 114b can be connected to the underlying epitaxial silicon layer 124.

Referring to FIG. 6, an oxide layer 114c is deposited in the hole 112, and polysilicon is further deposited to fill the hole 112 and the hole 150a. Therefore, the oxide The layer 114c is wrapped by polysilicon (ie, the channel layer 114b), and each hole 150a is filled with polysilicon to form a polysilicon plug, which can be used as a warpage height adjustment feature 150. Perform another planarization process (such as a CMP process) to remove excess polysilicon material. Next, an annealing treatment at 650° C. is performed for 4 hours to cooperate with the warpage height adjustment feature 150 to compensate for the height of the warped wafer horizontal drop. In this embodiment, the warpage height adjustment feature 150 and the channel layer 114b are formed of the same material and process steps, but are not limited thereto.

In some embodiments, the warp height adjustment features 150 are spaced apart from each other and thereby electrically insulated. In some embodiments, the warpage height adjustment feature 150 and the memory structure 114 are spaced apart from each other so as to be electrically insulated from the memory structure 114. In some embodiments, the warpage height adjustment feature 150 has a smaller height than the memory structure 114.

Referring to FIG. 7, the gate replacement process is performed later, and the conductive layer 108 is used to replace the insulating layer 109. For example, an etchant having a strong etching ability for the insulator 109 but a weak or no etching ability for the insulating layer 107 is used to remove the insulating layer 109 and backfill the conductive material to form the conductive layer 108. Therefore, each step 122 of the stepped structure after gate replacement includes a pair of adjacent insulating layers 107 and conductive layers 108. In some embodiments, the peripheral area 130a is the area where the multilayer stack structure (107, 108) does not exist, for example, the area where the multilayer stack structure (107, 108) does not exist under the warpage height adjustment feature 150. In some embodiments, the warp height adjustment feature 150 and the conductive layer 108 are spaced apart from each other so as to be electrically insulated from the conductive layer 108. In some embodiments, each memory structure 114 includes gate-all-around transistors, but it is not limited thereto. In some embodiments, the warpage height adjustment feature 150 and the multilayer stack structure (107, 108) are both located on the same side (ie, the front side) of the semiconductor substrate 101.

In some embodiments, the warpage height adjustment feature may be a polysilicon pad. For example, a shallow hole with a larger diameter is filled with polysilicon to form a polysilicon pad. In some embodiments, the warping height adjustment features 150 are densely located occupying at least 10% of the area of the peripheral area (for example, in Figure 1, the warping height adjustment features in the regions (130a, 130b) occupy at least 10% of the entire peripheral area). % Area) to minimize the wafer level drop height caused by wafer warpage.

Please refer to FIG. 8, which shows a cross-sectional view of a semiconductor memory device according to another embodiment of the present disclosure. The main difference between this embodiment and the previous examples is that the warpage height adjustment feature 152 can be located in the peripheral area 130c (or called the third area of the semiconductor substrate) on the back side of the semiconductor substrate 101 according to adjustment requirements, thereby minimizing The height of the wafer level drop caused by wafer warpage. In other words, the multi-layer stack structure (107, 108) and the warpage height adjustment feature 152 are located on the opposite side of the semiconductor substrate 101 (ie, the front side and the back side). The first area 103 and the peripheral area 130a and the peripheral area 130c are located on opposite sides of the semiconductor substrate 101 (ie, the front side and the back side). In some embodiments, the warpage height adjustment feature 152 may be a polysilicon plug or a polysilicon pad.

According to the foregoing embodiment, the three-dimensional semiconductor memory device is provided with a warpage height adjustment feature in the peripheral area to compensate for the height of the wafer level difference caused by the wafer warpage. The warpage height adjustment feature can be a polysilicon plug or a polysilicon pad, and can be located on the front side or the back side of the peripheral area of the semiconductor substrate (ie, the second region or the third region of the semiconductor substrate).

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Semiconductor memory element

110: Memory array area

120a, 120b: pad area

130a, 130b: surrounding area

150: Warp height adjustment feature

Claims (8)

A three-dimensional memory device, comprising: a plurality of conductive layers and a plurality of insulating layers, stacked alternately to form a multi-layer stack structure in a first region of a semiconductor substrate, wherein the multi-layer stack structure has a stepped structure and a non-stepped structure A plurality of memory structures are located in the non-stepped structure to form a memory array area, each of the memory structures passes through the conductive layers and the insulating layers; and a plurality of warpage height adjustment features are located on the semiconductor substrate In the second area, the warpage height adjustment features include polysilicon pads. The three-dimensional memory device according to claim 1, wherein the stepped structure is closer to the second area than the non-stepped structure. The three-dimensional memory device according to claim 1, wherein the warpage height adjustment features occupy at least 10% of the area of the second region. The three-dimensional memory device according to claim 1, wherein each memory structure includes a memory layer and a channel layer, and the warpage height adjustment features and the channel layer include the same material. The three-dimensional memory device according to claim 1, wherein the warpage height adjustment features are electrically insulated from each other. The three-dimensional memory device according to claim 1, wherein the warpage height adjustment features are electrically insulated from the memory structures. The three-dimensional memory device according to claim 1, wherein the warpage height adjustment features and the multilayer stack structure are located on the same side of the semiconductor substrate. A three-dimensional memory device, comprising: a plurality of conductive layers and a plurality of insulating layers, stacked alternately to form a multi-layer stack structure in a first region of a semiconductor substrate, wherein the multi-layer stack structure has a stepped structure and a non-stepped structure A plurality of memory structures are located in the non-stepped structure to form a memory array region, each of the memory structures passes through the conductive layers and the insulating layers; the second region, wherein the first region and the second region are relative to each other Adjacent to and located on the same side of the semiconductor substrate; and a plurality of warpage height adjustment features located in the third region of the semiconductor substrate, wherein the third region is located opposite to the first region and the second region on the semiconductor substrate On the opposite side of the region, the warpage height adjustment features include polysilicon pads.

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