JP2013110193A - Nonvolatile semiconductor storage device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit lateral displacement of a charge in a charge storage layer.SOLUTION: A nonvolatile semiconductor storage device according to an embodiment comprises: first through n-th semiconductor layers (n is a natural number more than 1) 12-1-12-3; and first through n-th memory strings S1-S3 employing the first through n-th semiconductor layers 12-1-12-3 as channels. The i-th memory string Si (i is one of 1-n) includes on a surface of the i-th semiconductor layer 12-i in a third direction, a plurality of charge storage layers 16 and a plurality of control gates 18, which correspond to a plurality of memory cells MC. In the i-th memory string, the charge storage layers 16 of at least two memory cells MC adjacent to each other in a second direction are bonded to each other. Further, among the plurality of control gates 18, a metal element 19 for increasing band offset of the plurality of charge storage layers 16 is added.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.

  In order to increase the integration density and capacity of the nonvolatile semiconductor memory, it is necessary to reduce the design rule. In order to reduce this design rule, further fine processing such as a wiring pattern is required. However, this requires a very advanced processing technique, and as a result, it has become difficult to reduce the design rule.

  Therefore, in recent years, a nonvolatile semiconductor memory having a three-dimensional structure has been proposed in order to increase the degree of integration of memory cells.

  As one of such memories, a plurality of semiconductor layers stacked on a semiconductor substrate are used as a channel of a memory string including a plurality of memory cells (cell transistors) connected in series, and each memory cell has data There is known a non-volatile semiconductor memory called a vertical gate ladder-bit cost scalable memory (VLB) having a vertical gate type three-dimensional stack including a charge storage layer for storing.

  In addition, VLB is a VG-FG type (Vertical gate-Floating gate type) in which the charge storage layer is in an electrically floating state (floating gate), and VG is an insulating layer in which the charge storage layer traps charges. -Classified as SONOS type (Vertical gate-Si / Oxide / Nitride / Oxide / Si type).

  In the VG-FG type, since a certain thickness is required for the floating gate, there is a limit to the shrinkage of the memory string. On the other hand, in the VG-SONOS type, the charge storage layer can be made thin, so theoretically, the memory string can be shrunk compared to the VG-FG type.

  However, even in the VG-SONOS type, as in the VG-FG type, in order to prevent the charge in the charge storage layer of one memory cell from moving into the charge storage layer of another memory cell adjacent thereto, It is necessary to divide the charge storage layer for each memory cell.

  This division of the charge storage layer becomes difficult due to the progress of shrinking of the memory string and the increase in the number of stacked memory strings. In particular, the charge storage layers of a plurality of memory cells connected in series in one memory string are divided at the same time when processing a control gate extending in the direction in which the plurality of semiconductor layers are stacked. It is easy to generate a division failure.

  If the charge storage layers of a plurality of memory cells in one memory string are combined with each other, the memory characteristics deteriorate due to the movement of charges in the charge storage layer.

A. Hubert, et al, IEDM, pp.637-640, 2009 S-J Whang et al., IEDM, pp.668-670, 2010

  The embodiment proposes a technique capable of suppressing the lateral movement of charges in the charge storage layer of each memory cell even if the charge storage layers of the plurality of memory cells in one memory string are not divided. .

  According to the embodiment, the nonvolatile semiconductor memory device is stacked in a first direction perpendicular to the surface of the semiconductor substrate and the semiconductor substrate, extends in a second direction parallel to the surface of the semiconductor substrate, and is insulated from each other. First to n-th semiconductor layers (n is a natural number of 2 or more) and first to n-th memory strings having the first to n-th semiconductor layers as channels. Each of the n memory strings includes a plurality of memory cells connected in series in the second direction, and the i th memory string (i is one of 1 to n) is the i th semiconductor. A plurality of charge storage layers and a plurality of control gates corresponding to the plurality of memory cells on a surface of a layer in a third direction perpendicular to the first and second directions; Within a string, at least Charge storage layer of the two memory cells adjacent to the serial second direction are coupled to each other, is added between the plurality of control gates, further comprising a metal element to increase the band offset of the plurality of charge storage layers.

The perspective view which shows a non-volatile semiconductor memory device. The top view which shows a non-volatile semiconductor memory device. Sectional drawing which shows a memory cell. Sectional drawing which shows a memory cell. Sectional drawing which shows a memory cell. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which follows the XXIII-XXIII line | wire of FIG. FIG. 24 is a sectional view taken along line XXIV-XXIV in FIG. 22. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. FIG. 26 is a sectional view taken along line XXVI-XXVI in FIG. 25. FIG. 26 is a sectional view taken along line XXVII-XXVII in FIG. 25. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. FIG. 29 is a sectional view taken along line XXIX-XXIX in FIG. 28. Sectional drawing which follows the XXX-XXX line of FIG. The perspective view which shows the manufacturing method of a non-volatile semiconductor memory device. Sectional drawing which follows the XXXII-XXXII line | wire of FIG. Sectional drawing which follows the XXXIII-XXXIII line | wire of FIG. The perspective view which shows VLB as an application example. Sectional drawing which follows the XXXV-XXXV line | wire of FIG. The top view which shows VLB as an application example. The top view which shows VLB as an application example. The top view which shows VLB as an application example. The top view which shows VLB as an application example.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

  In the following embodiments, a plurality of semiconductor layers stacked on a semiconductor substrate are used as a channel of a memory string including a plurality of memory cells (cell transistors) connected in series, and each memory cell stores data. A feature of the present invention is that a nonvolatile semiconductor memory including a charge storage layer for adding a metal element that increases the band offset of the charge storage layer between a plurality of memory cells (between a plurality of control gates) in one memory string. Have

  In such a three-dimensional nonvolatile semiconductor memory, in order to prevent the charge in the charge storage layer of one memory cell in one memory string from moving into the charge storage layer of another memory cell adjacent thereto, It is necessary to divide the charge storage layer for each memory cell. However, this division has become difficult due to the progress of shrinking memory strings and the increase in the number of stacked memory strings.

  Therefore, in the following embodiments, a metal that forms a dipole between the plurality of memory cells (between a plurality of control gates) in one memory string so that the charge storage layer side of the plurality of memory cells is negatively or positively charged. Add elements. Thereby, the band offset of the charge storage layer in contact with the metal element can be increased, so that the movement of charges in the charge storage layer of each memory cell can be suppressed.

  For example, if a dipole is formed such that the charge storage layer side is negatively charged, the movement of electrons in the charge storage layer of each memory cell can be suppressed.

  Therefore, high reliability can be realized by improving the memory characteristics.

  Thus, according to the embodiment, the movement of charges in the charge storage layer of each memory cell can be suppressed, that is, the movement of charges in the lateral direction (direction in which the memory string extends) can be prevented. Even if the charge storage layers of a plurality of memory cells in one memory string are not divided, desired memory characteristics can be obtained.

Note that this effect is particularly to improve the erasing characteristics, as a charge storage layer, More-Si-Rich Nitride ( MSRN), i.e., the composition ratio of Si is larger than the composition ratio of N Si _x N _y ( This is noticeable when x> y) is used.

  In addition, the embodiment is effective for the countermeasure against the division failure when it is assumed that the charge storage layers of the plurality of memory cells are divided. However, the division failure of the charge storage layer does not occur, that is, When the charge storage layer of the memory cell is completely divided, there is no problem even if the above-described metal element is added.

  Further, according to the embodiment, there is no problem even if the charge storage layers of a plurality of memory cells in one memory string are coupled to each other. Therefore, it is not necessary to divide the charge storage layers of the plurality of memory cells. Also, desired memory characteristics can be obtained.

  This embodiment is applied to both the VG-FG type in which the charge storage layer is an electrically floating conductive layer (floating gate) and the VG-SONOS type in which the charge storage layer is an insulating layer for trapping charges. Is possible. However, in consideration of scaling and processing accuracy, the nonvolatile semiconductor memory in which the present embodiment is applied to the VG-SONOS type is more suitable for practical use.

[Construction]
1 and 2 show a nonvolatile semiconductor memory device according to the embodiment.

  The semiconductor substrate 10 is a silicon substrate, for example. The insulating layer 11 is, for example, a silicon oxide layer called BOX (Buried oxide), and is used as an element isolation insulating layer.

  On the insulating layer 11, first, second and third layers are stacked in a first direction perpendicular to the surface of the semiconductor substrate 10, extend in a second direction parallel to the surface of the semiconductor substrate 10, and are insulated from each other. Semiconductor layers 12-1, 12-2, and 12-3 are arranged.

  Although this example shows a structure in which three semiconductor layers are stacked, the present invention is not limited to this, and it is sufficient that two or more semiconductor layers are stacked. Also, the larger the number of semiconductor layers that are stacked, the greater the memory capacity as a semiconductor memory, which is desirable.

  The first, second and third semiconductor layers 12-1, 12-2 and 12-3 are insulated from each other by an insulating layer (for example, a silicon oxide layer) 13. However, the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 may be insulated by means other than the insulating layer 13 (for example, a cavity).

  An insulating layer (for example, a silicon oxide layer, a silicon nitride layer, or a stacked layer thereof) 14 is disposed on the uppermost third semiconductor layer 12-3.

  The first, second, and third semiconductor layers 12-1, 12-2, 12-3 and the insulating layers 13, 14 constitute a fin-type stacked structure Fin. The first, second, and third semiconductor layers 12-1, 12-2, and 12-3 are preferably in a single crystal state, but may be in a polycrystalline state or an amorphous state.

  The first, second, and third memory strings S1, S2, and S3 use the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 as channels, respectively. Each of the first, second, and third memory strings S1, S2, and S3 includes a plurality of memory cells MC connected in series in the second direction.

  The first, second, and third memory strings S1, S2, and S3 are respectively in the first and second directions of the first, second, and third semiconductor layers 12-1, 12-2, and 12-3. A plurality of charge storage layers 16 and a plurality of control gates 18 corresponding to the plurality of memory cells MC are provided on the surface in the third direction perpendicular to the first direction.

  Between the first, second and third semiconductor layers 12-1, 12-2, 12-3 and the plurality of charge storage layers 16, a tunnel insulating layer (gate insulating layer) 15 is disposed, A block insulating layer 17 is disposed between the charge storage layer 16 and the plurality of control gates 18 to prevent leakage current at the time of writing / erasing.

  The plurality of control gates 18 extend in the first direction along the surfaces of the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 in the third direction.

  In this example, a structure in which three memory strings are stacked corresponding to three semiconductor layers is shown, but the present invention is not limited to this, and two or more memory strings corresponding to two or more semiconductor layers are shown. Need only be stacked.

  A plurality of control gates 18, specifically, at least at the interface between the exposed surfaces of the charge storage layers 16 of the plurality of memory cells MC after the processing of the control gates and the interlayer insulating layer 20, A metal element 19 for increasing the band offset of the charge storage layer 16 is added. For example, the metal element 19 forms a dipole in which the charge storage layer 16 side of the plurality of memory cells MC is negatively charged.

  The metal element 19 is selected from the group of, for example, Ge, Y, Sr, and lanthanoid (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). One element.

  Further, the metal element 19 may constitute one layer, or may not constitute one layer (for example, a state where the metal element is added in a dot shape or partially).

When the metal element 19 constitutes one layer, the one layer includes an oxide, nitride, or oxynitride containing the metal element 19. For example, when the charge storage layer 16 of the plurality of memory cells MC includes a silicon nitride layer, the metal element 19 is made of La containing La ₂ O ₃ so that the charge storage layer 16 side is negatively charged. Dipoles can be formed.

  Thereby, it is possible to suppress the movement of charges in the lateral direction (direction in which the first, second, and third memory strings S1, S2, and S3 extend) in the charge storage layer 16 of the plurality of memory cells MC. it can. This effect is remarkable when the thickness in the third direction (corresponding to t1 in FIG. 3) of one layer including the metal element 19 is 1 nm or less between the plurality of control gates 18. Further, in this case, when the metal element 19 is a so-called high-k material having a high dielectric constant, an effect of minimizing the influence of inter-cell interference due thereto is also achieved.

  According to the above structure, in each of the first, second, and third memory strings S1, S2, and S3, the charge storage layers 16 of the plurality of memory cells MC are coupled to each other and extend in the second direction. Even if one layer is formed, the lateral movement of charges can be suppressed.

  For example, FIG. 3 shows a region X in FIG. This figure shows a situation in which a division failure of the charge storage layer 16 occurs when it is assumed that the charge storage layer 16 of the plurality of memory cells MC is divided. In this case, in one layer as the charge storage layer 16, the thickness t1 in the third direction between the plurality of control gates 18 is generally smaller than the thickness t2 in the other third direction. It is.

  However, as shown in FIG. 4, when it is assumed that the charge storage layers 16 of the plurality of memory cells MC are divided, there is no division failure of the charge storage layers 16, that is, the plurality of memory cells MC. When the charge storage layer 16 is completely divided, there is no problem even if the metal element 19 is added.

  Further, as shown in FIG. 5, there is no problem even if the charge storage layers 16 of the plurality of memory cells MC in one memory string are coupled to each other. Therefore, the charge storage layers 16 of the plurality of memory cells MC are divided. It is not necessary to assume this. In this case, the thickness of one layer as the charge storage layer 16 in the third direction is substantially uniform.

  As the material constituting each element of the above-described nonvolatile semiconductor memory device, an optimum material corresponding to each generation of the semiconductor memory can be appropriately selected. Hereinafter, an example of the most frequently used material will be described. .

  The semiconductor substrate 10 is, for example, a single crystal silicon substrate. The insulating layers 11 and 13 are, for example, silicon oxide layers.

  Each of the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 is, for example, a silicon (Si) layer. The first, second, and third semiconductor layers 12-1, 12-2, and 12-3 are preferably single crystals, but may be amorphous or polycrystalline.

The uppermost insulating layer 14 constituting the fin-type stacked structure Fin has, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or a structure in which they are stacked.

  The tunnel insulating layer (gate insulating layer) 15 constituting the memory cell MC is, for example, a silicon oxide layer. The tunnel insulating layer 15 may be silicon oxynitride, a stacked structure of silicon oxide and silicon nitride, or the like. The tunnel insulating layer 15 may contain silicon nanoparticles, metal ions, or the like.

When the charge storage layer 16 constituting the memory cell MC is, for example, a silicon nitride layer and the interlayer insulating layer filling the space between the plurality of control gates 18 is TEOS (TetraEthOxySilane), the band offset on the charge storage layer 19 side is increased. As one material containing the metal element 19 for the purpose, a La ₂ O ₃ layer can be used. It is desirable that the La ₂ O ₃ layer has a thickness of 1 nm or less. This is because if the thickness exceeds this, there is a concern that inter-cell interference increases.

  The interlayer insulating layer that fills between the plurality of control gates 18 is preferably made of a material having a dielectric constant comparable to that of a silicon oxide layer having a relative dielectric constant of 3.9. Here, TEOS is used as an example of the interlayer insulating layer. However, for example, a silicon oxide layer formed by baking a polysilazane solvent by heat treatment may be used.

  Even when the charge storage layer 16 is not a silicon nitride layer or when the interlayer insulating layer is not a silicon oxide layer, the metal element 19 can be selected by selecting an appropriate material from the examples of the metal element 19 already described. It is possible to increase the band offset of the charge storage layer 16 in contact with the charge storage layer 16 and suppress the lateral movement of charges in the charge storage layer 16.

Note that the charge storage layer 16 constituting the memory cell MC includes, for example, silicon-rich SiN, Si _x N _y with arbitrary composition ratios x and y of silicon and nitrogen, silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), hafnia (HfO ₂ ), hafnium aluminate (HfAlO ₃ ), nitrided hafnia (HfON), nitrided hafnium aluminate (HfAlON), hafnium silicate (HfSiO), hafnium nitride It can be selected from the group of silicate (HfSiON), lanthanum oxide (La ₂ O ₃ ) and lanthanum aluminate (LaAlO ₃ ).

  Further, the charge storage layer 16 may contain silicon nanoparticles, metal ions, or the like. The charge storage layer 16 may function as a floating gate by including a conductor such as polysilicon or metal to which impurities are added.

The block insulating layer 17 constituting the memory cell MC has a function of preventing leakage current at the time of writing / erasing, for example. The block insulating layer 17 includes, for example, silicon oxide (SiO ₂ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), hafnia (HfO ₂ ), and hafnium aluminate (HfAlO). ₃ ), hafnia nitride (HfON), hafnium nitride aluminate (HfAlON), hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminate (LaAlO ₃ ) And a group of lanthanum aluminum silicate (LaAlSiO).

  The control gate 18 constituting the memory cell MC includes, for example, one of a conductive polysilicon layer and a metal silicide layer such as nickel silicide (NiSi).

  The control gate 18 is made of, for example, a metal compound such as tantalum nitride (TaN), tantalum carbide (TaC), or titanium nitride (TiN), or Ni, V, Cr, Mn that exhibits metallic electrical conductivity characteristics. Y, Mo, Ru, Rh, Hf, Ta, W, Ir, Co, Ti, Er, Pt, Pd, Zr, Gd, Dy, Ho, Er, and silicides thereof may be used.

[Production method]
6 to 33 show a method of manufacturing the semiconductor device shown in FIGS.

  First, as shown in FIGS. 6 and 7, for example, a p-type or n-type silicon substrate having a plane orientation (100) and a specific resistance of 10 to 20 Ωcm is prepared as the semiconductor substrate 10. On the semiconductor substrate 10, a silicon oxide layer as the insulating layers 11, 13, and 14, and a polycrystalline silicon layer as the first, second, and third semiconductor layers 12-1, 12-2, and 12-3, Are alternately formed. Subsequently, a mask layer (for example, a silicon nitride layer) 21 is formed on the insulating layer 14.

  Further, a resist pattern is formed on the mask layer 21 by PEP (Photo Engraving Process). Then, using the resist pattern as a mask, the mask layer 21, the insulating layer 14, the third semiconductor layer 12-3, the insulating layer 13, the second semiconductor layer 12-2, and the insulating layer 13 are formed by RIE (Reactive Ion Etching). Then, the first semiconductor layer 12-1 is etched sequentially.

  Thereby, the fin-type stacked structure Fin is formed. Thereafter, the resist pattern is removed.

  Next, as shown in FIGS. 8 and 9, for example, the first and second fins constituting the fin-type stacked structure Fin are formed by wet etching using choline, CDE (Chemical Dry Etching), or dry etching using chlorine gas. The surface of the second and third semiconductor layers 12-1, 12-2, 12-3 in the third direction is recess-etched. As a result, a recess is formed on the surface of the fin-type stacked structure Fin in the third direction.

  Next, as shown in FIGS. 10 and 11, for example, by a SPA (Slot Plane Antenna) plasma generation technique, in the concave portion in the third direction of the fin-type stacked structure Fin, that is, the first, second and second A tunnel insulating layer (for example, a silicon oxide layer) 15 is formed on the surface of the third semiconductor layers 12-1, 12-2, and 12-3 in the third direction.

  Next, as shown in FIGS. 12 and 13, a charge storage layer (for example, a silicon nitride layer) 16 that covers the entire surface of the fin-type stacked structure Fin is formed by, for example, CVD.

  Next, as shown in FIGS. 14 and 15, for example, by RIE, the charge accumulation layer existing in other portions except for the charge accumulation layer 16 existing in the recess in the third direction of the fin-type stacked structure Fin. Layer 16 is removed. As a result, the charge storage layer 16 remains only on the tunnel insulating layer 15 on the surface in the third direction of the first, second, and third semiconductor layers 12-1, 12-2, 12-3. .

  At this time, the charge storage layer 16 is divided into a plurality of parts in the first direction, and each part is one semiconductor layer 12-i (i is 1 to 3) functioning as a channel of the memory string. One layer) extending in the second direction along one).

  Next, as shown in FIGS. 16 and 17, the mask layer 21 is etched by, for example, isotropic etching, and the width of the mask layer 21 in the third direction is shrunk.

  This process is performed for the purpose of separating the charge storage layers (one layer extending in the second direction) in one memory string from one another for each memory cell when patterning the control gate described later.

  Therefore, when it is assumed that the charge storage layers in one memory string are not separated from each other for each memory cell, this step can be omitted.

  The shrink amount d of the mask layer 21 in this step is set to an amount (theoretical value) sufficient to divide the charge storage layers in one memory string from each other for each memory cell when the control gate is patterned.

  Specifically, the edge portion in the third direction of the mask layer 21 after shrinking is the interface between the first, second and third semiconductor layers 12-1, 12-2, 12-3 and the tunnel insulating layer 15. Place outside. More preferably, the edge portion in the third direction of the mask layer 21 after shrinking is from the interface between the first, second and third semiconductor layers 12-1, 12-2 and 12-3 and the tunnel insulating layer 15. It is preferable to arrange the outer side and the inner side of the interface between the tunnel insulating film 15 and the charge storage layer 16.

  Here, the variation in the shrink amount d of the mask layer 21 contributes to the failure of the division of the charge storage layer in one memory string.

Next, as shown in FIGS. 18 and 19, a block insulating layer (for example, an Al ₂ O ₃ layer) 17 covering the entire surface of the fin-type stacked structure Fin is formed by, for example, CVD.

  Next, as shown in FIGS. 20 and 21, a control gate (for example, a polysilicon layer) 18 that covers the fin-type stacked structure Fin and completely fills the space between the fin-type stacked structures Fin is formed.

  Next, as shown in FIGS. 22 to 24, a resist pattern is formed on the control gate 18 by PEP, and the control gate 18 is patterned by RIE using this resist pattern as a mask.

  Here, the upper surface (surface in the first direction) of the control gate 18 may be planarized by CMP (Chemical Mechanical Polishing) before patterning. In this case, it is desirable to perform CMP after forming an insulating layer such as a silicon oxide layer on the control gate 18.

  The resist pattern has a line and space pattern extending in the third direction on the upper surface of the control gate 18.

  The control gate 18 and the block insulating layer 17 existing in the portion not covered with the resist pattern are completely removed. At the same time, the charge storage layer 16 present in the portion not covered with the resist pattern is also removed.

  In this RIE, since the portion not covered with the resist pattern and the shrinked mask layer 21 is positively removed, theoretically, the charge storage layer 16 existing in the portion not covered with the resist pattern is also included. Removed.

  However, as already described, due to variations in the amount of shrinkage of the mask layer 21, there may be a case where the charge storage layer 16 is poorly divided.

  Thus, an example in which the charge storage layer 16 has a division failure is shown in FIGS. According to this example, the charge storage layer 16 in one memory string remains as one layer extending in the second direction without being completely divided for each memory cell.

  By this patterning, a plurality of line & space patterns extending in the first direction along the surfaces in the third direction of the first, second, and third semiconductor layers 12-1, 12-2, and 12-3. A control gate 18 is formed.

  Further, when the fin-type stacked structure Fin is viewed from the first direction, the plurality of control gates 18 extend in the third direction as a whole, like the resist pattern.

  After this patterning, the resist pattern is removed.

  Next, as shown in FIGS. 28 to 30, between the plurality of control gates 18, specifically, on the exposed surfaces of the plurality of charge storage layers 16 after processing the plurality of control gates 18, and A metal element 19 or a compound containing the metal element 19 (oxide, nitride, or oxynitride) is added to the surfaces of the plurality of control gates 18, respectively.

  Here, when the metal element 19 alone is added, an ion implantation method is used, and when a compound containing the metal element 19 is added, a conformal deposition process such as an LPCVD method or an ALD method may be used.

  The metal element 19 or a compound thereof does not need to constitute one layer. However, when the metal element 19 or a compound thereof constitutes one layer, the thickness is set to 1 nm or less. desirable.

  Further, the metal element 19 or a compound thereof is added to the interface between the charge storage layer 16 and an interlayer insulating layer described later, thereby increasing the band offset of the charge storage layer 16.

Finally, as shown in FIGS. 31 to 33, an interlayer insulating layer (for example, SiO ₂ ) 20 is filled between the plurality of control gates 18. The interlayer insulating layer 20 also completely fills the space between the fin-type stacked structures Fin.

  Through the above steps, the nonvolatile semiconductor memory device shown in FIGS. 1 and 2 can be formed.

  When this device is used as a three-dimensional nonvolatile semiconductor memory such as a VLB, one of the first, second and third semiconductor layers 12-1, 12-2, 12-3 is used. A selection function for selection is required, but for the selection function, a staircase structure, a layer selection transistor, and the like have already been proposed, and a description thereof is omitted here.

[Application example]
An application example of the nonvolatile semiconductor memory device according to the embodiment will be described.

  In the following application examples, the same components as those in the above-described nonvolatile semiconductor memory device in FIGS.

  FIG. 34 shows a VLB as a first application example. FIG. 35 shows a sectional view taken along line XXXV-XXXV in FIG.

  In this application example, the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 stacked on the semiconductor substrate 10 are selected in a staircase shape.

  Both ends in the second direction of the fin-type stacked structure Fin including the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 are connected to the beam 22, respectively. The beam 22 exhibits a function of preventing the collapse of the fin-type stacked structure Fin by extending in the third direction.

  The beam 22 includes first, second, and third semiconductor layers 12-1, 12-2, and 12-3 and insulating layers 11, 13, and 14, similarly to the fin-type stacked structure Fin. One end of the beam 22 in the third direction has a step shape. With this step shape, the contact plug 23 can be connected to the first, second, and third semiconductor layers 12-1, 12-2, 12-3 independently of each other.

  The width in the second direction of the beam 22 may be the same as or different from the width in the third direction of the fin-type stacked structure Fin. However, for the purpose of reducing the wiring resistance in the beam 22 and preventing the collapse of the fin-type stacked structure Fin, the width of the beam 22 in the second direction is wider than the width of the fin-type stacked structure Fin in the third direction. Is desirable.

  Note that the contact plug 23 includes a metal material such as W or Al. A bit line or a source line is connected to the contact plug 23.

  FIG. 36 is a diagram in which the i-th semiconductor layer (i is one of 1 to 3) 12-i is cut along a plane parallel to the surface of the semiconductor substrate 10. FIG. 37 is a diagram in which the insulating layers 13 and 14 are cut along a plane parallel to the surface of the semiconductor substrate 10.

  As can be seen from these drawings, when a plurality of fin-type stacked structures Fin are arranged, trenches are formed between the plurality of control gates 18 after patterning of the plurality of control gates 18. In this case, the metal element 19 or a compound thereof is added to the inner surface of the trench. In addition, after adding the metal element 19 or a compound thereof, the trench is filled with the interlayer insulating layer 20.

  That is, the metal element 19 and the compound thereof are respectively formed on the surface in the third direction of the charge storage layer 16 existing between the plurality of control gates 18 and on the surface in the second direction of the plurality of control gates 18. Added.

  FIG. 38 shows a pattern of the plurality of control gates 18 when the fin-type stacked structure Fin is viewed from the first direction.

  The plurality of control gates 18 have a line & space pattern and extend in the third direction as a whole. However, between the fin-type stacked structures Fin, the plurality of control gates 18 extend in the first direction (the direction perpendicular to the paper surface) along the surface of the fin-type stacked structure Fin in the third direction.

  FIG. 39 shows VLB as a second application example.

  In this application example, selection of the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 stacked on the semiconductor substrate 10 is performed by selecting the first, second, and third layer selection transistors. The case where it carries out by is shown.

  Both ends in the second direction of the fin-type stacked structure Fin including the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 are connected to the beam 22, respectively. The beam 22 exhibits a function of preventing the collapse of the fin-type stacked structure Fin by extending in the third direction.

  The beam 22 includes first, second, and third semiconductor layers 12-1, 12-2, and 12-3 and insulating layers 11, 13, and 14, similarly to the fin-type stacked structure Fin. At one end of the beam 22 in the third direction, the first, second and third layer selection transistors LST are arranged.

  The first, second, and third layer selection transistors LST are, for example, FETs (Field Effect Transistors), and channel the first, second, and third semiconductor layers 12-1, 12-2, 12-3. And one of the first, second, and third semiconductor layers 12-1, 12-2, 12-3 is selected.

  The first, second and third layer selection transistors LST are arranged side by side in the third direction, and are arranged at a constant pitch P in order from the contact plug (common electrode) 23 side. 2 and third gate electrodes 24-1, 24-2, 24-3. The first, second, and third gate electrodes 24-1, 24-2, 24-3 include, for example, a conductive polysilicon layer, a metal silicide layer such as a nickel silicide layer, or a stacked layer thereof.

  The first, second, and third gate electrodes 24-1, 24-2, 24-3 are at least the first, second, and third semiconductor layers 12-1, 12-2, 12-3. Extends in a first direction along a side surface in the direction of 2.

  In this example, the first, second, and third gate electrodes 24-1, 24-2, 24-3 are the upper surface in the first direction of the fin-type stacked structure Fin and the two in the second direction. Cover the sides. That is, the layer selection transistor LST has a double gate structure.

  The first layer selection transistor LST including the first gate electrode 24-1 has a normally on channel in the first semiconductor layer 12-1. That is, the first layer selection transistor LST including the first gate electrode 24-1 is normally on in the first semiconductor layer 12-1, and the second and third semiconductor layers 12-2 and 12-3. ON / OFF control can be performed within.

  The second layer selection transistor LST including the second gate electrode 24-2 has a normally on channel in the second semiconductor layer 12-2. That is, the second layer selection transistor LST including the second gate electrode 24-2 is normally on in the second semiconductor layer 12-2, and the first and third semiconductor layers 12-1, 12-3. ON / OFF control can be performed within.

  The third layer selection transistor LST including the third gate electrode 24-3 has a normally on channel in the third semiconductor layer 12-3. That is, the third layer selection transistor LST including the third gate electrode 24-3 is normally on in the third semiconductor layer 12-3, and the first and second semiconductor layers 12-1, 12-2. ON / OFF control can be performed within.

  When generalized, the i-th layer selection among the first to n-th layer selection transistors LST having the first to n-th semiconductor layers (n is a natural number of 2 or more) 12-1 to 12-n as a channel. The transistor (i is one of 1 to n) can be normally on in the i-th semiconductor layer and can be turned on / off in the other semiconductor layers.

  Note that normally-on channels in the first, second, and third semiconductor layers 12-1, 12-2, and 12-3 have n-type impurities (pentavalent elements such as arsenic and phosphorus), p-type impurities ( Boron, a trivalent element such as indium), or an impurity region containing both of them.

  With the first, second, and third layer selection transistors LST, the contact plug 23 is connected to the common electrode common to the first, second, and third semiconductor layers 12-1, 12-2, 12-3. Is possible. That is, since it is not necessary to provide a contact plug for each of the first, second and third semiconductor layers 12-1, 12-2 and 12-3, the size of the contact region can be reduced. .

  The width in the second direction of the beam 22 may be the same as or different from the width in the third direction of the fin-type stacked structure Fin. However, for the purpose of reducing the wiring resistance in the beam 22 and preventing the collapse of the fin-type stacked structure Fin, the width of the beam 22 in the second direction is wider than the width of the fin-type stacked structure Fin in the third direction. Is desirable.

  The contact plug (common electrode) 23 includes a metal material such as W or Al. A bit line or a source line is connected to the contact plug 23.

[Others]
This embodiment is also applicable to the VG-FG type in which the charge storage layer is a conductive layer (floating gate) in an electrically floating state.

For example, when the processing surface of the floating gate as a charge storage layer is covered with a natural oxide film (SiO ₂ ) formed during processing, the charge storage layer side is negatively charged and the band on the charge storage layer side is charged. A metal element or a compound thereof capable of forming a dipole that increases the offset and suppresses the movement of electrons in the charge storage layer may be formed with a sufficient thickness.

  Also, when the processed surface of the floating gate as a charge storage layer is exposed, the charge storage layer side is negatively charged, the band offset on the charge storage layer side is increased, and the movement of electrons in the charge storage layer It is only necessary to form a metal element or a compound thereof capable of forming a dipole that suppresses the formation of a very thin thickness of 1 nm or less.

  Also in this case, the metal element is, for example, Ge, Y, Sr, lanthanoid (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). You can select from a group.

[Musubi]
According to the embodiment, even if the charge storage layers of a plurality of memory cells in one memory string are not divided, the movement of charges in the charge storage layer of each memory cell can be suppressed.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10: Semiconductor substrate 11, 13, 14: Insulating layer 12-1, 12-2, 12-3: Semiconductor layer 15: Tunnel insulating layer (gate insulating layer) 16: Charge storage layer 17: Block insulating Layer: 18: control gate, 19: metal element, 20: interlayer insulating layer, 21: mask layer, 22: beam, 23: contact plug, 24-1, 24-2, 24-3: gate electrode, S1, S2 , S3: Memory string, MC: Memory cell, LST: Layer selection transistor.

Claims (12)

A semiconductor substrate and first to nth semiconductor layers (n is an insulating layer) stacked in a first direction perpendicular to the surface of the semiconductor substrate, extended in a second direction parallel to the surface of the semiconductor substrate, and insulated from each other A natural number of 2 or more) and first to n-th memory strings having the first to n-th semiconductor layers as channels.
Each of the first to nth memory strings includes a plurality of memory cells connected in series in the second direction,
The i th memory string (i is one of 1 to n) is formed on the surface of the i th semiconductor layer in a third direction perpendicular to the first and second directions. A plurality of charge storage layers and a plurality of control gates corresponding to the memory cells,
In the i-th memory string, at least the charge storage layers of two memory cells adjacent in the second direction are coupled to each other,
A nonvolatile semiconductor memory device further comprising: a metal element that is added between the plurality of control gates and increases a band offset of the plurality of charge storage layers. In the i-th memory string, the plurality of charge storage layers constitute one layer extending in the second direction by being coupled to each other,
The nonvolatile semiconductor memory device according to claim 1, wherein the metal element is added on a surface of the one layer existing between the plurality of control gates in the third direction.   3. The nonvolatile semiconductor memory device according to claim 2, wherein the one layer has a thickness in the third direction between the plurality of control gates smaller than a thickness in the other third direction.   The metal element is at least one selected from Ge, Y, Sr, and lanthanoid (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). The nonvolatile semiconductor memory device according to claim 1, comprising an element.   The nonvolatile semiconductor memory device according to claim 1, further comprising a metal compound layer between the plurality of control gates, wherein the metal compound layer includes the metal element.   The nonvolatile semiconductor memory device according to claim 5, wherein the metal compound layer includes an oxide, a nitride, or an oxynitride containing the metal element.   The nonvolatile semiconductor memory device according to claim 5, wherein a thickness of the metal compound layer in the third direction is 1 nm or less. The nonvolatile semiconductor memory device according to claim 5, wherein the plurality of charge storage layers include a silicon nitride layer, and the metal compound layer includes La ₂ O ₃ .   The nonvolatile semiconductor memory device according to claim 1, wherein one end of the first to nth semiconductor layers in the second direction has a step shape.   The first to n-th layer selection transistors having the first to n-th semiconductor layers as channels, and the i-th layer selection transistor (i is one of 1 to n) The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer is normally on. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1,
Forming the first to nth semiconductor layers;
Forming the plurality of charge storage layers and the plurality of control gates corresponding to the plurality of memory cells on a surface of the i-th semiconductor layer in the third direction;
Adding the metal element between the plurality of control gates. A method of manufacturing a nonvolatile semiconductor memory device.   The method of manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the addition of the metal element is performed by forming an oxide, nitride, or oxynitride containing the metal element between the plurality of control gates.

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