TWI525696B - Method for providing a process indicator for an etching chamber, and method for forming semiconductor features - Google Patents

Description

Method for providing process index of etching chamber and method for forming semiconductor feature portion [Cross-reference related application]

This case is a partial continuous case (CIP) of the following US patent application: US patent application, the serial number is No. 11/392,356, the invention name is "Process for Wafer Temperature Verification in Etch Tools", the inventor is Kanarik, etc., the application date This is incorporated herein by reference for all purposes.

The present invention relates to the formation of semiconductor devices, and in particular, to the process specifications for providing an etch tool for the formation of semiconductor devices.

During semiconductor wafer processing, features of the semiconductor component are defined on the wafer by well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and the photoresist is then exposed to light filtered through the primary mask. Thereafter, the wafer is etched to remove material below the area that is no longer protected by the photoresist material, thereby defining the desired features on the wafer. In the semiconductor manufacturing process, the characteristics generally measured for the feature portion are critical dimension (CD), etching rate, load effect, profile, selectivity, bow, and the like. There are still more "specifications" that are important at the time of manufacture. CD is an important parameter to consider, in part because it defines a feature node.

Reproducibility has become one of the most important in the semiconductor industry for different wafers processed in the same semiconductor processing device, and between the same semiconductor processing devices, or even different types of semiconductor processing devices. One of the topics. Performing only one feature etch is not sufficient, it must be regenerated on the entire wafer, and each wafer on each tool can be regenerated at any time. Repeatability is important because there are very many (eg, several mega) etched transistors on each wafer, and quite a few wafers are processed each day. Repeatability includes uniformity (in-wafer), wafer-to-wafer, batch-to-batch, chamber-to-chamber, over-time, and even different hardware Process transfer between the two chambers. To achieve this uniformity and regularity of repeatability, it is a big problem in the industry.

In an attempt to achieve this regularity, one approach is to try to get the tool calibrated between tools or timeouts, and try to make the tools the same. In practice, this method is helpful, but it does not completely solve the problem. For example, the tool may be verified as having been calibrated, but if the chamber wall is dirty or has component wear, the result will be uneven. A blanket etch test can be used to try to understand how the plasma works, but these full-area tests typically do not correlate with patterned wafer results, such as CDs, and it is important to be able to predict CDs. Before etching expensive patterned wafers, it is important to know if the chamber is ready to properly etch expensive patterned wafers.

In order to achieve the foregoing objectives, and in accordance with the purpose of the present invention, a method of providing a process index for an etch chamber is provided. A wafer having a full area etch layer is placed into the etch chamber. A full area etch is performed on the full area etch layer. After the completion of the full area etch, a blanket deposited layer is deposited over the full area etch layer. The thickness of the etched layer of the entire region and the thickness of the blanket deposited layer were measured. The measured thickness is used as a process index.

In another embodiment of the invention, a method of forming a semiconductor feature is provided. A wafer having a full area etch layer is placed into the etch chamber. A full area etch is performed on the full area etch layer. After the completion of the full area etch, a blanket deposited layer is deposited over the full area etch layer. The thickness of the etched layer of the entire region and the thickness of the blanket deposited layer were measured. The measured thickness is used as a process index. If the process index falls outside the threshold, the etch chamber is adjusted. Repeat the previous steps until the process metric falls within the threshold. After the process index value falls within the threshold, the patterned wafer is placed into the etch chamber. The patterned wafer is etched to form a semiconductor feature.

In another embodiment of the invention, a method of providing a process index for an etch chamber is provided. A first wafer having a full area etch layer is placed into the etch chamber. A full area etch is performed on the full area etch layer. The first wafer is removed from the etch chamber. The second wafer is placed into the etch chamber. A blanket deposited layer is deposited on the second wafer. The thickness of the entire area of the etch layer of the first wafer is measured. The thickness of the blanket deposited layer of the second wafer is measured. The measured thickness is used as a process index.

The above and other technical features of the present invention will be further described in detail in the following embodiments with reference to the accompanying drawings.

The invention will be described in detail by way of the preferred embodiments of the invention illustrated in the drawings. In the following, in order to make the invention more versatile, it will be explained with a number of specific details, but those of ordinary skill in the art should understand that these specific details, whether in whole or in part, are implemented. In the case of the present invention, it may not be required. In other instances, well-known process steps and/or structures are not described in detail to avoid unnecessarily obscuring the invention.

In the fabrication of semiconductor components, it is desirable to maintain critical dimensions (CD), etch rates, and other etch parameters consistent between different etch devices, or at the same etch device but at different times.

To aid understanding, Figure 1 is a high level flow diagram of a process for use in an embodiment of the present invention. A blanket wafer is placed in the etch chamber (step 104). 2A is a cross-sectional view of a patterned wafer 204 placed in an etch chamber. The patternless wafer 204 has a blanket etch layer 208 which is a uniform layer on the surface of the upper wafer. The full area etch layer 208 can be a ruthenium oxide layer formed on the surface of the wafer. Other embodiments may provide a blank germanium wafer having a full area etch layer, which may be any etchable material such as tantalum nitride, polyfluorene, TiN, and organic as present in the PR mask material. Compound. The full area etch layer is preferably a uniform layer on the wafer.

4 is a schematic diagram of an etch chamber 400 that can be used in an embodiment of the present invention. The etch chamber 400 includes a confinement ring 402, an upper electrode 404, a lower electrode 408, a gas source 410, and an exhaust pump 420. Gas source 410 can include an etch gas source and a deposition gas source. Within the plasma processing chamber 400, the wafer 204 is disposed on the lower electrode 408. Lower electrode 408 contains a suitable substrate chuck mechanism (eg, static electricity, mechanical clamps, etc.) to support wafer 204. The reactor upper portion 428 includes an upper electrode 404 disposed opposite the lower electrode 408. Upper electrode 404, lower electrode 408, and confinement ring 402 define a restricted plasma volume 440. Gas is supplied to the restricted plasma volume 440 using a gas source 410 and exhausted from the restricted plasma volume 440 by the exhaust pump 420 passing the gas through the confinement ring 402 and the discharge port. The first RF source 444 is electrically connected to the upper electrode 404. The second RF source 448 is electrically coupled to the lower electrode 408. The chamber wall 452 surrounds the confinement ring 402, the upper electrode 404, and the lower electrode 408. Both the first RF source 444 and the second RF source 448 can include a 27 MHz power supply, a 60 MHz power supply, and a 2 MHz power supply. It is also possible to have different combinations of RF power sources connected to the electrodes. In a preferred embodiment of the invention, the 27 MHz, 60 MHz, and 2 MHz power supplies form a second RF power source 448 that is coupled to the lower electrode and the upper electrode is grounded. Temperature control device 470 is coupled to lower electrode 408 to control the temperature of the lower electrode. Controller 435 is coupled to RF sources 444, 448, exhaust pump 420, temperature control device 470, and gas source 410 in a controlled manner. The device is capable of modulating chamber pressure, gas flow, gas combination, RF power, electrostatic chuck cooling, and length of time at various stages.

5A and 5B illustrate a computer system 500 that is suitable for implementing a controller 435 for use with embodiments of the present invention. Figure 5A shows a possible physical form of a computer system. Of course, computer systems can have many physical types, ranging from integrated circuits, printed circuit boards, small handheld devices to very large supercomputers. The computer system 500 includes a monitor 502, a display 504, a housing 506, a disc drive 508, a keyboard 510, and a mouse 512. The disc 514 is a computer readable medium for transmitting data to and from the computer system 500.

FIG. 5B is an example of a block diagram of computer system 500. Connecting to system bus 520 is a wide variety of subsystems. One or more processors 522 (also referred to as central processing units or CPUs) are coupled to the storage device including memory 524. The memory 524 includes random access memory (RAM) and read only memory (ROM). It is known in the art that the role of ROM is to transfer data and instructions to the CPU in one direction, while RAM is generally used to transmit data and instructions in both directions. Both of these memories can include any suitable computer readable medium described below. Fixed disc 526 is also coupled bi-directionally to CPU 522; it provides additional data storage space and can also include any of the computer readable media described below. The stationary disc 526 can be used to store programs, data, etc., and is typically a secondary storage medium (such as a hard drive) that is slower than the primary storage device. As will be appreciated, the information present in the stationary disc 526 can be included in the memory 524 as a virtual memory in a standard manner, where appropriate. The removable disc 514 can have the form of a computer readable medium described below.

CPU 522 is also coupled to various input/output devices such as display 504, keyboard 510, mouse 512, and speaker 530. In general, the input/output device can be any of the following: a video display, a trackball, a mouse, a keyboard, a microphone, a touch display, a conversion card reader, a tape or tape reader, a tablet device. , stylus, sound or handwriting recognizer, biometric reader or other computer. CPU 522 is selectively coupleable to another computer or communication network that uses network interface 540. Using this web interface, we should know that when performing the above method steps, the CPU can receive information from the network or can output information to the network. Moreover, embodiments of the method of the present invention may be performed separately on the CPU 522, or by a remote CPU sharing a portion of the processing via a network (e.g., the Internet).

Moreover, embodiments of the present invention are more directed to computer storage products having computer readable media storing computer program code for performing various computer implemented tasks. The media and computer code may be specially designed and constructed for the purposes of the present invention, or it may be well known and available to those of ordinary skill in the art of computer software. For example, tangible computer readable media include, but are not limited to, magnetic media such as hard disks, floppy disks, magnetic tapes; optical media such as CD-ROMs, holographic devices; optical magnetic media such as floptical disks And hardware devices that are used to store and execute code, such as application-specific integrated circuits (ASICs), coded logic devices (PLDs), and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher-level code that is executed by a computer using an interpreter. The computer readable medium can also be a computer code transmitted by a computer data signal embodied in a carrier wave, representing a sequence of instructions executable by the processor.

The full area etch layer 208 is etched by the etch chamber 400 (step 108). 2B is a cross-sectional view of the wafer 204 and the full area etch layer 208 after etching in the entire region. In this case, the outer edge of the wafer is etched faster than the interior. In other embodiments, the outer edges may be etched slower than the inner, or the two regions may be etched at the same rate, or other contours may be formed.

An example of a full area etch provides a CF ₄ etch gas at a flow rate of 200 sccm. An RF power of 27 MHz, 800 watts is provided to energize the etching gas. The pressure is maintained at 50 mTorr. The resulting plasma lasts for 120 s.

A blanket deposition layer is deposited over the full area etch layer (step 112). 2C is a cross-sectional view of wafer 204 and full-area etch layer 208 after deposition of blanket deposition layer 212.

An exemplary formulation for depositing this layer on a wafer is as follows: a deposition etch stage gas of 18 sccm C ₄ F ₈ and 300 sccm Ar is provided. A cooling system that passes through the electrostatic chuck is set to maintain the electrostatic chuck at a temperature of 20 °C. The chamber pressure was set to 180 mTorr. 300W is supplied with a 27 MHz RF source and 300W with a 2 MHz power supply. In this example, the deposition was carried out for 120 seconds. This formulation forms a polymer layer on the wafer.

The thickness of the full area etch layer 208 and the thickness of the blanket deposited layer 212 are then measured (step 116). Available manufacturing KLA-Tencor Corporation ^TM, sold means of ellipsometry to measure the thickness of the region of the etch layer 208 and the thickness of blanket layer 212 deposited. The dual oscillator model provides sufficient differentiation for the yttria optical function to measure both the polymer layer thickness and the underlying yttrium oxide layer thickness on the tantalum wafer. Other devices and methods may be used to measure the thickness of the full area etch layer 208 and the thickness of the blanket deposited layer 212. In general, such a measurement device requires the wafer to be removed from the etch chamber and placed in the metrology tool prior to measuring the thickness of the full-area etch layer 208 and the thickness of the blanket deposition layer 212. The thickness of the full area etch layer 208 and the thickness of the blanket deposited layer 212 can be measured at a location on the wafer or at a plurality of different locations on the wafer. In a preferred embodiment, the wafer is measured at at least 49 locations on the wafer.

The thickness of the full area etch layer 208 and the thickness of the blanket deposited layer 212 are used to determine a process index (step 120). Various methods can be used to determine process specifications. In one example, the thickness of the measured full area etch layer 208 and the thickness of the blanket deposited layer 212 can be compared to the thickness of the etch layer of the full area as measured by the standard and the thickness of the blanket deposited layer. The difference in uniformity across the wafer reveals a lot of information about the chamber state (ie, whether it is ready to process the patterned wafer) and whether there are errors. For example, if the bolt on one side of the chamber is not locked correctly, this may only be displayed on the side of the chamber.

In this example, it is determined if the process metric is outside the threshold (step 124). If the process specification is outside the threshold, it can be used to determine the etch chamber error. More complex algorithms can be used to compare thicknesses to determine process specifications. In this example, if the process index is outside the threshold, the etch chamber is adjusted according to the process index (step 128), and the process returns to step 104 where the unpatterned wafer is placed in the etch chamber.

If the process specification is not outside the threshold, the etch chamber is substantially in compliance with the standard and is ready for processing. The mask wafer is then placed in an etch machine (step 132). 3A is a cross-sectional view of wafer 304 with an etch layer 308 disposed thereon and an etch mask 312 disposed on etch layer 308. Various numbers of intermediate layers may be disposed between the wafer 304, the etch layer 308, and the etch mask 312. As shown in FIG. 3B, in the etching machine, the features 316 are etched through the mask in the etch layer 308 (step 136).

In one example, if a system uses five etchers in parallel, the method of the invention can be used in each etch machine. The method of the present invention can be used to adjust each set to a standard before five etchers are used for pattern etching. Adjustments will allow the five etchers to provide a more uniform component. Uniformity is defined herein as providing uniform results between different devices, and these devices may use different or the same process.

In the context of this specification and the patent application, the adjustment is defined as changing the recipe or changing the etching chamber. The goal of the adjustment is to improve process specifications.

The etch chamber can be any etch chamber, such as a dielectric etch chamber for etching a dielectric layer, or an etch chamber for etching a conductive or germanium layer. Preferably, the etch chamber is a dielectric etch chamber. In another embodiment, the etch chamber is an electrical conductor etch chamber that utilizes additional etching and deposition recipes.

In one embodiment of the invention, the invention provides a method of adjusting different types of etching chambers. For example, a standard dielectric etch machine from Lam Research Corp. of Fremont, Calif., can be tuned to an upgrade etch machine from Lam Research Corp. to provide uniform etching for different etches.

In another embodiment, the invention is applied periodically to the same etch chamber, such as after each cleaning of the chamber, or for any reason to open the chamber. The etch chamber may become out of tune over time, or the chamber may need to be re-adjusted after a particular event, such as after a cleaning process. Whether or not the chamber is periodically opened may also become non-compliant. For example, after many RF hours, the thickness of some parts may change and their electrical characteristics change, making the etch chamber different from its previous operating conditions. The method of the present invention provides testing and adjustment when the etching machine does not meet the standards. Adjusting the same chamber over time, or adjusting a plurality of nearly identical chambers together, is called "chamber matching." Chamber matching can be matched between tools, matched between sites, or matched between batches.

Whether there is a chamber matching, or whether the chamber and various subsystems are functioning properly, that is, whether the output power is operating, and whether the chamber and the subsystem are properly calibrated, the determination of the above is called "process calibration". Process specifications provide an indication of error detection or process calibration.

The CD is very sensitive to the amount of deposition in the process because it is located on the sidewall and the effect of the ion effect is much less. The normal etch test is not very good at measuring the deposition because it is etched, but the deposition test is a direct measurement of it and is therefore a preferred CD indicator. On the other hand, for feature properties that are highly ion dependent (vertical etch), such as etch rate, the etch test is a better indicator. Therefore, for measuring the properties of deposition and etching, the two layers are very complementary to each other.

In one embodiment, the thickness of the full area etch layer and the thickness of the blanket deposited layer are measured using a single location. In another embodiment, the thickness of the full area etch layer and the thickness of the blanket deposited layer are measured at at least 49 locations. FIG. 6 is a top plan view of wafer 604. Forty-nine polar plot points 608 and diagonal plot points are assigned to the wafer to form a test pattern.

FIG. 7 is a test result image for measuring a process index by using forty-nine polar plot test patterns of the blanket deposition layer of the present invention. As can be seen in the figure, the resulting process index is radially asymmetric. FIG. 8 is a test result image for measuring a process index by using forty-nine polar plot test patterns of the entire region etch layer of the present invention. As can be seen in the figure, the process index is radially symmetrical. The test results are that the blanket deposition layer of the present invention is asymmetrical, and the etch layer of the entire region of the present invention is symmetrical. For such a combination, it means that the chamber has a certain problem. Fig. 9 is a graph of the upper electrode temperature, which shows that in this example, the temperature of the upper electrode is asymmetrical. The asymmetry of the upper electrode temperature affects the CD uniformity of the patterned wafer. Conventional single-layer testing using only full-area etching results in a symmetric etch as shown in Figure 8, which does not reveal an asymmetry problem until expensive wafers are processed. The present invention provides a better indication of both etched and blanket deposited, which detects this asymmetrical nature.

In another embodiment of the invention, the measurement of the plurality of thicknesses performed at different locations provides spatial information about the uniformity, which may be to provide a spatial map. This can indicate whether the inner and outer portions of the wafer have different etch rates or whether there are asymmetric results.

In another embodiment, a plurality of thickness measurements can be taken at different locations, and the measurements at different locations are then averaged to determine the average thickness. The averaging method, the median or mode method, or other operations can be used to combine a plurality of thicknesses to obtain a combined thicknesses number, which can be used to determine process specifications. The use of a single value such as the combined thickness number determines the process index, thus providing a fast alignment method.

The process index test provided by the present invention utilizes immediately available materials and is inexpensive, fast and accurate. Testing that requires patterned wafers will not work because these tests do not meet these criteria.

Another embodiment of the invention can be used to "scan" process regimes. For example, in a process for providing an etched wafer having a non-uniform CD, an embodiment of the present invention can be used in a faster and cheaper manner than using a patterned wafer if it is desired to know which process state has a more uniform condition. Scan a large number of process states.

Other embodiments of the present invention can be used in place of other tests that require patterned wafers for any reason. These embodiments use less expensive (ie, no pattern) wafers instead of the more expensive wafers (ie, patterned wafers). ).

In another embodiment, blanket deposition can be performed on one wafer, while full-area etching can be performed on another unpatterned wafer, and the measurements of the two wafers can be combined and used as process specifications.

The invention has been described with reference to the preferred embodiments and the accompanying drawings, which are not to be considered as limiting. Various modifications, omissions and changes may be made in the form of the invention and the details of the particular embodiments.

104, 108, 112, 116, 120, 124, 128, 132, 136. . . step

204. . . Patternless wafer

208. . . Whole area etching layer

212. . . Blanket deposit

304. . . Wafer

308. . . Etched layer

312. . . Etched mask

316. . . Characteristic department

400. . . Etching/plasma processing chamber

404. . . Upper electrode

408. . . Lower electrode

410. . . Gas source

420. . . Exhaust pump

428. . . Upper part of the reactor

435. . . Controller

440. . . Restricted plasma volume

444. . . First RF source

448. . . Second RF source

452. . . Chamber wall

470. . . Temperature control device

500. . . computer system

502. . . Monitor

504. . . monitor

506. . . cabinet

508. . . Disc drive

510. . . keyboard

512. . . mouse

514. . . (removable) disc

520. . . Busbar

522. . . processor

524. . . Memory

526. . . Fixed disc

604. . . Wafer

608. . . Polar plot point

The drawings of the present invention are illustrative and not restrictive. In the figures, like elements have like reference numerals.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a high level flow diagram of the formation of features in an etch layer for use in an embodiment of the present invention.

2A through 2C are schematic cross-sectional views of the unpatterned wafer used in the process of Fig. 1.

3A and 3B are schematic cross-sectional views of a mask wafer used in a process used in Fig. 1.

Figure 4 is a schematic illustration of a plasma processing chamber that can be used for etching.

5A, 5B illustrate a computer system suitable for implementation as a controller in an embodiment of the invention.

Figure 6 is a top plan view of a wafer having a test pattern of forty-nine polar plot points and additional diagonal coordinate plot points.

Figure 7 is an image of the deposited layer of the present invention showing only the deposited layer in the double layer test results.

Figure 8 is an image of the etched layer in the full area etch of the present invention showing only the double layer test results.

Figure 9 is a graph of the upper electrode temperature.

104, 108, 112, 116, 120, 124, 128, 132, 136‧‧ steps

Claims (18)

A method of providing a process index for an etch chamber, comprising: a) placing a wafer into the etch chamber, the wafer having a full area etch layer; b) performing a full area etch of the full area etch layer; c) After performing the step of performing the full area etching, depositing a blanket deposition layer on the entire area etching layer; d) measuring the thickness of the entire area etching layer and the thickness of the blanket deposition layer; and e) using the measured The thickness determines the process specification. The method of providing a process index for an etch chamber according to the first aspect of the patent application, wherein the step of determining the process index by using the measured thickness is provided by combining a plurality of thicknesses to obtain a combined thickness. A method of providing a process index for an etch chamber according to claim 1, wherein the step of measuring the thickness of the etched layer of the entire region and the thickness of the blanket deposited layer is performed at a plurality of different locations, and Wherein the step of utilizing the measured thickness comprises providing a spatial map from a plurality of thicknesses measured at the plurality of different locations. The method for providing a process index of an etching chamber according to the third aspect of the patent application, wherein the step of determining the process index by using the measured thickness is to compare the measured thickness with a standard, and further comprises adjusting the etching. The chamber, and repeat steps a) through e) until a process index value falls within a threshold. A method of providing a process index for an etch chamber, as in claim 4, wherein the step of adjusting the etch chamber increases spatial symmetry of the measured thickness. The method for providing a process index of an etch chamber according to claim 5, further comprising: placing a patterned wafer into the etch after the process index value falls within the threshold Engraving the chamber; and etching the patterned wafer. A method of providing a process index for an etch chamber, as in claim 6, wherein the standard is generated from a thickness measured by a device different from the etch chamber. A method of providing a process index for etching a chamber according to claim 6 of the patent application, wherein the entire region etching layer is a hafnium oxide layer. A method of providing a process index for an etch chamber, as in claim 3, wherein the plurality of thicknesses at the plurality of different locations are at least 49 thicknesses in at least 49 locations. For example, in the third aspect of the patent application, the method for providing an etch chamber process index is provided, wherein the process index provides error detection. A method of providing a process index for an etch chamber, as in claim 3, wherein the process index provides process calibration. The method of providing a process index for an etching chamber according to the first aspect of the patent application, wherein the step of determining the process index by using the measured thickness is to compare the measured thickness with a standard, and further comprising adjusting the etching. The chamber, and repeat steps a) through e) until a process index value falls within a threshold. A method of providing a process index for an etch chamber, as in claim 12, wherein the step of adjusting the etch chamber increases spatial symmetry of the measured thickness. For example, the method for providing the process index of the etching chamber according to Item 13 of the patent application scope includes: After the process index value falls within the threshold, a patterned wafer is placed into the etching chamber; and the patterned wafer is etched. A method of providing a process index for an etch chamber, as in claim 14, wherein the standard is derived from a thickness measured for another etch chamber. A method of providing a process index for etching a chamber according to claim 14 wherein the entire region of the etch layer is a ruthenium oxide layer. A method of forming a semiconductor feature comprising: a) placing a wafer into an etch chamber having a full-area etch layer; b) performing a full-area etch of the full-area etch layer; c) completing the execution of the After the etching step of the whole region, a blanket deposition layer is deposited on the etching layer of the whole region; d) measuring the thickness of the etching layer of the whole region and the thickness of the blanket deposition layer; e) determining by using the measured thickness Process index; f) if the process index falls outside a threshold, adjust the etching chamber; g) repeat steps a) to f) until a process index value falls within the threshold; h) at the process index value After falling within the threshold, a patterned wafer is placed into the etch chamber; and i) etching the patterned wafer to form a semiconductor feature. A method of providing a process index for an etch chamber, comprising: a) placing a first wafer into the etch chamber, the first wafer having a full-area etch layer; b) performing a full-area etch of the full-area etch layer c) removing the first wafer from the etch chamber; d) placing a second wafer into the etch chamber; e) depositing a blanket on the second wafer in the etch chamber Lamination f) measuring the thickness of the full-area etch layer of the first wafer after the etch step of the whole region; g) measuring the thickness of the blanket deposited layer of the second wafer; and h) using the measured thickness Determine process specifications.