CN103531428A - Etch tool process indicator method and apparatus - Google Patents

Etch tool process indicator method and apparatus Download PDF

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Publication number
CN103531428A
CN103531428A CN201310482302.2A CN201310482302A CN103531428A CN 103531428 A CN103531428 A CN 103531428A CN 201310482302 A CN201310482302 A CN 201310482302A CN 103531428 A CN103531428 A CN 103531428A
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thickness
wafer
pattern
free
etching chamber
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CN103531428B (en
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克伦·雅各布斯·克瑙里克
乔治·卢克
尼古拉斯·韦布
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy

Abstract

The invention provides an etch tool process indicator method and an apparatus. A wafer with a blanket etch layer is provided in an etching chamber. A blanket etch layer is blanket-etched. A blanket deposition layer is deposited on the blanket etch layer after the blanket etch is carried out. The thicknesses of the blanket etch layer and the blanket deposition layer are measured. A process indicator is determined by using the measured thickness.

Description

Etch tool process indicator method and apparatus
The application is that application number is 201010604277.7, and the applying date is on December 14th, 2010, application Ren Wei Lam Res Corp., and what invention and created name was the application for a patent for invention of " etch tool process indicator method and apparatus " divides an application.
The cross reference of related application
The application by the people such as Kanarik on March 28th, 2006, submit to, name is called " Process For Wafer Temperature Verification in Etch Tools ", application number is 11/392, the part continuation application of 356 U.S. Patent application, for all objects by it by reference to being incorporated to herein.
Technical field
The present invention relates to the preparation of semiconductor device.More particularly, the present invention relates to provide technic index for the etch tool for the preparation of semiconductor device.
Background technology
In semiconductor crystal wafer processing procedure, the feature of described semiconductor device is that patterning and the etch process by knowing forms on wafer.In these techniques, photoresist (PR) material is deposited on described wafer, is then exposed to by photomask (reticle) and crosses in the light filtering.Then, not by the part of photoresist material protection, thereby the wafer material of photoresist below is etched, on described wafer, form required feature.Conventionally the characteristic properties that will measure in semiconductor technology is characteristic size (CD), etch-rate, load (loading), profile, selectivity, bow (bow) etc.There is in the mill more very important " specification ".CD is an important parameter will considering, and this part is because it defines specific node.
In same semiconductor processes device and between identical semiconductor processes device, the repeatability of even processing different wafers between dissimilar semiconductor technology device just becoming semicon industry in one of maximally related problem.Only feature of etching is inadequate, and described feature must be reproduced on whole wafer, and can on each wafer of each tool processes, reproduce all the time.Repeatable why important be because will be on each wafer etching a large amount of (such as trillion) transistor, wherein to process a large amount of wafers every day.Repeatability comprises between consistency (wafer in), different wafer, between different batches, between different disposal chamber, different time, even taking to transmit between two process chambers with different hardware of technique.How realizing so consistent and stable repeatability is a great problem of industrial quarters.
Attempt to obtain this kind of conforming method and be attempt between different instruments or single instrument along with the During of time, as much as possible calibration degree and the consistency of retaining tool.Its principle is if the identical words of instrument, and result is also identical so.In practice, this is useful, but can not address this problem completely.For example, can be calibrated by verification tool, if but on locular wall, have dirt, if or parts be depleted, result or inconsistent so.Can use pattern-free etching (blanket etch) test to obtain plasma operating state, but these pattern-free tests are common and patterned wafer result (such as CD) is not mutually related, and can predict that described patterned wafer result is very important.Importantly before the patterned wafer of etching costliness, understand process chamber and whether be ready to expensive patterned wafer described in correctly etching.
Summary of the invention
In order to realize above-mentioned technical goal, and for purposes of the present invention, in the present invention, provide a kind of and provide the method for technic index for etching chamber.The wafer with pattern-free etch layer is provided in described etching chamber.Described pattern-free etch layer is carried out to pattern-free etching.After the etching of described execution pattern-free completes, above described pattern-free etch layer, deposit pattern-free sedimentary deposit.Measure the thickness of described pattern-free etch layer and the thickness of described pattern-free sedimentary deposit.The thickness that use measures is determined technic index.
In the another kind of form of expression of the present invention, provide a kind of method that forms characteristic of semiconductor.The wafer with pattern-free etch layer is provided in described etching chamber.Described pattern-free etch layer is carried out to pattern-free etching.After the etching of described execution pattern-free completes, above described pattern-free etch layer, deposit pattern-free sedimentary deposit.Measure the thickness of described pattern-free etch layer and the thickness of described pattern-free sedimentary deposit.The thickness that use measures is determined technic index.If described technic index is finely tuned (tune) etching chamber described in this outward in threshold value.Repeat abovementioned steps, until technic index value is in threshold range.After described technic index value is in described threshold range, the wafer of patterning is provided in described etching chamber.Described in etching, the wafer of patterning is to form characteristic of semiconductor.
In the another kind of form of expression of the present invention, provide a kind of and provide the method for technic index for etching chamber.First wafer with pattern-free etch layer is provided in described etching chamber.Described pattern-free etch layer is carried out to pattern-free etching.From described etching chamber, remove described the first wafer.The second wafer is provided in described etching chamber.Above described the second wafer, deposit pattern-free sedimentary deposit.Measure the thickness of the described pattern-free etch layer of described the first wafer.Measure the thickness of the described pattern-free sedimentary deposit of described the second wafer.The thickness that use measures is determined technic index.
Below in detailed description of the invention, in conjunction with following figure, above-mentioned and further feature of the present invention is further described in more detail.
Accompanying drawing explanation
The present invention describes by way of example, rather than carries out restricted explanation, and in the legend of accompanying drawing, identical reference numbers represents identical key element, and wherein:
Fig. 1 is the high-level flowchart that forms feature in etch layer of using in an embodiment of the invention.
Fig. 2 A-C is the schematic cross-section of the pattern-free wafer (blanket wafer) that uses in technique as shown in Figure 1.
Fig. 3 A-B is the schematic cross-section of (masked) wafer that has mask of using in technique as shown in Figure 1.
Fig. 4 is the schematic diagram that can be used to etched plasma processing chamber.
Shown in Fig. 5 A-B, be a computer system, it is suitable as the required controller of embodiments of the present invention.
Fig. 6 is the vertical view of wafer, and described wafer has the test pattern that has four nineteen limit plot points and additional diagonal plot point.
Fig. 7 is for the etched image of pattern-free of the present invention, has only shown the sedimentary deposit of double-deck test result.
Fig. 8 is for the etched image of pattern-free of the present invention, has only shown the etch layer of double-deck test result.
Fig. 9 is upper electrode temperature figure.
Detailed description of the preferred embodiment
With reference now to describing in accompanying drawing, some preferred implementations, describe the present invention.In the following description, many details have been illustrated, to the present invention is had to the thorough understanding of one.Yet obviously, for a person skilled in the art, even if lack some or all in these details, the present invention still can implement.For fear of unnecessarily weakening advantage of the present invention, in other embodiment, known processing step or structure just do not elaborate.
In the semiconductor device of manufacturing, need to be between different etch device or the CD that the different time sections of same etch device is consistent, etch-rate and other etching parameters.
For ease of understanding, Fig. 1 is the high-level flowchart of the technique used in an embodiment of the invention.Pattern-free wafer is put into etching chamber (step 104).Fig. 2 A is the cross sectional view that is placed into the pattern-free wafer 204 in etching chamber.Pattern-free wafer 204 has pattern-free etch layer 208, and described pattern-free etch layer is the consistent layer on the crystal column surface of top.Pattern-free etch layer 208 can be the silicon oxide layer forming above described crystal column surface.In other embodiments, may on pattern-free Silicon Wafer, cover by any etchable material (such as silicon nitride, polysilicon, TiN and organic compound, such as in PR mask material, find those) the pattern-free etch layer that forms.Described pattern-free etch layer is the consistent layer above described wafer preferably.
Fig. 4 is the schematic diagram of the etching chamber 400 that can use in embodiments of the present invention.Etching chamber 400 comprises confinement ring 402, top electrode 404, bottom electrode 408, gas source 410 and exhaust pump 420.Gas source 410 can comprise etch gas source and deposition gas source.In plasma processing chamber 400, wafer 204 is placed on bottom electrode 408.Bottom electrode 408 comprises that suitable substrate clamping mechanism (for example, static, machinery fix etc.) is with fixing wafer 204.Reactor head 428 comprises the top electrode 404 direct relative with bottom electrode 408.Top electrode 404, bottom electrode 408 and confinement ring 402 limit confined plasma volume 440.Gas is provided to confined plasma volume 440 by gas source 410 and from confined plasma volume 440, is discharged by confinement ring 402 and exhaust outlet by exhaust pump 420.The first radio-frequency power supply 444 is electrically connected at top electrode 404.The second radio-frequency power supply 448 is electrically connected at bottom electrode 408.Locular wall 452 is around confinement ring 402, top electrode 404 and bottom electrode 408.The first radio-frequency power supply 444 and the second radio-frequency power supply 448 both can comprise 27MHz power supply, 60MHz power supply and 2MHz power supply, and the RF power supply of different frequency combination can be provided to electrode.In a preferred embodiment of the present invention, described 27MHz, 60MHz and 2MHz electric power generating composition are connected to described second radio-frequency power supply 448 of described bottom electrode, and described top electrode ground connection.Temperature control equipment 470 is connected in bottom electrode 408 to control the temperature of described bottom electrode.Controller 435 is connected to radio frequency source 444,448, exhaust pump 420, temperature control equipment 470 and gas source 410 with controlled manner.This device can regulate the duration in cooling and each stage of pressure, air-flow, gas component, radio-frequency power, the electrostatic chuck of described chamber.
Fig. 5 A and 5B illustrate computer system 500, and it is suitable as the required controller of embodiments of the present invention 435.Fig. 5 A has shown a kind of possible entity form of computer system.Certainly, described computer system can have multiple entity form, and scope is from integrated circuit, printed circuit board (PCB) and small handheld devices until huge super computer.Computer system 500 comprises monitor 502, display 504, shell 506, disc driver 508, keyboard 510 and mouse 512.Disk 514 is computer-readable mediums, for transmitting data to computer system 500 or transmitting data from computer system 500.
Fig. 5 B is an embodiment of the block diagram of computer system 500.Various subsystems are connected in system bus 520.One or more processor 522(are also referred to as CPU, or CPUs) be coupled in memory device, comprise memory 524.Memory 524 comprises random-access memory (ram) and read-only memory (ROM).As well known in the art, ROM can be to described CPU one-way transmission data and instruction, and RAM conventionally can be for transmitting data and instruction in a bi-directional way.This memory of two types can comprise any suitable computer-readable medium described below.Fixed disk 526 is also two-way coupled in CPU522; It provides extra data storage capacity but also can comprise any following computer-readable medium.Fixed disk 526 can be used to storage program, data etc., and normally slower than main storage secondary storage media (such as hard disk).Should be appreciated that the information of preserving in fixed disk 526, in appropriate circumstances, can be used as virtual memory (virtual memory) and be incorporated in memory 524 with standard mode.Removable disk 514 can be taked the form of following any computer-readable medium
CPU522 is also coupled in various input-output apparatus, such as display 504, keyboard 510, mouse 512 and loud speaker 530.Conventionally, input-output equipment may be following any: video display, trace ball, mouse, keyboard, microphone, touch-screen, transducer card, tape or paper tape reader, Digitizing plate, felt pen, voice or person's handwriting identifier, biological characteristic reader, or other computer.Alternatively, CPU522 can be used network interface 540 to be coupled in another computer or communication network.Use this network interface, can imagine, in carrying out the process of said method step, described CPU can be from described network receiving information, or can output information to described network.And method execution mode of the present invention can be carried out separately or carry out together with the remote cpu of network (such as internet) and shared section processes on CPU522.
In addition, embodiments of the present invention further relate to the computer storage products with computer-readable medium, and described computer-readable medium has to carry out the computer code of the various operations that completed by computer.Described medium and computer code can be object specialized designs of the present invention and manufacture, can be also know and can obtain concerning having the personnel of technology of computer software fields.The embodiment of computer-readable medium includes but not limited to: magnetizing mediums is such as hard disk, floppy disk and tape; Light Media Ratio is as CD-ROM and holographic element; Magneto-optic (magneto-optical) medium, such as light floppy disk (floptical disks); With the hardware unit being specially configured as storage and executive program code, such as application-specific integrated circuit (ASIC) (ASIC), programmable logic device (PLD) and ROM and RAM device.The embodiment of computer code comprises machine code, the code of for example being worked out by compiler; And the document that comprises high-order code, described high-order code is by using the computer of interpretive program to carry out.Computer-readable medium can also be that computer data signal in carrier wave transmits and the computer code of the command sequence that represents to be carried out by processor by embedding.
By etching chamber 400, on pattern-free etch layer 208, carried out pattern-free etching (step 108).Fig. 2 B is the viewgraph of cross-section of wafer 204, and it has the pattern-free etch layer 208 after pattern-free etching.In this example, the outer rim of described wafer obtains faster than its etched inside.In other embodiments, the comparable etched inside of described outer rim obtains slower or two regions with roughly the same speed etching or can form other profile.
The etched example of pattern-free can provide 200sccm CF 4the air-flow of etchant gasses.Provide the radio frequency power of lower 800 watts of 27MHz to excite described etchant gasses.Pressure is maintained at 50 millitorrs.The plasma that maintenance produces 120 seconds.
Above described pattern-free etch layer, deposit pattern-free sedimentary deposit (step 112).Fig. 2 C is the cross sectional view of wafer 204, and it has the pattern-free etch layer 208 having deposited after pattern-free sedimentary deposit 212.
The example formulation (recipe) that deposits described sedimentary deposit above described wafer is as follows: 18sccm C is provided 4f 8deposition etch phase gas with 300sccm Ar.The cooling system that passes described electrostatic chuck is set to and described electrostatic chuck is remained on to the temperature of 20 degrees Celsius.Described chamber pressure is set to 180 millitorrs.By described 27MHz radio-frequency power supply, the energy of 300W is provided and the energy of 300W is provided by described 2MHz power supply.In this example, described deposition continues 120 seconds.This formula forms polymeric layer above described wafer.
Then measure the thickness of pattern-free etch layer 208 and the thickness (step 116) of pattern-free sedimentary deposit 212.By KLA-Tencor Corporation tMthe ellipsometer of manufacturing and selling is a kind of device that can be used to measure the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212.The optical function that double oscillator model is silica provides enough differentiation, measures the thickness of the silicon oxide layer of the thickness of polymeric layer and the top of Silicon Wafer in its lower section.Can measure the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212 by other apparatus and method.Conventionally, this measurement mechanism requires described wafer to be removed and put into from described etching chamber described survey tool before measuring the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212.On can a position on described wafer or measure the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212 on a plurality of positions on described wafer.In a preferred implementation, at least 49 described wafers of local measurement around described wafer.
Use the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212 to determine technic index (step 120).Can make ins all sorts of ways determines described technic index.In one example, the canonical measure thickness of the thickness of the thickness of the pattern-free etch layer 208 measuring and pattern-free sedimentary deposit 212 and pattern-free etch layer 208 and pattern-free sedimentary deposit 212 can be compared.Conforming difference on described wafer can provide the state (that is, whether being ready to pattern Processing wafer) of relevant described chamber and whether have many information of fault.For example, if the bolt of described chamber one side correctly do not fixed, may be only in that side display consistency difference of described chamber.
In this example, determine that described technic index is whether outside described threshold value (step 124).If described technic index is outside threshold value, it can be used for determining etching chamber fault.Can come with more complicated algorithm comparison thickness to determine described technic index.In this example, if described technic index, outside threshold value, is finely tuned described etching chamber (step 128) and described technique is got back to step 104 according to described technic index, in step 104, new pattern-free wafer is put into described etching chamber.
If described technic index is not outside described threshold value, so described etching chamber is enough suitable and be ready for processing.Then the wafer that has mask is put into described etcher (step 132).The cross sectional view of Fig. 3 A wafer 304 arranges etch layer 308 above wafer 304, and etching mask 312 is set above etch layer 308.The intermediate layer of various quantity can be set between wafer 304, etch layer 308 and etching mask 312.In etcher, see through etching mask 312 feature 316 be etched into etch layer 308(step 136), as shown in Figure 3 B.
In one example, if system is used five parallel etchers, technique of the present invention can be for each etcher.Technique of the present invention can be used to before providing pattern etched with described etcher each in described five etchers to be fine-tuning to a kind of standard.Described fine setting can make these five etchers that more consistent device is provided.Here " consistency " is defined between different devices consistent result is provided, and it can use different or same technique.
In the present specification and claims, fine setting is defined as adjusting formula or adjusts etching chamber.The target of fine setting is to improve described technic index.
Described etching chamber can be any etching chamber, such as the dielectric etch chamber might for etch dielectric layer or for the conductive etch chamber of etching conductive layer or silicon layer.Preferably, described etching chamber is dielectric etch chamber might.In another embodiment, described etching chamber is the conductor etch chamber might of using another kind of etching and deposition formulation.
An embodiment of the invention are to the invention provides a kind of method of finely tuning dissimilar etching chamber.For example, the dielectric etch device of the standard of the Lam Research Corp. from California Fu Leimeng can be fine-tuning to upgrade version etcher from Lam Research Corp. to consistent etch effect is provided in different etchings.
In another embodiment, the present invention by regularly for same etching chamber, such as after or described chamber clean at each etching chamber be at any time opened for any reason.As time goes by, etching chamber can become " imbalance " (out of tune), or in some event (such as cleaning procedure) afterwards, described chamber need to be finely tuned again.No matter whether regularly open described chamber, and " imbalance " all can become.For example, after many radio frequencies hour, the thickness of some parts may change and their electrical properties also can change, thereby described etching chamber is no longer worked with them habitually in the past like that.Technique of the present invention provides test and the fine setting when described etcher becomes imbalance.Along with the same chamber of time fine tuning or together fine setting almost completely identical chamber be called as " chamber coupling ".Chamber coupling can mated between different Tool Rooms, different location or between different batches.
Whether determine whether to have family coupling or chamber and each subsystem in normal operation, that is, whether described power output is in work, and whether they are properly calibrated and are called as " technique calibration ".Technic index provides the index for fault detect or technique calibration.
CD is very responsive to the deposition in described technique, because ionic effect has much smaller impact on sidewall.Because be to carry out etching when measuring deposition, so normal etch test can not be measured deposition well, and the test of described deposition is directly measured it, is therefore the much better index of CD.On the other hand, etching test is better index for the characteristic properties (such as etch-rate) that highly relies on ion (vertically etching).Therefore, these two layers are complimentary to one another, thereby not only measure deposit properties but also measure etching character.
In one embodiment, use the thickness of pattern-free etch layer and the thickness of described pattern-free sedimentary deposit described in single position measurement.In another embodiment, the thickness of the thickness of described pattern-free etch layer and described pattern-free sedimentary deposit is at least 49 position measurements.Fig. 6 is the schematic top plan view of wafer 604.Indicated four nineteen limit plot points 608 of described wafer and additional oblique angle plot point to form test pattern (test pattern).
Fig. 7 is for pattern-free sedimentary deposit of the present invention, uses the test pattern of four nineteen limit plot points to measure the image of the test result of technic index.As can be seen from the figure the technic index, producing is asymmetric diametrically.Fig. 8 is for pattern-free etch layer of the present invention, uses the test pattern of four nineteen limit plot points to measure the image of the test result of technic index.As can be seen from the figure, this layer process index is symmetrical diametrically.Find the asymmetry of pattern-free sedimentary deposit of the present invention, in conjunction with the symmetry of pattern-free etch layer of the present invention, both combine the specific problem of having indicated described chamber.Fig. 9 is the hygrogram of top electrode.This figure demonstration, in this particular instance, the temperature of top electrode is asymmetric.The Asymmetric ef-fect of upper electrode temperature the CD consistency of wafer of patterning.Traditional single-interval test (only using pattern-free etching) can cause symmetrical etching, as shown in Figure 8, before expensive wafer is processed, can not find asymmetry problem.In the present invention, not only use pattern-free etching but also use pattern-free deposition that better index is provided, it can detect this asymmetry.
In yet another embodiment of the present invention, measure a plurality of thickness relevant conforming spatial information is provided at diverse location, this can provide spatial distribution map.It can indicate the inside and outside part of described wafer whether to have different etch-rates, and whether has asymmetric result.
In another embodiment, can be in different position measurements a plurality of thickness, then the measured value at diverse location is averaged to obtain average thickness.Described average (obtaining median or mould) or other operations can be used in conjunction with a plurality of thickness to obtain integrated thickness number, and described integrated thickness number can be used to determine described technic index.Use individual digit (such as described integrated thickness number) to determine that described technic index provides quick relatively technique.
The invention provides technic index and test, current material and cheap, quick and accurate is used in described technic index test.Need the test of the wafer after patterning not handy, because they do not meet these standards.
Another embodiment of the invention can be used for " scanning " process system (regime).For example, after the etching with inconsistent CD is provided in the technique of wafer, and want to know when which process system has more consistent state, can use an embodiment of the invention to scan a large amount of process systems, compare use patterned wafer, faster also considerably cheaper.
Other execution mode of the present invention is used to substitute due to any former thereby need the test of the wafer of patterning, and wherein these execution modes can be used more the wafer of cheap (that is, pattern-free) rather than more expensive wafer (that is, patterned wafer).
In another embodiment, pattern-free deposition can complete and pattern-free etching can complete on another pattern-free wafer on a wafer.The measurement result of two wafers can combine and be used as technic index.
Although this invention is described according to several preferred implementations, yet exist, falls into the change, displacement of scope of the present invention and to be variously equal to replacement.Shall also be noted that many alternative that realize method and apparatus of the present invention.Therefore, claims are intended to be read as and comprise all these changes, displacement and be variously equal to replacement, all fall in true spirit of the present invention and scope.

Claims (16)

1. a method for technic index is provided for etching chamber, comprises:
A) first wafer with pattern-free etch layer is provided in described etching chamber;
B) described pattern-free etch layer is carried out to pattern-free etching;
C) from described etching chamber, remove described the first wafer;
D) the second wafer is provided in described etching chamber;
E) above the second wafer described in described etching chamber, deposit pattern-free sedimentary deposit;
F) after described pattern-free etching, measure the thickness of the described pattern-free etch layer of described the first wafer;
G) measure the thickness of the described pattern-free sedimentary deposit of described the second wafer; And
H) use the thickness of described measurement to determine technic index.
2. method according to claim 1, the thickness that wherein said use measures determines that technic index provides in conjunction with a plurality of thickness to obtain integrated thickness number.
3. method according to claim 1, the thickness of the described pattern-free etch layer of described the first wafer of wherein said measurement and the thickness of measuring the described pattern-free sedimentary deposit of described the second wafer are measured a plurality of thickness at a plurality of diverse locations, and wherein use the thickness measuring to comprise to utilize described a plurality of different position measurements to a plurality of thickness space diagram is provided.
4. method according to claim 3, the thickness that wherein said use measures determines that technic index compares the described thickness measuring and standard, and further comprise the described etching chamber of fine setting repeating step a-e, until the desired value of processor is in threshold range.
5. method according to claim 4, the spatial symmetry of the thickness having measured described in wherein said fine setting has increased.
6. method according to claim 5, further comprises:
After described technic index value is in described threshold range, the wafer of patterning is provided in described etching chamber; And
The wafer of patterning described in etching.
7. method according to claim 6, wherein said standard is to produce from being different from the thickness of measurement of the device of described etching chamber.
8. method according to claim 6, wherein said pattern-free etch layer is silicon oxide layer.
9. method according to claim 3, wherein the described a plurality of thickness at a plurality of diverse locations is at least 49 thickness from least 49 diverse locations.
10. method according to claim 3, wherein said technic index provides fault detect.
11. methods according to claim 3, wherein said technic index provides technique calibration.
12. methods according to claim 1, the thickness that wherein said use measures determines that technic index compares the described thickness measuring and standard, and further comprise the described etching chamber of fine setting repeating step a-e, until technic index value is in threshold range.
13. methods according to claim 12, the spatial symmetry of the thickness having measured described in wherein said fine setting has increased.
14. methods according to claim 13, further comprise:
After described technic index value is in described threshold range, the wafer of patterning is provided in described etching chamber; And
The wafer of patterning described in etching.
15. methods according to claim 14, wherein said standard is to produce from the thickness of the measurement of another etching chamber.
16. methods according to claim 14, wherein said pattern-free etch layer is silicon oxide layer.
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