CN102142385A - Etch tool process indicator method and apparatus - Google Patents
Etch tool process indicator method and apparatus Download PDFInfo
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- CN102142385A CN102142385A CN2010106042777A CN201010604277A CN102142385A CN 102142385 A CN102142385 A CN 102142385A CN 2010106042777 A CN2010106042777 A CN 2010106042777A CN 201010604277 A CN201010604277 A CN 201010604277A CN 102142385 A CN102142385 A CN 102142385A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
- H05H1/00—Generating plasma; Handling plasma
- H05H1/24—Generating plasma
- H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
Abstract
A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator.
Description
The cross reference of related application
The application by people such as Kanarik submit on March 28th, 2006, name is called " Process For Wafer Temperature Verification in Etch Tools ", application number is 11/392, the part continuation application of 356 U.S. Patent application is for all purposes are incorporated it herein into by reference.
Technical field
The present invention relates to the preparation of semiconductor device.More particularly, the present invention relates to provide technic index for the etch tool that is used to prepare semiconductor device.
Background technology
In the semiconductor crystal wafer processing procedure, the feature of described semiconductor device is to form on wafer by patterning of knowing and etch process.In these technologies, photoresist (PR) material is deposited on the described wafer, is exposed to then by photomask (reticle) to cross in the light that filters.Then, not by the part of photoresist material protection, on described wafer, form required feature thereby the wafer material of photoresist below is etched.Usually the characteristic properties that will measure in semiconductor technology is characteristic size (CD), etch-rate, load (loading), profile, selectivity, bow (bow) etc.More very important " specification " arranged in the mill.CD is an important parameters will considering, and this part is because it defines specific node.
In same semiconductor processes device and between the identical semiconductor processes device, even the repeatability of the different wafers of processing is just becoming one of maximally related problem in the semicon industry between dissimilar semiconductor technology devices.Only feature of etching is not enough, and described feature must be reproduced on whole wafer, and can reproduce on each wafer of each tool processes all the time.Repeatable why important be because will be on each wafer etching a large amount of (such as trillion) transistor, wherein to handle a large amount of wafers every day.Repeatability comprises between consistency (wafer in), different wafer, between different batches, between the different disposal chamber, different time in addition taking to transmit between two process chambers with different hardware of technology.How to realize so consistent and stable repeatability is a great problem of industrial quarters.
Attempting obtaining this conforming a kind of method is to attempt keeping the calibration degree and the consistency of instrument as much as possible between the different instruments or during the variation of single instrument along with the time.Its principle is if the identical words of instrument, and the result is also identical so.In practice, this is useful, but can not address this problem fully.For example, can be calibrated by verification tool, if but on the locular wall dirt is arranged, if perhaps parts are depleted, the result still is inconsistent so.Can use pattern-free etching (blanket etch) test to obtain the plasma operating state, but these pattern-free tests are common and patterned wafer result (such as CD) is not mutually related, and can predict that described patterned wafer result is very important.Importantly before the patterned wafer of etching costliness, understand process chamber and whether be ready to the patterned wafer of the described costliness of etching correctly.
Summary of the invention
In order to realize above-mentioned technical goal, and for purposes of the present invention, provide a kind of method that technic index is provided for etching chamber among the present invention.The wafer that will have the pattern-free etch layer is provided in the described etching chamber.Described pattern-free etch layer is carried out the pattern-free etching.After the etching of described execution pattern-free is finished, deposition pattern-free sedimentary deposit above described pattern-free etch layer.Measure the thickness of described pattern-free etch layer and the thickness of described pattern-free sedimentary deposit.The thickness that use measures is determined technic index.
In the another kind of form of expression of the present invention, provide a kind of method that forms characteristic of semiconductor.The wafer that will have the pattern-free etch layer is provided in the described etching chamber.Described pattern-free etch layer is carried out the pattern-free etching.After the etching of described execution pattern-free is finished, deposition pattern-free sedimentary deposit above described pattern-free etch layer.Measure the thickness of described pattern-free etch layer and the thickness of described pattern-free sedimentary deposit.The thickness that use measures is determined technic index.If described technic index is finely tuned (tune) this described etching chamber outside threshold value.Repeat abovementioned steps, up to the technic index value in threshold range.After described technic index value is in described threshold range, the wafer of patterning is provided in the described etching chamber.The wafer of the described patterning of etching is to form characteristic of semiconductor.
In the another kind of form of expression of the present invention, provide a kind of method that technic index is provided for etching chamber.First wafer that will have the pattern-free etch layer is provided in the described etching chamber.Described pattern-free etch layer is carried out the pattern-free etching.Remove described first wafer from described etching chamber.Second wafer is provided in the described etching chamber.Deposition pattern-free sedimentary deposit above described second wafer.Measure the thickness of the described pattern-free etch layer of described first wafer.Measure the thickness of the described pattern-free sedimentary deposit of described second wafer.The thickness that use measures is determined technic index.
Below in detailed description of the invention,, above-mentioned and further feature of the present invention is carried out more detailed description in conjunction with following each figure.
Description of drawings
The present invention describes by way of example, rather than carries out restricted explanation, and in the legend of accompanying drawing, the identical identical key element of reference numbers representative, and wherein:
Fig. 1 is the high-level flowchart of using in an embodiment of the invention that forms feature in etch layer.
Fig. 2 A-C is the schematic cross-section of the pattern-free wafer (blanketwafer) that uses in as shown in Figure 1 the technology.
Fig. 3 A-B is the schematic cross-section of (masked) wafer that mask is arranged of using in as shown in Figure 1 the technology.
Fig. 4 is the schematic diagram that can be used to etched plasma processing chamber.
Be a computer system shown in Fig. 5 A-B, it is suitable as the required controller of embodiments of the present invention.
Fig. 6 is the vertical view of wafer, and described wafer has the test pattern of the diagonal plot point that four nineteen limit plot points is arranged and add.
Fig. 7 is used for the etched image of pattern-free of the present invention, has only shown the sedimentary deposit of double-deck test result.
Fig. 8 is used for the etched image of pattern-free of the present invention, has only shown the etch layer of double-deck test result.
Fig. 9 is upper electrode temperature figure.
Detailed description of the preferred embodiment
With reference now to describing in the accompanying drawing, some preferred implementations describe the present invention.In the following description, many details have been illustrated, so that the present invention there is one thorough understanding.Yet obviously, for a person skilled in the art, even if lack in these details some or all, the present invention still can implement.For fear of the advantage of the present invention that unnecessarily weakens, in other embodiment, known processing step or structure just do not elaborate.
In the semiconductor device of making, need be between different etch device or CD, etch-rate and other etching parameters that the different time sections of same etch device is consistent.
For ease of understanding, Fig. 1 is the high-level flowchart of the technology used in an embodiment of the invention.The pattern-free wafer is put into etching chamber (step 104).Fig. 2 A is the cross sectional view that is placed into the pattern-free wafer 204 in the etching chamber.Pattern-free wafer 204 has pattern-free etch layer 208, and described pattern-free etch layer is the layer of the unanimity on the crystal column surface of top.Pattern-free etch layer 208 can be the silicon oxide layer that forms above described crystal column surface.In other embodiments, may on the pattern-free Silicon Wafer, cover by any etchable material (such as silicon nitride, polysilicon, TiN and organic compound, such as in the PR mask material, find those) the pattern-free etch layer that forms.Described pattern-free etch layer is the layer of the unanimity above described wafer preferably.
Fig. 4 is the schematic diagram of the etching chamber 400 that can use in embodiments of the present invention.Etching chamber 400 comprises confinement ring 402, top electrode 404, bottom electrode 408, gas source 410 and exhaust pump 420.Gas source 410 can comprise etch gas source and deposition gas source.In plasma processing chamber 400, wafer 204 is placed on the bottom electrode 408.Bottom electrode 408 comprises that suitable substrate clamping mechanism (for example, static, machinery fix or the like) is with fixing wafer 204.Reactor head 428 comprises and bottom electrode 408 direct relative top electrodes 404.Top electrode 404, bottom electrode 408 and confinement ring 402 limit confined plasma volume 440.Gas is provided to confined plasma volume 440 by gas source 410 and is discharged from confined plasma volume 440 by confinement ring 402 and exhaust outlet by exhaust pump 420.First radio-frequency power supply 444 is electrically connected at top electrode 404.Second radio-frequency power supply 448 is electrically connected at bottom electrode 408.Locular wall 452 is around confinement ring 402, top electrode 404 and bottom electrode 408.First radio-frequency power supply 444 and second radio-frequency power supply, 448 boths can comprise 27MHz power supply, 60MHz power supply and 2MHz power supply, and the RF power supply of different frequency combination can be provided to electrode.In a preferred embodiment of the present invention, described 27MHz, 60MHz and 2MHz power supply constitute described second radio-frequency power supply 448 that is connected to described bottom electrode, and described top electrode ground connection.Temperature control equipment 470 is connected in bottom electrode 408 to control the temperature of described bottom electrode.Controller 435 is connected to radio frequency source 444,448, exhaust pump 420, temperature control equipment 470 and gas source 410 with controlled manner.This device can be regulated pressure, air-flow, gas component, radio-frequency power, electrostatic chuck cooling and the duration in each stage of described chamber.
Fig. 5 A and 5B illustrate computer system 500, and it is suitable as the required controller of embodiments of the present invention 435.Fig. 5 A has shown a kind of possible entity form of computer system.Certainly, described computer system can have multiple entity form, scope from integrated circuit, printed circuit board (PCB) and small handheld devices up to huge super computer.Computer system 500 comprises monitor 502, display 504, shell 506, disc driver 508, keyboard 510 and mouse 512.Disk 514 is computer-readable mediums, is used for transmitting data or transmitting data from computer system 500 to computer system 500.
Fig. 5 B is an embodiment of the block diagram of computer system 500.Various subsystems are connected in system bus 520.One or more processors 522 (be also referred to as CPU, or CPUs) be coupled in memory device, comprise memory 524.Memory 524 comprises random-access memory (ram) and read-only memory (ROM).Just as known in the art, ROM can be to described CPU one-way transmission data and instruction, and RAM can be used for transmitting in a bi-directional way data and instruction usually.This memory of two types can comprise any suitable computer-readable medium described below.Fixed disk 526 also bidirectional coupled in CPU 522; It provides extra data storage capacity but also can comprise any following computer-readable medium.Fixed disk 526 can be used to stored program, data or the like, and normally slower than main storage secondary storage media (such as hard disk).Should be appreciated that the information of preserving in the fixed disk 526, in appropriate circumstances, can be used as virtual memory (virtual memory) and be incorporated in the memory 524 with standard mode.Removable disk 514 can be taked the form of following any computer-readable medium
In addition, embodiments of the present invention further relate to the computer storage products with computer-readable medium, and described computer-readable medium has in order to carry out the computer code of the various operations of being finished by computer.Described medium and computer code can be purpose specialized designs of the present invention and manufacturing, also can be to know concerning the personnel of technology with computer software fields and can obtain.The embodiment of computer-readable medium includes but not limited to: magnetizing mediums is such as hard disk, floppy disk and tape; The light medium is such as CD-ROM and holographic element; Magneto-optic (magneto-optical) medium is such as light floppy disk (floptical disks); With the hardware unit that is specially configured to storage and executive program code, such as application-specific integrated circuit (ASIC) (ASIC), programmable logic device (PLD) and ROM and RAM device.The embodiment of computer code comprises machine code, for example the code of being worked out by compiler; And the document that comprises the high-order code, described high-order code is carried out by the computer that uses interpretive program.Computer-readable medium can also be the computer code by the command sequence that embeds the computer data signal transmission in the carrier wave and represent to be carried out by processor.
On pattern-free etch layer 208, carry out pattern-free etching (step 108) by etching chamber 400.Fig. 2 B is the viewgraph of cross-section of wafer 204, and it has the pattern-free etch layer 208 after the pattern-free etching.In this example, the outer rim of described wafer gets faster than its etched inside.In other embodiments, the comparable etched inside of described outer rim get slower or two zones with roughly the same speed etching or can form other profile.
The etched example of pattern-free can provide 200sccm CF
4The air-flow of etchant gasses.Provide the following 800 watts radio frequency power of 27MHz to excite described etchant gasses.Pressure is maintained at 50 millitorrs.The plasma that maintenance produces 120 seconds.
Deposition pattern-free sedimentary deposit (step 112) above described pattern-free etch layer.Fig. 2 C is the cross sectional view of wafer 204, and it has the pattern-free etch layer 208 that has deposited after the pattern-free sedimentary deposit 212.
The example formulation (recipe) of the described sedimentary deposit of deposition is as follows above described wafer: 18sccm is provided C
4F
8Deposition etch phase gas with 300sccm Ar.The cooling system that passes described electrostatic chuck is set to the temperature that described electrostatic chuck is remained on 20 degrees centigrade.Described chamber pressure is set to 180 millitorrs.The energy of 300W is provided and the energy of 300W is provided by described 2MHz power supply by described 27MHz radio-frequency power supply.In this example, described deposition continues 120 seconds.This prescription forms polymeric layer above described wafer.
Measure the thickness of pattern-free etch layer 208 and the thickness (step 116) of pattern-free sedimentary deposit 212 then.By KLA-Tencor Corporation
TMThe ellipsometer of making and selling is the device of the thickness of a kind of thickness that can be used to measure pattern-free etch layer 208 and pattern-free sedimentary deposit 212.The double oscillator model provides enough differentiation for the optical function of silica, measures the thickness of the silicon oxide layer of the thickness of polymeric layer and Silicon Wafer in its lower section top.Can use other apparatus and method to measure the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212.Usually, this measurement mechanism requires before the thickness of the thickness of measuring pattern-free etch layer 208 and pattern-free sedimentary deposit 212 described wafer to be removed and put into described survey tool from described etching chamber.Can on a position on the described wafer or on a plurality of positions on the described wafer, measure the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212.In a preferred implementation, at least 49 described wafers of local measurement around described wafer.
Use the thickness of pattern-free etch layer 208 and the thickness of pattern-free sedimentary deposit 212 to determine technic index (step 120).Can make and in all sorts of ways to determine described technic index.In one example, the thickness of the pattern-free etch layer 208 that measures and the thickness of pattern-free sedimentary deposit 212 and the canonical measure thickness of pattern-free etch layer 208 and pattern-free sedimentary deposit 212 can be compared.Conforming difference on the described wafer can provide the state (that is, whether being ready to the pattern Processing wafer) of relevant described chamber and whether have many information of fault.For example, if the bolt of described chamber one side is not correctly fixed possibility that side display consistency difference in described chamber.
In this example, determine that described technic index is whether outside described threshold value (step 124).If described technic index is outside threshold value, it can be used for determining the etching chamber fault.Can use more complicated algorithm to come comparison thickness to determine described technic index.In this example, if described technic index outside threshold value, is finely tuned described etching chamber (step 128) and described technology is got back to step 104 according to described technic index, in step 104, new pattern-free wafer is put into described etching chamber.
If described technic index is not outside described threshold value, so described etching chamber is enough suitable and be ready for processing.To there be the wafer of mask to put into described etcher (step 132) then.The cross sectional view of Fig. 3 A wafer 304 is provided with etch layer 308 above wafer 304, etching mask 312 is set above etch layer 308.The intermediate layer of various quantity can be set between wafer 304, etch layer 308 and etching mask 312.In etcher, see through etching mask 312 feature 316 is etched into etch layer 308 (step 136), as shown in Fig. 3 B.
In one example, if system uses five parallel etchers, technology of the present invention can be used for each etcher.Technology of the present invention can be used to before providing pattern etched with described etcher in described five etchers each is fine-tuning to a kind of standard.Described fine setting can make these five etchers that more consistent device is provided.Here " consistency " is defined in the result who provides consistent between different devices, and it can use different or same technology.
In this specification and claims, fine setting is defined as adjusting prescription or adjusts etching chamber.The target of fine setting is to improve described technic index.
Described etching chamber can be any etching chamber, such as the dielectric etch chamber might that is used for etch dielectric layer or be used for the conductive etch chamber of etching conductive layer or silicon layer.Preferably, described etching chamber is a dielectric etch chamber might.In another embodiment, described etching chamber is to use the conductor etch chamber might of another kind of etching and deposition formulation.
An embodiment of the invention are to the invention provides a kind of method of finely tuning dissimilar etching chambers.For example, the dielectric etch device from the standard of the Lam Research Corp. of California Fu Leimeng can be fine-tuning to upgrade version etcher from Lam Research Corp. so that consistent etch effect is provided in different etchings.
In another embodiment, the present invention regularly is used for same etching chamber, such as after etching chamber cleaning or described chamber at any time are opened for any reason at every turn.As time goes by, etching chamber can become " imbalance " (out of tune), and perhaps in some incident (such as cleaning procedure) afterwards, described chamber need be finely tuned again.No matter whether regularly open described chamber, and " imbalance " all can become.For example, behind many radio frequencies hour, the thickness of some parts may change and their electrical properties also can change, thereby described etching chamber is no longer worked with them habitually in the past like that.Technology of the present invention provides test and the fine setting when described etcher becomes imbalance.Along with the same chamber of time fine tuning or together the fine setting almost completely identical chamber be called as " chamber coupling ".The chamber coupling can mated between different Tool Rooms, different location or between different batches.
Whether determine whether to have family coupling or chamber and each subsystem in operate as normal, that is, whether described power output is in work, and whether they are called as " technology calibration " by calibration correctly.Technic index provides the index that is used for fault detect or technology calibration.
CD is very responsive to the deposition in the described technology, because ionic effect has much smaller influence on sidewall.Because be to carry out etching when measuring deposition, so the normal etch test can not be measured deposition well, and the test of described deposition is directly measured it, is the much better index of CD therefore.On the other hand, the etching test is better index for the characteristic properties (such as etch-rate) that highly relies on ion (vertically etching).Therefore, these two layers are complimentary to one another, thereby not only measure deposit properties but also measure etching character.
In one embodiment, use the thickness of the described pattern-free etch layer of single position measurement and the thickness of described pattern-free sedimentary deposit.In another embodiment, the thickness of the thickness of described pattern-free etch layer and described pattern-free sedimentary deposit is at least 49 position measurements.Fig. 6 is the schematic top plan view of wafer 604.The oblique angle plot point of having indicated four nineteen limit plot points 608 of described wafer and having added is to form test pattern (test pattern).
Fig. 7 is for pattern-free sedimentary deposit of the present invention, uses the test pattern of four nineteen limit plot points to measure the image of the test result of technic index.As can be seen from the figure, the technic index that is produced is asymmetric diametrically.Fig. 8 is for pattern-free etch layer of the present invention, uses the test pattern of four nineteen limit plot points to measure the image of the test result of technic index.As can be seen from the figure, this layer process index is symmetrical diametrically.Find the asymmetry of pattern-free sedimentary deposit of the present invention, in conjunction with the symmetry of pattern-free etch layer of the present invention, both combine the specific problem of having indicated described chamber.Fig. 9 is the hygrogram of top electrode.This figure shows that in this particular instance, the temperature of top electrode is asymmetric.The asymmetric CD consistency that has influenced the wafer of patterning of upper electrode temperature.Traditional single-interval test (only using the pattern-free etching) can cause the etching of symmetry, as shown in Figure 8, can not find asymmetry problem before the wafer of costliness is processed.In the present invention, not only use the pattern-free etching but also use the pattern-free deposition that better index is provided, it can detect this asymmetry.
In yet another embodiment of the present invention, measure a plurality of thickness at diverse location relevant conforming spatial information is provided, this can provide spatial distribution map.It can indicate the inside and outside part of described wafer whether to have different etch-rates, and whether asymmetric result is arranged.
In another embodiment, can then the measured value at diverse location be averaged to obtain average thickness at a plurality of thickness of different position measurements.Described average (obtaining median or mould) or other operations can be used in conjunction with a plurality of thickness to obtain the integrated thickness number, and described integrated thickness number can be used to determine described technic index.Use individual digit (such as described integrated thickness number) to determine that described technic index provides quick relatively technology.
The invention provides technic index and test, current material and cheap, quick and accurate is used in described technic index test.Need the test of the wafer behind the patterning not handy, because they do not satisfy these standards.
Another embodiment of the invention can be used for " scanning " process system (regime).For example, after the etching with inconsistent CD is provided in the technology of wafer, and want to know when which process system has more consistent state, can use a large amount of process system of an embodiment of the invention scanning, compare the use patterned wafer, faster also considerably cheaper.
Other execution mode of the present invention is used to substitute because any former thereby need the test of the wafer of patterning, and wherein these execution modes can use the wafer of more cheap (that is pattern-free) rather than more expensive wafer (that is patterned wafer).
In another embodiment, pattern-free deposition can be finished on a wafer and the pattern-free etching can be finished on another pattern-free wafer.The measurement result of two wafers can combine and as technic index.
Although this invention is described according to several preferred implementations, yet there is the change fall into scope of the present invention, displacement and variously is equal to replacement.Shall also be noted that the alternative of many realizations method and apparatus of the present invention.Therefore, claims are intended to be read as and comprise all these changes, displacement and variously be equal to replacement, all fall in true spirit of the present invention and the scope.
Claims (18)
1. one kind for etching chamber provides the method for technic index, comprises:
A) wafer that will have a pattern-free etch layer is provided in the described etching chamber;
B) described pattern-free etch layer is carried out the pattern-free etching;
C) after the etching of described execution pattern-free is finished, deposition pattern-free sedimentary deposit above described pattern-free etch layer;
D) measure the thickness of described pattern-free etch layer and the thickness of described pattern-free sedimentary deposit; And
E) use the thickness that measures to determine technic index.
2. method according to claim 1, the thickness that wherein said use measures determine that technic index provides in conjunction with a plurality of thickness to obtain the integrated thickness number.
3. method according to claim 1, the thickness of the described pattern-free etch layer of wherein said measurement and the thickness of described pattern-free sedimentary deposit are measured a plurality of thickness at a plurality of diverse locations, and wherein use the thickness measure comprise utilization described a plurality of different position measurements to a plurality of thickness space diagram is provided.
4. method according to claim 3, the thickness that wherein said use measures determines that technic index compares described thickness that measures and standard, and further comprise fine setting described etching chamber and repeating step a-e, up to the desired value of processor in threshold range.
5. method according to claim 4, wherein said fine setting has increased the spatial symmetry of the described thickness that measures.
6. method according to claim 5 further comprises:
After described technic index value is in described threshold range, the wafer of patterning is provided in the described etching chamber; And
The wafer of the described patterning of etching.
7. method according to claim 6, wherein said standard are to produce from the thickness of the measurement of the device that is different from described etching chamber.
8. method according to claim 6, wherein said pattern-free etch layer is a silicon oxide layer.
9. method according to claim 3 is at least 49 thickness from least 49 diverse locations at described a plurality of thickness of a plurality of diverse locations wherein.
10. method according to claim 3, wherein said technic index provides fault detect.
11. method according to claim 3, wherein said technic index provide the technology calibration.
12. method according to claim 1, the thickness that wherein said use measures determines that technic index compares described thickness that measures and standard, and further comprise fine setting described etching chamber and repeating step a-e, up to the technic index value in threshold range.
13. method according to claim 12, wherein said fine setting has increased the spatial symmetry of the described thickness that measures.
14. method according to claim 13 further comprises:
After described technic index value is in described threshold range, the wafer of patterning is provided in the described etching chamber; And
The wafer of the described patterning of etching.
15. method according to claim 14, wherein said standard are to produce from the thickness of the measurement of another etching chamber.
16. method according to claim 14, wherein said pattern-free etch layer is a silicon oxide layer.
17. a method that forms characteristic of semiconductor comprises:
A) wafer that will have a pattern-free etch layer is provided in the described etching chamber;
B) described pattern-free etch layer is carried out the pattern-free etching;
C) after the etching of described execution pattern-free is finished, deposition pattern-free sedimentary deposit above described pattern-free etch layer;
D) measure the thickness of described pattern-free etch layer and the thickness of described pattern-free sedimentary deposit;
E) use the thickness of described measurement to determine technic index;
F) if described technic index is finely tuned described etching chamber outside threshold value;
G) repeating step a-f, up to the technic index value in threshold range;
H) after described technic index value is in described threshold range, the wafer of patterning is provided in the described etching chamber; And
I) wafer of the described patterning of etching is to form characteristic of semiconductor.
18. one kind for etching chamber provides the method for technic index, comprises:
A) first wafer that will have a pattern-free etch layer is provided in the described etching chamber;
B) described pattern-free etch layer is carried out the pattern-free etching;
C) remove described first wafer from described etching chamber;
D) second wafer is provided in the described etching chamber;
E) deposition pattern-free sedimentary deposit above described second wafer;
F) thickness of the described pattern-free etch layer of described first wafer of measurement;
G) thickness of the described pattern-free sedimentary deposit of described second wafer of measurement; And
E) use the thickness of described measurement to determine technic index.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/638,697 | 2009-12-15 | ||
| US12/638,697 US8206996B2 (en) | 2006-03-28 | 2009-12-15 | Etch tool process indicator method and apparatus |
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| CN107728589B (en) * | 2017-09-25 | 2019-11-15 | 华南理工大学 | A kind of on-line monitoring method of flexibility IC substrate etch developing process |
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| KR20040025945A (en) * | 2002-09-17 | 2004-03-27 | 아남반도체 주식회사 | Method for forming flash memory cell |
| CN1886823A (en) * | 2003-09-26 | 2006-12-27 | 兰姆研究有限公司 | Etch with ramping |
| CN101197258A (en) * | 2006-11-22 | 2008-06-11 | 朗姆研究公司 | Method for multi-layer resist plasma etch |
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| FR2801422B1 (en) * | 1999-11-23 | 2002-02-22 | Mhs | METHOD AND DEVICE FOR MONITORING THE THICKNESS OF A LAYER OF AN INTEGRATED CIRCUIT IN REAL TIME |
| US7482178B2 (en) * | 2003-08-06 | 2009-01-27 | Applied Materials, Inc. | Chamber stability monitoring using an integrated metrology tool |
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|---|---|---|---|---|
| KR20040025945A (en) * | 2002-09-17 | 2004-03-27 | 아남반도체 주식회사 | Method for forming flash memory cell |
| CN1886823A (en) * | 2003-09-26 | 2006-12-27 | 兰姆研究有限公司 | Etch with ramping |
| CN101197258A (en) * | 2006-11-22 | 2008-06-11 | 朗姆研究公司 | Method for multi-layer resist plasma etch |
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| TWI525696B (en) | 2016-03-11 |
| CN103531428B (en) | 2016-06-08 |
| KR101759745B1 (en) | 2017-07-19 |
| CN102142385B (en) | 2013-11-20 |
| CN103531428A (en) | 2014-01-22 |
| KR20110068914A (en) | 2011-06-22 |
| TW201131646A (en) | 2011-09-16 |
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