TWI524549B - A photoelectronic element and the manufacturing method thereof - Google Patents

Description

Photoelectric element and method of manufacturing same

The present invention relates to a photovoltaic element, and more particularly to a photovoltaic element having a composite substrate.

Photoelectric elements include many types, such as light-emitting diodes (LEDs), solar cells (Solar cells), and photodiodes (Photo diodes). Taking an LED as an example, the LED is a solid-state semiconductor device including at least a p-n junction formed between the p-type and n-type semiconductor layers. When a certain degree of bias is applied to the p-n junction, the holes in the p-type semiconductor layer combine with the electrons in the n-type semiconductor layer to emit light. This region of light generation is also commonly referred to as the light-emitting region.

The main features of LEDs are small size, high luminous efficiency, long life, fast response, high reliability and good chromaticity. They have been widely used in electrical appliances, automobiles, signboards and traffic signs. With the advent of full-color LEDs, LEDs have gradually replaced traditional lighting devices such as fluorescent lights and incandescent light bulbs.

The above-mentioned photovoltaic element may be further connected to a substrate via a solder bump or a glue material to form a light-emitting device or a light-absorbing device. In addition, the pedestal has at least A circuit electrically connecting the electrodes of the light emitting device or the light absorbing device via a conductive structure, such as a metal wire.

According to a first embodiment of the present invention, a photovoltaic element includes an electrically insulating substrate; a conductive substrate including a portion of the electrically insulating substrate; a semiconductor laminate; and a bonding layer on the electrically insulating substrate and the Between the semiconductor layers.

10, 20, 30, 40, 50‧‧‧ composite substrate

101‧‧‧ cavity

102, 202, 302, 402, 502‧‧‧Electrically insulated substrates

103‧‧‧First reflective layer

104, 204, 304, 404, 504‧‧‧Intermediary

105‧‧‧Adsorption layer

106, 206, 306, 406, 506‧‧‧ conductive substrate

107, 207, 307, 407‧‧‧ contact surfaces

12, 22, 32, 42, 52‧‧ ‧ adhesive layer

122, 222, 322, 422, 522‧‧‧ conductive areas

124, 224, 324, 424, 524‧‧ Electrically insulating areas

126‧‧‧Top surface of conductive area

13, 23, 53‧‧‧ current barrier

132‧‧‧The upper surface of the current blocking layer

14, 24, 34, 44, 54‧‧‧ first current diffusion layer

15, 25, 35, 45, 55‧‧‧second current diffusion layer

152‧‧‧Under the surface of the second current diffusion layer

16, 26, 36, 46, 56‧‧‧ first semiconductor stack

162, 262, 362, 462, 562‧‧‧ first semiconductor layer

164, 264, 364, 464, 564‧‧‧ first active layer

166, 266, 366, 466, 566‧‧‧ second semiconductor layer

17, 27, 37, 47, 57‧‧‧ first electrode

172‧‧‧The lower surface of the first electrode

21, 31, 51‧‧ ‧ window layer

368, 568‧‧‧ high energy gap area

43‧‧‧Second reflective layer

48‧‧‧ Third current diffusion layer

49‧‧‧Second semiconductor stack

58‧‧‧second electrode

59‧‧‧through hole

6‧‧‧Light source generating device

61‧‧‧Light source

62‧‧‧Power supply system

63‧‧‧Control elements

7‧‧‧Backlight module

71‧‧‧Optical components

The drawings are intended to facilitate an understanding of the invention and are part of the specification. The embodiments of the drawings are described in conjunction with the embodiments to explain the principles of the invention.

1A-1G is a cross-sectional view of a manufacturing process in accordance with a first embodiment of the present invention.

Fig. 2A is a cross-sectional view showing a second embodiment of the present invention.

Fig. 2B is a cross-sectional view showing a third embodiment of the present invention.

Figure 3 is a cross-sectional view showing a fourth embodiment of the present invention.

Figure 4 is a cross-sectional view showing a fifth embodiment of the present invention.

Fig. 5A is a cross-sectional view showing a sixth embodiment of the present invention.

Fig. 5B is a cross-sectional view showing a seventh embodiment of the present invention.

Figure 5C is a cross-sectional view showing an eighth embodiment of the present invention.

Figure 6 is a schematic view showing a schematic diagram of a light source generating apparatus constructed using an embodiment of the present invention.

Figure 7 is a schematic diagram showing one of the embodiments of the present invention. A schematic diagram of a backlight module.

The embodiments of the present invention are described in detail, and in the drawings, the same or similar

1A-1G is a cross-sectional view showing a manufacturing process of the first embodiment, wherein the first A-1C is a cross-sectional view showing a manufacturing process of the composite substrate 10 included in the photovoltaic element shown in Fig. 1G. As shown in FIG. 1C, the composite substrate 10 has an electrically insulating substrate 102, a conductive substrate 106 and an interposer 104 formed between the electrically insulating substrate 102 and the electrically conductive substrate 106. As shown in FIG. 1A, an electrically insulating substrate 102 having a cavity 101 is formed. The cavity 101 is formed in the electrically insulating substrate 102, and a portion of the electrically insulating substrate 102 is removed to form a space surrounded by its exposed inner wall. . The method of forming the cavity 101 includes etching or laser stripping. As shown in FIG. 1B, an interposer 104 is formed under the electrically insulating substrate 102 and between the cavity 101 and the electrically insulating substrate 102. The interposer 104 includes an adsorption layer 105 under the electrically insulating substrate 102 and the cavity 101. Between the electrically insulating substrate 102 and a first reflective layer 103 is disposed between the electrically insulating substrate 102 and the adsorption layer 105. As shown in FIG. 1C, a conductive substrate 106 is formed under the interposer 104 to form a composite substrate 10 in which one portion of the conductive substrate 106 is located in the cavity 101. Next, as shown in FIG. 1D-1E, a bonding layer 12 is formed on the composite substrate 10, wherein the bonding layer 12 includes a conductive region 122 on the conductive substrate 106 to form an electrical connection with the conductive substrate 106; An electrically insulating region 124 is disposed over the electrically insulating substrate 102, surrounding and adjacent to the electrically conductive region 122, and is in direct contact with the electrically insulating substrate 102. The adjacent fingers are in direct contact with the sides of the electrically conductive region 122. A first current spreading layer 14 is formed over the bonding layer 12. As shown in FIG. 1F-1G, a first semiconductor stack 16 is formed over the first current spreading layer 14, wherein the first semiconductor stack 16 includes a first semiconductor layer 162. Above the first current diffusion layer 14; a first active layer 164 is over the first semiconductor layer 162; and a second semiconductor layer 166 is over the luminescent layer 164. A current blocking layer 13 is formed over the first semiconductor stack 16, wherein the current blocking layer 13 is located at a position where the conductive region 122 is located upward; a second current spreading layer 15 is formed on the first semiconductor stack 16 and current blocking Above the layer 13, and covering the current blocking layer 13; and a first electrode 17 is formed on the second current diffusion layer 15, wherein the first electrode 17 is located at a position where the conductive region 122 is located upward, above the conductive region 122 The area of surface 126 is preferably no greater than the area of lower surface 172 of first electrode 17.

The electrically insulating substrate 102 is used to support the semiconductor structure located thereon, and the material thereof can be an electrically insulating material with a high energy gap, such as Sapphire, Diamond, Glass, Quartz, and Acrylic. Acryl, zinc oxide (ZnO) or aluminum nitride (AlN). The first reflective layer 103 may be a material having high reflectivity, such as copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum (Pt), zinc (Zn), Silver (Ag), titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), nickel (Ni), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn),锑(Sb), bismuth (Bi), gallium (Ga), strontium (Tl), arsenic (As), selenium (Se), strontium (Te), strontium (Po), strontium (Ir), strontium (Re), Rh (Rh), bismuth (Os), tungsten (W), lithium (Li), sodium (Na), potassium (K), bismuth (Be), magnesium (Mg), calcium (Ca), strontium (Sr), Ba (Ba), Zr (Zr), Mo (Mo), La (La), Cu-Sn, Cu-Zn, Cu-Cd, Tin-Lead -锑(Sn-Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co) or gold alloy (Au alloy), etc. The light generated by the foreign or first active layer 164 is reflected. The adsorption layer 105 can be used to assist the adhesion and deposition of the plating material, and can be a conductive material such as copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum ( Pt), zinc (Zn), silver (Ag), titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), nickel (Ni), chromium (Cr), cadmium (Cd), cobalt ( Co), manganese (Mn), strontium (Sb), bismuth (Bi), gallium (Ga), strontium (Tl), arsenic (As), selenium (Se), strontium (Te), strontium (Po), strontium (Po) Ir), 铼 (Re), 铑 (Rh), 锇 (Os), tungsten (W), lithium (Ii), Sodium (Na), potassium (K), strontium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), lanthanum (La), Cu-Sn, Cu-Zn, Cu-Cd, Sn-Pb-Sb, Tin-Pb-Sb, Sn-Pb- Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co) or gold alloy (Au alloy). The conductive substrate 106 can support the electrically insulating substrate 102 and the semiconductor structure thereon, and help to conduct heat or conduct. The material comprises copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum ( Pt), zinc (Zn), silver (Ag), titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), nickel (Ni), chromium (Cr), cadmium (Cd), cobalt ( Co), manganese (Mn), strontium (Sb), bismuth (Bi), gallium (Ga), strontium (Tl), arsenic (As), selenium (Se), strontium (Te), strontium (Po), strontium (Po) Ir), ruthenium (Re), rhodium (Rh), osmium (Os), tungsten (W), lithium (Li), sodium (Na), potassium (K), bismuth (Be), magnesium (Mg), calcium ( Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), lanthanum (La), copper-tin (Cu-Sn), copper-zinc (Cu-Zn), copper-cadmium ( Cu-Cd), tin-lead-bismuth (Sn-Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co), gold Alloy, AuSn, InAg, InAu, AuBe, AuGe, AuZn, Tin Lead (PbSn) or indium palladium (PdIn). The method of forming the conductive substrate 106 includes an electroplating method. In addition, the material of the composite substrate 10 may also include copper (Cu), aluminum (Al), metal, composite materials, metal matrix composite (MMC), ceramic matrix composite (CMC), and germanium. (Si), phosphine oxide (IP), zinc selenide (ZnSe), aluminum nitride (AlN), gallium arsenide (GaAs), tantalum carbide (SiC), gallium phosphide (GaP), gallium arsenide ( GaAsP), zinc selenide (ZnSe), zinc oxide (ZnO), indium phosphide (InP), lithium gallate (LiGaO2) or lithium aluminate (LiAlO2).

The conductive region 122 is a material capable of conducting and bonding, such as indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti) ), lead (Pb), palladium (Pd), germanium (Ge), copper (Cu), nickel (Ni), gold (AuSn), indium (InAg), indium (InAu), antimony AuBe, AuGe, AuZn, PbSn or PdIn to conduct current And bonding the composite substrate 10 to the semiconductor structure thereon. The electrically insulating region 124 is a material having high energy gap and can be electrically insulated and bonded, such as a dielectric material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), Acrylic Resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyether quinone ( Polyetherimide), Fluorocarbon Polymer, Silicone, Glass, Al2O3, SiO2, TiO2, SiNx, Spin-on Glass (SOG), Tetraethyl orthosilane (TEOS) or other organic bonding material to modify the current path and bond the composite substrate 10 to the semiconductor structure thereon. The first current diffusion layer 14 and the second current diffusion layer 15 may be materials having a low lateral resistance, which facilitate current lateral diffusion, including indium tin oxide (ITO), indium oxide (InO), and tin oxide (SnO). , cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc oxide (ZnO), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), Gallium phosphide (GaP), gallium arsenide (GaAs), gallium arsenide (GaAsP), indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), zinc (Zn ), silver (Ag), titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), copper (Cu), nickel (Ni), indium (InAg), indium (InAu) , AuBe, AuGe, AuZn, PbSn, PdIn or AuSn, the structure can be single layer or Laminated structure. The first active layer 164 of the first semiconductor stack 16 can absorb or generate light, and the first semiconductor layer 162 and the second semiconductor layer 166 are electrically different, and the material includes one or more substances selected from the group consisting of gallium (Ga), Aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), zinc (Zn), cadmium (Cd), selenium (Se), antimony (Sb), cadmium (Cd),鍗(Te), mercury (Hg), sulfur (S), hydrogen (H), magnesium (Mg), tin (Sn), boron (B), lead (Pb), carbon (C) and bismuth (Si) The group that makes up. The second semiconductor layer 166 may optionally include a rough upper surface under the second current diffusion layer 15. The current blocking layer 13 can be high power Resistive materials, such as dielectric materials, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), Polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, silicone (Silicone) ), Glass, Al2O3, SiO2, TiO2, SiNx, SOG, Tetraethyl Orthosilane (TEOS) or Other organic materials, etc., to change the current path of the photovoltaic element. The first electrode 17 may be a metal material such as copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), Titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), nickel (Ni), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn), antimony (Sb),铋 (Bi), gallium (Ga), strontium (Tl), arsenic (As), selenium (Se), strontium (Te), strontium (Po), strontium (Ir), strontium (Re), argon (Rh), Os, tungsten (W), lithium (Li), sodium (Na), potassium (K), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), Zirconium (Zr), molybdenum (Mo), lanthanum (La), copper-tin (Cu-Sn), copper-zinc (Cu-Zn), copper-cadmium (Cu-Cd), tin-lead-bismuth (Sn- Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co) or Au alloy, etc., to accept an external voltage.

As shown in FIG. 1G, the first electrode 17 and the current blocking layer 13 are both located above the conductive region 122, preferably where the conductive region 122 extends upward. The area of the upper surface 132 of the current blocking layer 13 is preferably not less than the area of the lower surface 172 of the first electrode 17 or the upper surface 126 of the conductive region 122, and is not larger than the area of the lower surface 152 of the second current diffusion layer 15. . The conductive substrate 106 includes a contact surface 107 in direct contact with the conductive region 122, wherein the contact surface 107, the current blocking layer 13, the conductive region 122, and the first electrode 17 may have a patterned structure of the same or different patterns. The conductive region 122 can be a single conductive region, for example, the only region of the adhesive layer 12 formed of a conductive material, located at or below the position where the first electrode 17 is located, And in direct contact with the contact surface 107.

Since the conductive substrate 106 is a material having high thermal conductivity, the thermal conduction rate of the photovoltaic element can be increased, and the reliability and luminous efficiency of the photovoltaic element can be improved. In addition, the electrical connection between the conductive region 122 and the conductive substrate 106 allows the current of the photovoltaic element to be vertically turned on; and the electrically insulating region 124 having a higher energy gap and the electrically insulating substrate 102 are combined to avoid light absorption. The current blocking layer 13 is located at or below the position where the first electrode 17 is located downward, so that current flows to a region not covered by the current blocking layer 13, and the first semiconductor layer 16 is prevented from being lighted in a region below the first electrode 17, reducing The probability of the first electrode 17 absorbing light.

2A is a cross-sectional view showing a structure of a second embodiment. The second embodiment is similar to the first embodiment and includes a composite substrate 20. The composite substrate 20 includes an electrically insulating substrate 202, an interposer 204 and a The conductive substrate 206; a bonding layer 22, comprising a conductive region 222 and an electrically insulating region 224; a first current diffusion layer 24; a first semiconductor layer 26 comprising a first semiconductor layer 262, a first active layer 264 and a second semiconductor layer 266; a current blocking layer 23; a second current spreading layer 25; and a first electrode 27. The second embodiment differs from the first embodiment in that the second embodiment further comprises a window layer 21 between the first semiconductor stack 26 and the first current spreading layer 24. Because the refractive index of the window layer 21 is different from that of the first semiconductor stack 26, light scattering can be caused to enhance light extraction efficiency. The material of the window layer 21 comprises indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide ( ZTO), zinc oxide (ZnO), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs) or gallium arsenide (GaAsP). In addition, the window layer 21 can optionally include a rough lower surface located between the window layer 21 and the first current spreading layer 24. 2B is a cross-sectional view showing a structure of a third embodiment, and the third embodiment is similar to the second embodiment, and the difference is The current blocking layer 23 is located between the first current diffusion layer 24 and the window layer 21 and is covered by the window layer 21. The conductive substrate 206 includes a contact surface 207 in direct contact with the conductive region 222, wherein the contact surface 207, the current blocking layer 23, the conductive region 222, and the first electrode 27 may have patterned structures of the same or different patterns.

As shown in FIG. 3, a fourth embodiment is similar to the second embodiment, and includes a composite substrate 30. The composite substrate 30 includes an electrically insulating substrate 302, an interposer 304 and a conductive substrate 306, and a bonding layer 32. A conductive region 322 and an electrically insulating region 324; a first current diffusion layer 34; a first semiconductor layer 36 comprising a first semiconductor layer 362, a first active layer 364 and a second semiconductor layer 366 a second current spreading layer 35; and a first electrode 37. The difference is that there is no current blocking layer in the fourth embodiment, and the first active layer 364 includes a high energy gap region 368, which is a high resistance region, which can change the current path in the photovoltaic element. The high energy gap region 368 is located at or below the position where the first electrode 37 is located downward, so that current flows to a region other than the high energy gap region 368, and the high energy gap region 368 is prevented from generating light to reduce the probability of the first electrode 17 absorbing light. The conductive substrate 306 includes a contact surface 307 that is in direct contact with the conductive region 322, wherein the contact surface 307, the conductive region 322, the high energy gap region 368, and the first electrode 37 may have patterned structures of the same or different patterns.

The method of forming the high energy gap region 368 includes directly heating a specific region of the first active layer 364 with a laser, and forming a high energy gap region 368 after changing the composition of the specific region. Alternatively, the second semiconductor layer 366 is heated by laser, and heat is re-conducted to a specific region of the first active layer 364 to change its composition. The high energy gap region 368 is located at or below the downward extension of the location at which the first electrode 37 is located.

As shown in FIG. 4, a fifth embodiment is similar to the fourth embodiment, and includes a composite substrate 40, wherein the composite substrate 40 includes an electrically insulating substrate 402, an interposer 404 and a guide. An electrical substrate 406; a bonding layer 42 comprising a conductive region 422 and an electrically insulating region 424; a first current spreading layer 44; a first semiconductor stack 46 comprising a first semiconductor layer 462, a first active layer 464 and a second semiconductor layer 466; a second current diffusion layer 45; and a first electrode 47. The difference is that the fifth embodiment does not have a high energy gap region, but further includes a second reflective layer 43 between the composite substrate 40 and the bonding layer 42. A second semiconductor laminate 49 includes at least a second active layer (not Displayed between the second reflective layer 43 and the bonding layer 42; and a third current spreading layer 48 between the second semiconductor stack 49 and the bonding layer 42. The conductive substrate 406 includes a contact surface 407 that is in direct contact with the second reflective layer 43, wherein the contact surface 407, the conductive region 422, and the first electrode 47 may have a patterned structure of the same or different patterns.

The second reflective layer 43 may be a material having high reflectivity, such as copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum (Pt), zinc (Zn), Silver (Ag), titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), nickel (Ni), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn),锑(Sb), bismuth (Bi), gallium (Ga), strontium (Tl), arsenic (As), selenium (Se), strontium (Te), strontium (Po), strontium (Ir), strontium (Re), Rh (Rh), bismuth (Os), tungsten (W), lithium (Li), sodium (Na), potassium (K), bismuth (Be), magnesium (Mg), calcium (Ca), strontium (Sr), Ba (Ba), Zr (Zr), Mo (Mo), La (La), Cu-Sn, Cu-Zn, Cu-Cd, Tin-Lead -锑(Sn-Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co) or gold alloy (Au alloy), etc. Reflecting light generated by the first active layer 464 or the second active layer or from the outside. The second semiconductor stack 49 can generate or absorb light, and optionally includes a rough upper surface, the material of which includes one or more substances selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), and arsenic. (As), phosphorus (P), nitrogen (N), zinc (Zn), cadmium (Cd), selenium (Se), antimony (Sb), cadmium (Cd), antimony (Te), mercury (Hg), sulfur (S), hydrogen (H), magnesium (Mg), tin (Sn), boron (B), lead (Pb), carbon (C) and bismuth (Si). The third current diffusion layer 48 may be a material having a low lateral resistance, so that the current is more easily diffused laterally. Indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), oxidation Zinc (ZnO), AlGaAs, AlGaN, GaN, GaP, GaAs, GaAs, GaAs, Sn ) aluminum, Al, platinum, Pt, zinc, Zn, Zn, Pb, Pd, Pd ), nickel (Ni), indium (InAg), indium (InAu), gold (AuBe), gold (AuGe), gold (AuZn), lead (PbSn), indium Palladium (PdIn) or gold-plated gold (AuSn), which may have a single layer or a stacked structure. Since the first semiconductor stack 46 and the second semiconductor stack 49 can also absorb light, they can be applied to a photo sensor or a solar cell.

As shown in FIG. 5A, a sixth embodiment is similar to the second embodiment, and includes a composite substrate 50, wherein the composite substrate 50 is an electrically insulating substrate 502, an interposer 504 and a conductive substrate 506, and a bonding layer 52. The first semiconductor layer 56 includes a first semiconductor layer 562, a first active layer 564 and a first semiconductor layer 562. a semiconductor layer 566; a current blocking layer 53; a second current spreading layer 55; and a first electrode 57. The difference is that the sixth embodiment further includes a second electrode 58 disposed on the first semiconductor layer 562, connected to the first current diffusion layer 54 via a through hole 59, and the conductive region 522 is electrically connected to the conductive substrate 506. . The first electrode 57 and the second electrode 58 are located on the same side of the composite substrate 50 to form a horizontal photovoltaic element. In addition, the conductive region 522, the current blocking layer 53 and the first electrode 57 have a patterned structure of the same or different patterns. As shown in FIG. 5B, the seventh embodiment is similar to the sixth embodiment except that the current blocking layer 53 is located between the first current diffusion layer 54 and the window layer 51, and is covered by the window layer 51. As shown in FIG. 5C, the eighth embodiment is similar to the sixth embodiment except that the photovoltaic element has no current blocking layer 53, but the first active layer 564 further includes a high energy gap region 568 at the position of the first electrode 57. The downward extension or below. The conductive region 522, the high energy gap region 568 and the first electrode 57 have a patterned structure of the same or different patterns. The patterned structure may be a continuous pattern, such as a circle having at least one protrusion.

Figure 6 is a schematic diagram showing a light source generating device. The light source generating device 6 includes a die which is formed by cutting a photovoltaic structure of a wafer in any of the embodiments of the present invention. The light source generating device 6 may be a lighting device, such as a street light, a car light, or an indoor lighting source, or may be a traffic signal or a backlight source of a backlight module in a flat display. The light source generating device 6 comprises a light source 61 of the aforementioned photovoltaic element; a power supply system 62 for supplying a current to the light source 61; and a control element 63 for controlling the power supply system 62.

FIG. 7 is a cross-sectional view showing a backlight module. The backlight module 7 includes the light source generating device 6 of the foregoing embodiment, and an optical element 71. The optical element 71 can process the light emitted by the light source generating device 6 to be applied to a flat display such as the light emitted by the scattered light source generating device 6.

The above-described embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is as set forth in the appended claims.

10‧‧‧Composite substrate

102‧‧‧Electrically insulating substrate

104‧‧‧Intermediary

106‧‧‧Electrical substrate

107‧‧‧Contact surface

12‧‧‧Bonded layer

122‧‧‧Conducting area

124‧‧‧Electrical insulation zone

126‧‧‧Top surface of conductive area

13‧‧‧current barrier

132‧‧‧The upper surface of the current blocking layer

14‧‧‧First current diffusion layer

15‧‧‧Second current diffusion layer

152‧‧‧Under the surface of the second current diffusion layer

16‧‧‧First semiconductor stack

162‧‧‧First semiconductor layer

164‧‧‧Lighting layer

166‧‧‧second semiconductor layer

17‧‧‧First electrode

172‧‧‧The lower surface of the first electrode

Claims (10)

A photovoltaic element comprising: an insulating substrate having a surface; a conductive substrate comprising a portion disposed in the same and coplanar with the surface; a semiconductor stack; and a bonding layer on the insulating substrate and the semiconductor Between the layers. The photovoltaic device of claim 1, wherein the insulating substrate comprises a cavity exposing the conductive substrate. The photovoltaic device according to claim 1, further comprising an interposer between the insulating substrate and the conductive substrate. The photovoltaic device of claim 3, wherein the interposer further comprises a first reflective layer under the insulating substrate. The photovoltaic element according to claim 4, further comprising a second reflective layer formed on the first reflective layer, and the second reflective layer being located between the semiconductor laminate and the insulating substrate. The photovoltaic device according to claim 1, further comprising an adsorption layer between the insulating substrate and the conductive substrate. The photovoltaic element of claim 1 further comprising a window layer between the bonding layer and the semiconductor laminate, and the window layer comprises a rough lower surface. The photovoltaic device of claim 1, wherein the bonding layer comprises a conductive region and an electrically insulating region. The photovoltaic element of claim 8, wherein the conductive region corresponds to a location of the portion of the conductive substrate in the insulating substrate. The photovoltaic element according to claim 8, wherein the electrically insulating region corresponds to an insulating substrate The location of the board.