TWI521511B - Split page 3d memory array - Google Patents

Description

Paging three-dimensional memory array

The present invention relates to high density memory devices, and more particularly to memory devices in which a plurality of planar memory cells are arranged to provide a three dimensional array.

The high density memory device is designed to include multiple arrays of flash memory cells or other types of memory cells. In some examples, the memory cell includes a plurality of thin film transistors that can be configured in a three dimensional architecture.

In one example, a three-dimensional memory device includes a plurality of stacked NAND string memory cells. These stacks include a plurality of active strips separated by an insulating material. The three-dimensional memory device includes an array including a plurality of word line structures, a plurality of serial selection structures, and a plurality of ground selection lines disposed orthogonally on the stack. A memory cell comprising a charge storage structure is formed at an intersection between a side surface of the active strip and a word line structure in a plurality of stacks. The array configuration of the array elements including the tandem selection structure can affect the efficiency of the array and/or the on/off characteristics of the three-dimensional memory device stack of the gate train.

A three-dimensional memory device uses a finger-shaped vertical gate (VG), and It has a relatively low array efficiency due to the use of two sets of SSL gate structures, two horizontal ground selection lines, and two sets of ground contacts for the three dimensional memory device. Another three-dimensional memory device uses independent double gates (IDG) and has higher array efficiency because the three-dimensional memory device uses a set of SSL gate structures instead of two groups, one level Ground select lines instead of two and one ground line instead of two sets of ground contacts. However, such three-dimensional memory devices exhibit relatively poor current conduction/non-conduction characteristics.

A related method is shown in the related U.S. Patent Application Serial No. 13/887,019, in which the independent double gates control the conductivity at one of the ends of the anti-gate column memory cells. In this method, a separate gate is placed between each adjacent pair of these inverted gate bank memory cells. Since the number of independent gates and the number of these reverse gate bank memory cells are substantially one-to-one correspondence, the pitch requirements on the junctions of the individual gates are quite strict.

Another method is a "twisting" selection configuration in which adjacent selection structures are staggered at the same end of the stack along the length of the anti-gate column memory cell stack. While this configuration has relatively relaxed spacing requirements for the contacts of the "twisted" selection structure, staggering along the length of the counter-serial column memory cells requires more space.

It is desirable to provide a three-dimensional integrated circuit memory structure with higher array efficiency and improved on/off characteristics of the anti-gate column stack.

One embodiment of the present invention is an integrated circuit having a memory array, comprising: a plurality of memory cells having a plurality of active strip stacks of the memory array, a plurality of active strip stack selection structures, and a control circuit.

The active strip stack has a first end and a second end. A first pad is in contact with the first end of the one or more active strip stacks. A second pad is in contact with the second end of the one or more active strip stacks.

The active strip stack selection structure is electrically coupled to the active strip stack at a position between the first end and the second end.

The control circuit is coupled to the first pad and the second pad. The control circuit responds by receiving a first command to read a first group of memory cells on the memory array by applying a first set of read voltages to the first pad and the second pad, so that the first A pad has a higher voltage than the second pad. The control circuit responds by receiving a second command to read a second set of memory cells on the memory array by applying a second set of read voltages to the first pad and the second pad to enable The second pad has a higher voltage than the first pad. Therefore, whether the first pad or the second pad has a high read voltage depends on whether the memory cell that is being read is located in the first group or the second group of memory cells.

In one embodiment of the invention, the first set of voltages includes a bit line voltage applied to the first pad and a source line voltage applied to the second pad. The second set of voltages includes a bit line voltage applied to the second pad and a source line voltage applied to the first pad. Therefore, depending on whether the memory cell receiving the reading is in the first group or the second group of memory cells, the source line voltage and the bit line voltage are applied to Different pads.

In an embodiment of the present invention, the active strip stack selection structure includes: a first set of active strip stack selection structures, located on a first side of one of the plurality of word lines; and a second set of active strip stack selection structures , located on the second side of one of the plurality of character lines. The active strip stack selection structure selects a particular stack of active strips for operations such as reading, erasing, and stylizing.

In one embodiment of the invention, the first set of voltages includes a tandem select line voltage applied to at least one of the first set of active strip stack selection structures, and at least one applied to the second set of active strip stack selection structures One of the ground selects a line voltage, and the second set of voltages includes a tandem select line voltage applied to at least one of the second set of active strip stack selection structures, and at least one applied to the first set of active strip stack selection structures Ground selection line voltage. Therefore, depending on whether the memory cell receiving the read is in the first group or the second group of memory cells, the tandem select line voltage and the ground select line voltage are applied to different active strip stack selection structures.

An embodiment of the invention includes a first plurality of metal lines for transmitting one of (i) a plurality of serial select line signals and (ii) a plurality of ground select line signals to the first set of active strip stacks And selecting a structure; and a second plurality of metal lines for transmitting (i) the plurality of serial select line signals and (ii) the plurality of ground select line signals to the second set of active strip stack selection structures. The first plurality of metal lines and the second plurality of metal lines are on the same metal layer.

In one embodiment of the present invention, the plurality of active strip stacks comprise one of the first set of active strip stacks and one of the second set of active strip stacks interleaved with each other. First group The active strip stack is electrically coupled to the first pad and electrically decoupled from the second pad. The second set of active strips is electrically coupled to the second pad and electrically decoupled from the first pad.

Another embodiment of the present invention is an integrated circuit having a memory array comprising: a plurality of memory cells having a plurality of active strip stacks of the memory array, and a plurality of active strip stack selection structures.

The active strip stack selection structure is electrically coupled to the active strip stack at a position between the first end and the second end. The active strip stack selection structure selects a particular stack of active strips for operations such as reading, erasing, and stylizing. The active strip stack selection structure is a double gate structure and includes a first set of active strip stack selection structures located on one of the first sides of the plurality of word lines, and a second side of one of the plurality of word lines One of the second set of active strip stack selection structures.

Each active strip stack of the plurality of active strip stacks has: (i) a first active strip stack selection structure from the first set of active strip stack selection structures for each of the first side of the plurality of character line lines And first (ii) a second active strip stack selection structure and a third active strip stack selection structure, and the second active strip stack selection structure is respectively used for The third and fourth side gates on each of the active strip stacks on the second side of the plurality of word line lines.

In some embodiments of the invention, adjacent active strip stacks have opposite runs. The first one of the adjacent active strip stacks has a single stack selection structure to a plurality of stack selection structure orientations from the first end to the second end. The second one of the adjacent active strip stacks has a plurality of stacked selection structures in a direction from the first end to the second end of the plurality of active strip stacks to A single stack selects the structure to go.

In one embodiment of the invention, the first one of the adjacent active strip stacks has a single stack selection structure to a plurality of stack selection structure runs. A plurality of active strip stack selection structures apply a plurality of independent control voltages to a first one of adjacent active strip stacks on a second side of one of the plurality of word lines. The second series of adjacent active strip stacks has a plurality of stacked selection structures to a single stack selection structure. A plurality of active strip stack selection structures apply a plurality of independent control voltages to a second one of the adjacent active strip stacks on a first side of one of the plurality of word lines.

In one embodiment of the invention, the first of the adjacent active strip stacks has a single stack selection structure to a plurality of stack selection structure runs. The plurality of active strip stack selection structures apply only one independent control voltage to the first of the adjacent active strip stacks on the first side of one of the plurality of word lines. The second system of adjacent active strip stacks has a plurality of stack selection structures to a single stack selection structure orientation such that the plurality of active strip stack selection structures apply only one independent control voltage to one of the plurality of word lines. The second of the adjacent active strip stacks on the side.

In one embodiment of the present invention, the first one of the adjacent active strip stacks has a single stack selection structure to a plurality of stack selection structure orientations such that only one first stack selection structure of the plurality of active strip stack selection structures is Electrically coupled to the first one of the adjacent active strip stacks on the first side of the plurality of character line lines, and one of the plurality of active strip stack selection structures, the first plurality of stacked selection structures, The first one of the adjacent active strip stacks coupled to the second side of one of the plurality of word lines. The second of the adjacent active strip stacks has a plurality of stacking options Structure to a single stack selection structure, such that one of the plurality of active strip stack selection structures, the second plurality of stack selection structures, is electrically coupled to adjacent ones of the first side of the plurality of word lines The second one of the plurality of active strip stack selection structures has a second stack selection structure electrically coupled to the second active strip stack of the second side of the plurality of character lines One.

In one embodiment of the invention, the plurality of active strip stacks have a first surface and a second surface on the opposite side along the length of the active strip stack. A plurality of independent control voltages are applied to the first of the adjacent active strip stacks on the second side of one of the plurality of word lines. The plurality of independent control voltages include: a first independent control voltage coupled to the first surface of the first one of the adjacent active strip stacks instead of the second surface; and a second independent control voltage coupled to the adjacent active The second surface of the first stack of strips is stacked instead of the first surface. In another embodiment, a plurality of independent control voltages are applied to the second of the adjacent active strip stacks on the first side of one of the plurality of word lines. The plurality of independent control voltages include: a third independent control voltage coupled to the first surface of the second active strip stack instead of the second surface; and a fourth independent control voltage coupled to the adjacent active The second surface of the second stack of strips is instead of the first surface.

Yet another embodiment of the present invention is an integrated circuit having a memory array comprising: a plurality of memory cells having a plurality of active strip stacks of the memory array and a plurality of active strip stack selection structures.

The active strip stack has a first end and a second end.

The active strip stack selection structure is a bit between the first end and the second end The power is electrically coupled to the active strip stack. The active strip stack selection structure selects a particular stack of active strips for operations such as reading, erasing, and stylizing.

The active strip stack selection structure is positioned to surround the alternating ends of the plurality of active strip stacks. Using adjacent active strip stacks, (i) one of the adjacent active strip stacks first has a first active strip stack selection structure disposed to surround adjacent active strip stacks on one of the first sides of the plurality of word lines The first one, and (ii) the second of the adjacent active strip stacks has a second active strip stack selection structure disposed to surround adjacent active strip stacks on a second side of one of the plurality of word lines the second.

In one embodiment of the invention, the first end of the first one of the adjacent active strip stacks receives a first independent control voltage from one of the plurality of active strip stack selection structures via the first active strip stack selection structure. The first active strip stack selection structure provides a first independent control voltage of the second side of the plurality of word line lines to the active strips of the plurality of active strip stacks adjacent to either side of the first one of the adjacent active strip stacks Stacking. A second end of the second of the adjacent active strip stacks receives a second independent control voltage from one of the plurality of active strip stack selection structures via the second active strip stack selection structure. The second active strip stack selection structure provides a second independent control voltage of the first side of the plurality of character line lines to the active plurality of active strip stacks adjacent to either side of the second active strip stack Strips are stacked.

A further implementation of the present invention is an integrated circuit having a memory array comprising: a plurality of memory cells having a plurality of active strip stacks of the memory array and a plurality of active strip stack selection structures.

The active strip stack has a stack width, and the first end and the second end end. A plurality of active strip stacks are placed adjacent to each other to divide a gap width.

The active strip stack selection structure is electrically coupled to the active strip stack at a position between the first end and the second end. The active strip stack selection structure selects a particular stack of active strips for operations such as reading, erasing, and stylizing. The active strip stack selection structure has a sum greater than (i) stack width and (ii) twice the gap width, and less than i) twice the stack width and (ii) twice the sum of the gap widths.

In one embodiment of the invention, the active strip stack selection structure is designed to be used as a side gate for a channel in a plurality of active strip stacks to form a tandem select switch.

An embodiment of the present invention is a method for operating an integrated circuit having a memory array, comprising: applying a first control voltage to a first active strip stack selection structure, configured to: (i) provide one The first active strip is stacked on the opposite side of the first active strip stack, and the first active strip is stacked between a second active strip stack and a third active strip stack, and (ii) the second active strip stack One of the first side gates is not a second side gate, and (iii) one of the third active strip stacks has a first side gate instead of a second side gate.

In one embodiment of the present invention, the first active strip stack has first and second ends, and the first control voltage is applied to one of the plurality of word lines by the first active strip stack selection structure. The first active strip is stacked on one side, and the method further includes: applying a second control voltage to a second active strip stack selection node The first side gate of one of the second sides of the plurality of word lines is configured instead of a second side gate.

In an embodiment of the invention, the method further includes applying a third control voltage to a third active strip stack selection structure, configured as one of the second side gates of one of the plurality of word lines Instead of a first side gate.

Other embodiments and advantages of the present invention will be apparent from the review of the drawings, the detailed description and the claims.

A'-A"‧‧‧ hatching

BL1 to BL6‧‧‧active strip/active strip stacking

ML1, ML2, ML3‧‧‧ metal layer

SSL0 to SSL7‧‧‧serial selection structure

X, y, z‧‧‧ coordinate axis

102, 103, 104, 105‧ ‧ active strips

102B, 103B, 104B, 105B‧‧‧ solder pads

109‧‧‧SSL gate structure

112, 113, 114, 115‧‧ ‧ active strips

112A, 113A, 114A, 115A‧‧‧ pads

119‧‧‧SSL gate structure

125-1 WL to 125-N WL‧‧‧ character line

126‧‧‧ Grounding selection line

127‧‧‧ Grounding selection line

128‧‧‧ source line

210‧‧‧ solder pads

215‧‧‧ solder pads

230‧‧‧ character line

602, 604, 610, 612, 614, 616, 618, 620, 622, 624‧‧‧ outline

704, 706, 708, 710, 712 ‧ ‧ outline

815, 813, 811 ‧ ‧ active strip

816, 814, 812, 810 ‧ ‧ insulation strip

830, 834, 838‧‧‧ stack width

832‧‧‧ gap width

836‧‧‧ gap width

1058‧‧‧Planar decoder

1059‧‧‧ bit line

1060‧‧‧ memory array

1061‧‧‧ column decoder

1062‧‧‧ character line

1063‧‧‧ line decoder

1064‧‧‧SSL line

1065‧‧‧ Busbar

1066‧‧‧ squares

1067‧‧‧ data bus

1068‧‧‧

1069‧‧‧ bias configuration state machine

1071‧‧‧ data input line

1072‧‧‧ data output line

1074‧‧‧ Circuitry

1075‧‧‧Integrated circuit/semiconductor device

Figure 1 is a perspective view of a three-dimensional inverse gate memory array structure.

Figure 2 is a layout diagram of a first array configuration of one of the page-finger vertical gate three-dimensional and gate memory devices.

Figure 3 is a layout diagram of a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices having a read bias configuration as shown in Figure 2.

Figure 4 is a layout diagram of a first array configuration of one of the finger-shaped vertical gate three-dimensional anti-gate memory devices having another read bias configuration as shown in Figure 2.

Figure 5 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device having a program bias configuration as shown in Figure 2.

Figure 6 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device as shown in Figure 2, the memory device having a stacked outline of a tandem selection line structure ( Superimposed outline) mask.

Figure 7 is a three-dimensional inverse gate memory of the finger vertical gate as shown in Figure 2. A layout of a first array of body devices having a mask with a stack of pads and a stack of active strips.

Figure 8 is a cross-sectional view showing a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2.

Figure 9 is a cross-sectional view showing a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2, the memory device having a misaligned serial selection line structure .

Figure 10 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device as shown in Figure 2, the memory device having a stacked layer carrying a string selection line voltage metal wires.

Figure 11 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device having a page and even and odd bit lines accessed by respective pads.

Figure 12 is a schematic diagram of an integrated circuit including a three-dimensional inverted gate memory array having a paged tandem selection structure.

A detailed description of several embodiments will be provided below with reference to the accompanying drawings.

Figure 1 is a perspective view of a three-dimensional inverse gate memory array structure. For ease of illustration, this figure removes the insulating material to reveal other structures. For example, the insulating layer between the active strips (eg, 112-115) in the stack is removed and the insulating layer between the stacks of active strips is removed.

The multilayer array is formed on an insulating layer and includes a plurality of stacks A plurality of word lines 125-1 WL, ..., 125-N WL of a stack conformal. The majority of the stack includes active strips 112, 113, 114, 115. The material of the active strip includes, for example, a doped semiconductor and a metal. The active strips in the same plane are electrically coupled together by a pad that is configured to have a landing area for contact to an interlayer conductor. The pads of most of the layers can be arranged in a stepped configuration as shown in Fig. 1, wherein the landing zone on each of the continuous pads is placed on the step of the structure. If a particular manufacturing setting is desired or required, the landing zones used to connect the pads and interlayer conductors to the landing zone on the pads can be patterned rather than in a simple stepped configuration.

The displayed word line number (from 1 to N from the back of the overall structure to the front) applies to even memory pages. For odd-numbered memory paging, the word line number is decremented from N to 1 from the back of the overall structure to the front.

Solder pads 112A, 113A, 114A, 115A terminate alternating active strips, such as active strips 112, 113, 114, 115 in each layer. As shown, these pads 112A, 113A, 114A, 115A are electrically coupled to different bit lines for connection of the decoding circuitry to the selected planes within the array. These pads 112A, 113A, 114A, 115A can be patterned while defining a plurality of stacks, but the channel to landing zone can be an exception.

Pads 102B, 103B, 104B, 105B terminate other alternate active strips, such as active strips 102, 103, 104, 105 in each layer. As shown, these pads 102B, 103B, 104B, 105B are electrically coupled to different bit lines for connection of the decoding circuitry to the selected planes within the array. These pads 102B, 103B, 104B, 105B can be patterned while defining a plurality of stacks, but the channel to landing zone can be an exception.

As shown, in this embodiment, any predetermined stack of active strips is coupled to pads 112A, 113A, 114A, 115A or pads 102B, 103B, 104B, 105B, but not both. However, in other figures for embodiments of the present invention, the active strip stacks are coupled to pads at both ends of the active strip stack.

A active strip stack has one of two opposite runs of a bit line end to a source line end or a source line end to a bit line end. For example, the stack of active strips 112, 113, 114, 115 has a bit line end to a source line end trend; and the stack of active strips 102, 103, 104, 105 has a source line end to a bit line end .

One end of the stack of active strips 112, 113, 114, 115 ends with pads 112A, 113A, 114A, 115A, through SSL gate structure 119, ground select line GSL 126, word lines 125-1 WL through 125- N WL, ground select line GSL 127, and the other end ends with source line 128. The stack of active strips 112, 113, 114, 115 does not reach pads 102B, 103B, 104B, 105B.

One end of the stack of active strips 102, 103, 104, 105 ends with pads 102B, 103B, 104B, 105B, through SSL gate structure 109, ground select line GSL 127, word line 125-N WL to 125-1 WL, ground select line GSL 126, and the other end ends with a source line (masked by other parts of the figure). The stack of active strips 102, 103, 104, 105 does not reach pads 112A, 113A, 114A, 115A.

A layer of memory material separates word lines 125-1 WL through 125-N WL from active strips 112-115 and 102-105. The ground select lines GSL 126 and GSL 127 are conformal to a plurality of active strips, similar to word lines.

One end of each active strip stack ends with a pad and the other end ends with a source line. For example, one end of the stack of active strips 112, 113, 114, 115 ends with pads 112A, 113A, 114A, 115A and the other end ends with source line 128. At the proximal end of the figure, every other active strip stack ends with pads 102B, 103B, 104B, 105B; and every other active strip stack ends with a separate source line. At the far end of the figure, every other active strip stack is terminated with pads 112A, 113A, 114A, 115A, and every other active strip stack is terminated with a separate source line.

As previously mentioned, in the remaining figures for embodiments of the present invention, the stack of active strips is coupled to the pads at both ends of the stack of active strips.

The bit line and the string selection line are formed on the metal layers ML1, ML2, and ML3. The electro-crystalline system is formed at the intersection between the active strip (e.g., 112-115) and the word lines 125-1 WL through 125-N WL. In these transistors, a active strip (e.g., 113) acts as a channel region for the device. Active strips (eg, 112-115) can be used as gate dielectric layers for powering crystals.

The tandem selection structure (e.g., 119, 109) is patterned during the same step of defining word lines 125-1 WL through 125-N WL. The electro-crystalline system is formed at the intersection between the active strip (e.g., 112-115) and the tandem selection structure (e.g., 119, 109). These transistors act as a serial selection switch coupled to the decoding circuit for selection A specific stack in this array.

Figure 2 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device. For reference, the "X" axis is in the horizontal direction parallel to the word line in the structure (eg, 125-1 WL to 125-N WL in Figure 1 or 230 in Figure 2), "Y" The axis is located perpendicular to the vertical direction of the active strip (such as 112-115 in Figure 1 or BL1-BL6 in Figure 2), and the "Z" axis is perpendicular to the character line and perpendicular to the structure. The direction of the active bar in and out of this page.

In the layout of Figure 2, this array configuration includes a number of active strips. Memory cells are deployed at the intersection of active strips (eg, BL1-BL6) and word lines (eg, 230). Adjacent active strips alternate between a single tandem selection structure to the opposite direction of the plurality of tandem selection structures and a plurality of tandem selection structures to a single string selection structure. In one of the active strips, every other active strip (eg, BL1, BL3, BL5) is routed through a single tandem selection structure (eg, SSL1, SSL3, SSL5) that is closest to the top pad (eg, 210) and The two serial selection structures (such as SSL0 and SSL2, SSL2 and SSL4, SSL4 and SSL6) closest to the bottom pad (for example, 215).

In the opposite direction of the active strip, every other active strip (eg, BL2, BL4, BL6) walks in two tandem selection structures (eg, SSL1 and SSL3, SSL3, and the closest to the top pad (eg, 210). A single serial selection structure (eg, SSL2, SSL4, SSL6) between SSL5, SSL5, and SSL7) and via the closest pad (eg, 215) at the bottom.

Thus, one of the active strips surrounded by the tandem selection structure strip closest to the top end of the active strip travels between the two tandem selection structures closest to the bottom end of the active strip. For example, the active strip BL1 is routed through SSL1 closest to pad 210 and between SSL0 and SSL2 closest to pad 215.

Similarly, an active strip that runs between the two tandem selection structures closest to the top end of the active strip is surrounded by a string of selected structural strips closest to the bottom end of the active strip. For example, the active strip BL2 travels between SSL1 and SSL3 closest to the pad 210 and via SSL2 closest to the pad 215.

Overlaid on the active strips (eg, BL1-BL6) are horizontal word lines (eg, 230) and tandem select line SSL gate structures. Near the upper pad 210, the serial selection structure (eg, SSL1, SSL3, SSL5) surrounds every other active strip closest to the top end of the active strip (eg, BL1, BL3, BL5) for each active One of the opposite side gates on the sides of the strip. SSL1 acts as one of the opposite gates of BL1. SSL3 acts as one of the side gates of BL3. SSL5 acts as one of the side gates of BL5. Near the bottom pad 215, the serial selection structure (eg, SSL2, SSL4, SSL6) encloses every other active strip closest to the bottom end of the active strip (eg, BL2, BL4, BL6) for each active Side gates on the sides of the strip. SSL2 acts as one of the opposite gates of BL2. SSL4 acts as one of the side gates of BL4. SSL6 acts as one of the opposite gates of BL6.

At the closest to the upper pad 210, a serial selection structure (eg, SSL1, SSL3, SSL5) surrounding every other active strip at the top end of the active strip (eg, BL1, BL3, BL5) is also used as each Adjacent to one side of the active strip One of the side gates on the surface. SSL1 acts as a side gate of BL2. SSL3 acts as a side gate of BL2 and a side gate of BL4. SSL5 acts as a side gate of BL4 and a side gate of BL6. Also, SSL7 acts as a side gate of BL6.

At the closest to the bottom pad 215, the serial selection structure (eg, SSL2, SSL4, SSL6) surrounding every other active strip at the bottom end of the active strip (eg, BL2, BL4, BL6) is also used as each One of the side gates on one side surface of the active strip. SSL2 acts as a side gate of BL1 and a side gate of BL3. SSL4 acts as a side gate of BL3 and a side gate of BL5. SSL6 acts as a side gate for BL5. Also, SSL0 is used as one side gate of the active strip BL1.

The horizontal word line (e.g., 230) is sandwiched with an insulating material (not shown). There may be 64 word lines deployed between the top and bottom tandem select line structures (eg, between SSL1, SSL3, SSL5, SSL7 at the top and SSL0, SSL2, SSL4, SSL6 on the bottom). The word line can be manufactured using SADP (Self-Aligned Double Pattern Method).

The three-dimensional inverse gate memory device includes a plurality of planar memory cells. A plurality of bit lines from an upper metal layer are selected from a particular plane of the plurality of planar memory cells via pads (e.g., 210, 215 in FIG. 2). A particular memory cell within a particular plane is decoded by a plurality of serial select line structures and word lines.

Figure 3 is a layout diagram of a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2, the memory device having a read bias configuration.

The memory cell selected for reading is in the active strip stack BL3. To choose BL3. The top and bottom portions of the BL3 are conductive. The serial selection line SSL structure SSL3 surrounding BL3 and passing through the top pad 210 as one of the side gates to BL3 has a selection voltage of 3V, thereby turning on the top portion of BL3. The series select line SSL structures SSL2 and SSL4 adjacent to BL3 and having the bottom pad 215 as one of the opposite gates to BL3 have a selection voltage of 3V, thereby turning on the bottom portion of BL3.

Adjacent to the selected active strip BL3 are deselected active strips BL2 and BL4. Both BL2 and BL4 are surrounded by SSL2 and SSL4, respectively, by bottom pad 215, each for use as a side gate having one of the selected voltages of 3V, thereby turning on the bottom portions of BL2 and BL4. However, both BL2 and BL4 have respective side gates SSL1 and SSL5 by top pad 210 (having a strong negative voltage of -8V). The strong negative voltage on one of the side gates overcomes the selection voltage 3V from the other side gate SSL3, thereby rendering the top portions of BL2 and BL4 non-conductive. Since both the top and bottom portions of a active strip are turned on by a selected active strip, and the top portion is BL2 and BL4 remain non-conductive, BL2 and BL4 remain deselected. The gates SSL0, SSL2, SSL4, and SSL6 have 3V.

The top pad 210 has a bit line voltage 3V for the selected layer of the memory array and 0V for the plurality of deselected layers of the memory array, and the bottom pad 215 has one for all layers. The source line voltage is 0V. The plurality of word lines 230 that are deselected have a pass voltage, and one of the selected word lines 230 has a read voltage. According to the selection layer of the top pad 210, the first reading Current is drawn from the top pad 210 to the bottom pad 215 via the selected active strip BL3. The value or presence of the current depends on the threshold voltage of the memory cell selected by the selected word line.

Figure 4 is a layout diagram of a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2, and the memory device has another read bias configuration.

The memory cell selected for reading is in the active strip stack BL4. In order to select BL4, the top and bottom portions of BL4 are conductive. The serial selection line SSL structure SSL4 surrounding BL4 and passing through the bottom pad 215 as one of the opposite gates to BL4 has a selection voltage of 3V, thereby turning on the bottom portion of BL4. The series select line SSL structures SSL3 and SSL5 adjacent to BL4 and having the top pad 210 as one of the opposite gates to BL4 have a select voltage of 3V, thereby turning on the top portion of BL4.

Adjacent to the selected active strip BL4 are deselected active strips BL3 and BL5. Both BL3 and BL5 are surrounded by SSL3 and SSL5 by top pad 210, and SSL3 and SSL5 are each used as a side gate having a selection voltage of 3V, thereby turning on the top portions of BL3 and BL5. . However, both BL3 and BL5 have respective side gates SSL2 and SSL4 by bottom pad 215 (having a strong negative voltage of -8V). The strong negative voltage on one of the side gates overcomes the selection voltage of 3V from the other side gate SSL4, so that the bottom portions of BL3 and BL5 are not turned on. Because both the top and bottom portions of a active strip are turned on by a selected active strip, and the bottom portion is BL3 and BL5 remain non-conductive, Therefore, BL3 and BL5 remain unselected. The gates SSL1, SSL3, SSL5, and SSL7 have 3V.

The bottom pad 215 has a bit line voltage 3V for the selected layer of the memory array and 0V for the plurality of deselected layers of the memory array, and the top pad 210 has one for all layers. The source line voltage is 0V. The plurality of word lines 230 that are deselected have a pass voltage, and one of the selected word lines 230 has a read voltage. A read current flows from the bottom pad 215 to the top pad 210 via the selected active strip BL4 in accordance with the selected layer of the bottom pad 215. The value or presence of the current depends on the threshold voltage of the memory cell selected by the selected word line.

3 and 4 show whether the top pad 210 and the bottom pad 215 respectively provide a bit line voltage and a source line voltage, or respectively provide a source line voltage and a bit line voltage, depending on being selected and included to be selected A specific active strip for the read memory cell. Similarly, depending on the particular active strip selected and including the memory cells selected for reading, the tandem selection structures SSL1, SSL3, SSL5, and SSL7 closest to the top pad 210; and the string closest to the bottom pad 215 Whether the column selection structures SSL0, SSL2, SSL4, and SSL6 provide the string selection line voltage and the ground selection line voltage, respectively, or the ground selection line voltage and the string selection line voltage, respectively. Other voltages can be used to select, deselect, suppress, and read voltages.

Figure 5 is a layout diagram of a first array arrangement of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2, the memory device having a program bias configuration.

The memory cell selected for the program is located in the active strip stack BL3. In order to select BL3, the BL3 structure is surrounded by the top pad 210 as a tandem selection line SSL structure to one of the BL3 gates, and has a selection voltage of 3V, thereby turning on BL3. Adjacent to the selected active strip BL3 are deselected active strips BL2 and BL4, each having a side surface receiving a selection voltage 3V from BL3 for use as a side gate. Both BL2 and BL4 have respective side gates SSL1 and SSL5 by top pad 210 (having a strong negative voltage of -8V). The strong negative voltage on one of the side gates overcomes the selection voltage of 3V from the other side gate SSL3, thereby rendering BL2 and BL4 non-conducting.

The top pad 210 has a bit line voltage of 0V for the selected layer of the memory array and 3V for the plurality of deselected layers of the memory array, and the bottom pad 215 has one for all layers. The source line voltage is 3V. The plurality of word lines 230 that are deselected have a pass voltage, and one of the selected word lines 230 has a program voltage. According to the selected layer of the top pad 210, a stylized current flows from the top pad 210 through the selected active strip BL3 toward the bottom pad 215, and is then injected into the memory selected by the selected word line. In the cell. Other voltages can be used to select, deselect, suppress, and program voltages.

Figure 6 is a layout diagram of a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2, the memory device having a stack for the serial selection line SSL structure A mask that accumulates outlines.

The first mask having outlines 602 and 604 displays exemplary respective patterns for defining a tandem select line structure SSL1, SSL3, by top pad 210, Blocks of SSL5 and SSL7; and blocks of the serial select line structures SSL0, SSL2, SSL4, and SSL6 are defined by the bottom pad 215.

The second mask having outlines 610, 612, 614, 616 displays a number of exemplary patterns for etching the blocks separating the serial select line structures SSL1, SSL3, SSL5, and SSL7 by the top pad 210. The second mask also has outlines 618, 620, 622, 624 showing an exemplary pattern for etching the blocks separating the serial select line structures SSL0, SSL2, SSL4, and SSL6 by the bottom pad 215.

Figure 7 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device as shown in Figure 2, the memory device having a stack of pads and active strips stacked A mask that accumulates outlines.

The mask having the outline 702 displays an exemplary pattern for defining the entire area having the top pad 210, the bottom pad 215, and the active strip stack BL1-BL6. The same mask includes an exemplary pattern having contours 704, 706, 708, 710, and 712 for defining a gap between the active strip stacks. These gaps define one of the gap widths in the X direction to separate adjacent ones of the active strip stack. The active strip stack has a stack width in the X direction.

The section line A'-A" indicates the position of the cross-sectional view of the subsequent figure.

Figure 8 is a cross-sectional view showing a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices as shown in Figure 2.

The cross-sectional view in Fig. 8 is taken along the section line A'-A" in Fig. 7. For the purpose of explanation, the oxide is removed.

BL4 is a active strip stack with active strips 815, 813 and 811 Stack. The active strips are separated by insulating strips 816, 814, 812 and 810. The active strip stack includes a cover memory material layer, which may be a charge gap engineering SONOS (BE-SONOS) charge storage structure including a dielectric tunneling layer, the dielectric tunneling layer including a zero bias voltage A composite material with one of the reversed "U" shaped valence bands. In one embodiment, the composite tunnel dielectric layer includes a first layer called a tunneling layer, a second layer called a band compensation layer, and a third layer called an isolation layer. The hole tunneling layer of this layer in this embodiment includes cerium oxide on the side surface of the strip of semiconductor material, which is formed, for example, by using ISSG to generate on-site steam, and selectively utilizes a NO annealing after deposition. Nitriding may be carried out by adding NO to the ambient during deposition. The thickness of the first layer of cerium oxide is less than 20 Å, preferably 15 Å or less. Several representative embodiments can be 10 Å or 12 Å thick.

The energy band compensation layer in this embodiment includes tantalum nitride on the tunneling layer of the hole, for example, by using low pressure chemical vapor deposition LPCVD, at 680 ° C, for example, using dichlorosilane DCS and NH ₃ precursors. form. In other alternative processes, the band offset layer comprises silicon oxynitride, which is a system using a similar process and N ₂ O precursor is made. The thickness of the band of the tantalum nitride band is less than 30 Å, and preferably 25 Å or less.

The spacer layer in this embodiment includes ruthenium dioxide on the band gap compensation layer of the tantalum nitride, and the band compensation layer is formed, for example, by deposition using LPCVD high temperature oxide HTO. The thickness of the separator of cerium oxide is less than 35 Å, and preferably 25 Å or less. These three tunneling layers result in an inverted U-shaped valence band energy level.

The valence band in the first position enables an electric field to be sufficient to cause a hole Tunneling through a thin region between the semiconductor body interface and the first location, and also sufficient to increase the valence band energy level after the first location to a level, which effectively eliminates composite wear after the first location A hole in the tunnel dielectric material tunnels through the barrier. This structure establishes an inverted U-shaped valence band energy level in a three-layer tunneling dielectric layer, and can achieve electric field-assisted high-speed hole tunneling, in the absence of an electric field or for other operational purposes (eg, reading In the case where the presence of a small electric field induced by the unit cell or the stylized adjacent unit cell is taken, the charge leakage is effectively prevented from passing through the composite tunneling dielectric material.

The adjacent active strip stacks BL3 and BL5 have a similar configuration to BL4.

The tandem selection line structure SSL4 surrounds the active strip stack BL4 for use as one of the side gates for the side surfaces of the active strips 815, 813, and 811. The tandem select line structure SSL4 also serves as a side gate on one side surface of the active strip in BL3. The tandem select line structure SSL4 also serves as a side gate on one side surface of the active strip in BL3.

Active strip stacks such as BL3, BL4, and BL4 have respective stack widths 830, 834, and 838. These active strip stacks are separated by a gap width, such as a gap width 832 between BL3 and BL4 and a gap width 836 between BL4 and BL5. In order to make the tandem select line structure SSL4 wide enough to not only surround the active strip stack BL4 but also serve as one of the side gates for the active strip stack BL4, and also as a side gate for the adjacent active strip stacks BL3 and BL5. The tandem select line structure SSL4 has a width exceeding the sum of: (i) stacking width and (ii) twice Gap width. However, to avoid touching adjacent serial select line structures SSL2 and SSL4, the tandem select line structures SSL2, SSL4, and SSL6 have a width less than the sum of: (i) twice the stack width and (ii) twice The gap width.

Figure 9 is a cross-sectional view showing a first array configuration of one of the finger-shaped vertical gate three-dimensional and gate memory devices shown in Figure 2 with a misaligned tandem selection line structure.

Unlike the cross-sectional view of FIG. 8, the tandem select line SSL structure SSL4 is decoupled from the center of the active strip stack BL4. Regardless of the poor alignment up to about the gap width 832/836, the SSL 4 still surrounds the active strip stack BL4 and acts as one of the side gates for the sides of the active strip stack BL4.

However, this misalignment is sub-optimal because the tandem select line SSL structure SSL4 acts as a side gate for BL5 rather than one surface of BL3. Therefore, misalignment causes one end of the active strip stack to have only side gates instead of two side gates.

Figure 10 is a layout diagram of a first array configuration of a finger-shaped vertical gate three-dimensional inverse gate memory device as shown in Figure 2, the memory device having a stacked layer carrying a string selection line voltage metal wires.

The metal lines of this layer carry the string select line voltage from the elsewhere of the integrated circuit to the tandem select line SSL structure. In pre-design, such as the design shown in Figure 1, two metal layers are required - one metal layer for the string select line voltage and the other for the ground select line voltage. However, in the illustrated embodiment, the tandem select line SSL structure closest to the top pad and the tandem select line SSL closest to the bottom pad The structure combines the functions of an older serial select line voltage and an older ground select line voltage. Thus, in the illustrated embodiment, a single metal layer is sufficient for performing the tandem selection function.

Figure 11 is a layout diagram of a first array arrangement of a finger-shaped vertical gate three-dimensional inverse gate memory device having a page and even and odd bit lines accessed by respective pads.

The different layers of the upper pad 210 are electrically coupled to every other active strip (eg, BL1, BL3, BL5), which are odd pages. BL1, BL3, and BL5 are electrically coupled to layer 1, layer 2, and layer 3 of upper pad 210, respectively. The BL1, BL3, and BL5 systems are electrically decoupled from the layers of the lower pads 215.

The different layers of the lower pad 215 are electrically coupled to every other active strip (eg, BL2, BL4, BL6), which are even pages. BL2, BL4, and BL6 are electrically coupled to layer 1, layer 2, and layer 3 of the lower pad 215, respectively. The BL2, BL4, and BL6 are electrically decoupled from the layers of the upper pad 210.

Some embodiments have even layers, even odd pages, and even even pages (not shown).

12 is a schematic diagram of a semiconductor device of a three-dimensional inverse gate memory array according to an embodiment of the present invention, the memory array including a page tandem selection structure. The semiconductor device 1075 includes a three-dimensional anti-gate flash memory array 1060, as described herein, implemented on a semiconductor substrate having the closest deployed pads and located on the opposite side of the memory cell. A plurality of page tandem selection structures on the opposite side of the plurality of active strips of the series. A column of decoders 1061 is coupled to the plurality of word line lines 1062 and along the memory array 1060. Sequence configuration. A row of decoders 1063 is coupled to a plurality of SSL lines 1064, including a plurality of serial selection structures, configured along rows corresponding to active strips in the memory array 1060 for reading and programming from the array 1060. The memory of the data. A planar decoder 1058 is coupled to a plurality of planes in the memory array 1060 via bit lines 1059. The address on bus 8065 is provided to row decoder 1063, column decoder 1061, and plane decoder 1058. The sense amplifier and data input structure in block 1066 is coupled to row decoder 1063 via data bus 1067 in this example. The data is supplied to the data input structure in block 1066 via data input line 1071, from input/output ports on integrated circuit 1075, or from other sources internal or external to integrated circuit 1075. In the embodiment shown, another circuit 1074, such as a general purpose processor or special purpose application circuit, is included on the integrated circuit or provides a system single chip supported by the anti-gate flash memory cell array. A combination of functional modules. The data is provided from the sense amplifiers in block 1066 to the input/output ports on integrated circuit 1075 via data output line 1072, or to other data objects internal or external to integrated circuit 1075.

In this example, a controller is implemented by using a bias configuration state machine 1069 to control the application of a bias voltage configuration voltage voltage generated or provided via a voltage source, or to provide, for example, read and erase in block 1068. , program, erase confirmation and program confirmation voltage.

In order to select a particular active strip among a plurality of active strips, the controller can apply an appropriate voltage to the tandem selection structure surrounding one of the active strip stacks closest to one of the active strip stacks and apply it to be used as the closest One of the side gates of the other end of the active strip stack has a serial selection structure.

The controller can use special purpose logic power known from the prior art. Implemented by the road. In an alternate embodiment, the controller includes a general purpose processor that can be implemented on the same integrated circuit and that executes a computer program to control the operation of the device. In still other embodiments, the controller can be implemented using a combination of special purpose logic circuitry and a general purpose processor.

While the invention has been described with reference to the embodiments of the invention, It will be apparent to those skilled in the art that various modifications and combinations may be made without departing from the spirit and scope of the invention.

BL1~BL6‧‧‧active strip/active strip stacking

SSL0~SSL7‧‧‧serial selection structure

210, 215‧‧ ‧ pads

230‧‧‧ character line

x, y‧‧‧ coordinate axis

Claims (21)

An integrated circuit having a memory array, comprising: a plurality of active strip stacks having a plurality of memory cells of the memory array, the active strip stacks having a plurality of first ends and a plurality of second ends; a solder pad in contact with the first ends of one or more of the active strip stacks; a second solder pad in contact with the second ends of one or more of the active strip stacks; a plurality of active The strip stacking structure is electrically coupled to the active strip stacks at a position between the first ends and the second ends; and a control circuit coupled to the first pads and the second a pad in response to receiving a first command to read a first group of memory cells on the memory array, the control circuit applying a first set of read voltages to the first pad and the second pad So that the first pad has a higher voltage than the second pad, and in response to receiving a second command to read a second group of memory cells on the memory array, the control circuit applies a a second set of read voltages to the first pad and the second pad to enable the Two pad having a pad higher than the first voltage. The integrated circuit of claim 1, wherein the first set of read voltages comprises a one-bit line voltage and a source line voltage, and the bit line voltage is applied to the first pad, the source a line voltage is applied to the second pad, and the second set of read voltages includes the bit line voltage and the source line voltage, the bit A source line voltage is applied to the second pad, the source line voltage being applied to the first pad. The integrated circuit as described in claim 1, wherein the active strip stack selection structure comprises: a first set of active strip stack selection structures, located on a first side of one of the plurality of word lines; and a first Two sets of active strip stack selection structures are located on a second side of the one of the word lines, and the control circuit uses the first set of active strip stack selection structures and the second set of active strip stack selection structures to select the A specific number of active strip stacks are used for operation. The integrated circuit of claim 3, wherein the first set of read voltages comprises a series select line voltage and a ground select line voltage, the series select line voltage being applied to the first set of active strips At least one of a stack selection structure, the ground select line voltage is applied to at least one of the second set of active strip stack selection structures, and the second set of read voltages includes the tandem select line voltage and the ground selection A line voltage, the series select line voltage is applied to at least one of the second set of active strip stack selection structures, the ground select line voltage being applied to at least one of the first set of active strip stack selection structures. The integrated circuit of claim 3, further comprising: a plurality of first metal lines, wherein one of (i) the plurality of serial selection line signals and (ii) the plurality of ground selection line signals are transmitted to The first set of active strip stack selection knots And a plurality of second metal lines transmitting (i) the plurality of serial select line signals and (ii) the plurality of ground select line signals to the second set of active strip stack selection structures, wherein the The first metal line and the second metal lines are on the same metal layer. The integrated circuit of claim 1, wherein the active strip stack comprises a first set of active strip stacks and a second set of active strip stacks interleaved with each other, the first set of active strips stacked electrically And being electrically decoupled from the first pad, the second set of active strips being electrically coupled to the second pad and electrically decoupled from the first pad . An integrated circuit having a memory array, comprising: a plurality of active strip stacks having a plurality of memory cells of the memory array, the active strip stacks having a plurality of first ends and a plurality of second ends; a plurality of active The strip stack selection structure is electrically coupled to the active strip stacks at the positions between the first ends and the second ends, and the active strip stack selection structures select specific ones of the active strip stacks For operation, the active strip stack selection structures are double gate structures, and the active strip stack selection structures include: a first set of active strip stack selection structures, located on a first side of one of the plurality of word lines; And a second set of active strip stack selection structures, located on a second side of the one of the character lines, wherein each active strip stack of the active strip stacks has: a first active strip stack selection structure from the first set of active strip stack selection structures for use as first and second side gates on each active strip stack of the first side of the word lines; And a second active strip stack selection structure and a third active strip stack selection structure, the second active strip stack selection structure is used as each active strip stack of the second side of the word lines The third and fourth side gates. The integrated circuit of claim 7, wherein the adjacent active strip stacks of the active strip stacks have opposite directions such that the adjacent active strips are stacked on the first one, The direction from the first end to the second ends of the active strip stack has a single stack selection structure to a plurality of stack selection structure orientations, and the adjacent active strips are stacked on the second one. The direction from the first end to the second ends of the active strip stack has a plurality of stack selection structures to a single stack selection structure, and the adjacent ones of the active strip stacks have the single Stacking the selection structure to the plurality of stack selection structures such that the active strip stack selection structures apply a plurality of independent control voltages to the adjacent active strip stacks on the second side of the word lines One of the adjacent active strip stacks, wherein the second one has the plurality of stack selection structures to a single stack selection structure, such that the active strip stack selection structures are independent A control voltage is applied to the second of the adjacent active strips stacked on the first side of the word lines. The integrated circuit of claim 7, wherein the adjacent active strip stacks of the active strip stacks have opposite directions such that the adjacent active strips are stacked on the first one, The direction from the first end to the second ends of the active strip stack has a single stack selection structure to a plurality of stack selection structure orientations, and the adjacent active strips are stacked on the second one. The direction from the first end to the second ends of the active strip stack has a plurality of stack selection structures to a single stack selection structure, and the adjacent ones of the active strip stacks have the single Stacking the selection structure to the plurality of stack selection structures such that the active strip stack selection structures apply only one independent control voltage to the adjacent active strip stacks on the first side of the word lines One of the adjacent active strip stacks, wherein the second one has the plurality of stack selection structures to a single stack selection structure, so that the active strip stack selection structures only have one An independent control voltage is applied to the second of the adjacent active strips stacked on the second side of the word lines. The integrated circuit of claim 7, wherein the adjacent active strip stacks of the active strip stacks have opposite directions such that the adjacent active strips are stacked on the first one, The direction from the first end to the second ends of the active strip stack has a single stack selection structure to a plurality of stack selection structure orientations, and the adjacent active strips are stacked on the second one. The direction from the first end to the second ends of the active strip stacks has a plurality of stack selection structures to a single stack selection structure. Each of the adjacent active strip stacks has the single stack selection structure to the plurality of stack selection structures, such that only one first stack selection structure is electrically coupled to the active strip stack selection structure. The first one of the adjacent active strips on the first side of the plurality of word lines is stacked, and the first plurality of stacked select structures in the active strip stack selection structure are electrically coupled Up to the first one of the adjacent active strips on the second side of the word lines, and the second one of the adjacent active strip stacks has the plurality of stacked selection structures to a single The stacking structure is configured such that the second plurality of stack selection structures of the active strip stack selection structure are electrically coupled to the adjacent active strips of the first side of the word lines The second one of the active strip stacking structures is electrically coupled to the adjacent active strip stacks on the second side of the word line lines. the second. The integrated circuit of claim 7, wherein the adjacent active strip stacks of the active strip stacks have opposite directions such that the adjacent active strips are stacked on the first one, The direction from the first end to the second ends of the active strip stack has a single stack selection structure to a plurality of stack selection structure orientations, and the adjacent active strips are stacked on the second one. The direction from the first end to the second ends of the active strip stack has a plurality of stack selection structures to a single stack selection structure, and the active strip stacks are along the length direction of the active strip stacks. And a plurality of first surfaces and a plurality of second surfaces, the first surfaces are opposite to the second surfaces, and the adjacent active strip stacks are applied to the second side of the word lines The plurality of independent control voltages of the first one of the first ones include: a first independent control voltage coupled to the first surface of the first one of the adjacent active strip stacks, instead of the The second surface, and a second independent control voltage, are coupled to the second surface of the adjacent one of the adjacent active strip stacks instead of the first surface. The integrated circuit of claim 7, wherein the adjacent active strip stacks of the active strip stacks have opposite directions such that the adjacent active strips are stacked on the first one, The direction from the first end to the second ends of the active strip stack has a single stack selection structure to a plurality of stack selection structure orientations, and the adjacent active strips are stacked on the second one. The direction from the first end to the second ends of the active strip stack has a plurality of stack selection structures to a single stack selection structure, and the active strip stacks are along the length direction of the active strip stacks. The plurality of first surfaces and the plurality of second surfaces, the first surfaces are opposite to the second surfaces, and the adjacent active strips applied to the second side of the word lines are stacked therein The first plurality of independent control voltages of the first one comprise: a first independent control voltage coupled to the first surface of the first one of the adjacent active strip stacks instead of the second Surface, and a second An independent control voltage coupled to the second surface of the first active strip stack, not the first surface, and applied to the adjacent sides of the first side of the word lines The active strips stack the plurality of independent control voltages of the second one, including: a third independent control voltage coupled to the second surface of the adjacent active strip stack, instead of the second surface, and a fourth independent control voltage coupled to the neighbors The active strip stacks the second surface of the second one instead of the first surface. The integrated circuit of claim 7, wherein the active strip stack selection structure is designed to be used as a plurality of side gates for a plurality of channels in the active strip stack to form a plurality Serial selector switch. An integrated circuit having a memory array, comprising: a plurality of active strip stacks having a plurality of memory cells of the memory array, the active strip stacks having a plurality of first ends and a plurality of second ends; The strip stack selection structure is electrically coupled to the active strip stacks at the positions between the first ends and the second ends, and the active strip stack selection structures select specific ones of the active strip stacks For operation, wherein the active strip stack selection structures are disposed to surround alternating ends of the active strip stacks to utilize adjacent active strip stacks in the active strip stacks to (i) the adjacent ones The first of the active strip stacks has a first active strip stack selection structure, the first active strip stack selection structure being disposed to surround the adjacent active strips stacked on the first side of one of the plurality of word lines The first one, and (ii) the second of the adjacent active strip stacks has a second active strip stack selection structure, the second active strip stack selection structure is disposed to surround the word lines The adjacent active strips on one of the second sides stack the second one of them. An integrated circuit as described in claim 14 of the patent application, wherein The first active end of the adjacent active strip stack receives a first independent control voltage via the first active strip stack selection structure, the first independent control voltage is derived from the active strip stack selection Structure, the first active strip stack selection structure provides the first independent control voltage of the second side of the plurality of word lines to be adjacent to any one of the adjacent ones of the adjacent active strip stacks The active strips are stacked, and the second one of the adjacent active strip stacks receives a second independent control voltage via the second active strip stack selection structure, the second independent control voltage And the second active strip stack selection structure, the second independent control voltage of the first side of the word lines is provided to the adjacent active strips. The active strips adjacent to either side of the second stack are stacked. The integrated circuit of claim 14, wherein the active strip stack selection structures are designed to be used as a plurality of side gates for a plurality of channels in the active strip stack to form a plurality of Tandem selection switch. An integrated circuit having a memory array, comprising: a plurality of active strip stacks having a plurality of memory cells of the memory array, the active strip stacks having a stack width and a plurality of first ends and second ends, The first end and the second end are located adjacent to the stack of the active strips separated by a gap width; a plurality of active strip stack selection structures, and the active strip stack selection structures are connected to the first ends And a position between the second ends electrically coupled to the active strips Stacking, the active strip stack selection structure selects a specific one of the active strip stacks for operation, the active strip stack selection structures having a width greater than (i) the stack width and (ii) twice the gap width The sum is less than (i) twice the width of the stack and (ii) twice the width of the sum of the gap widths. The integrated circuit of claim 17, wherein the active strip stack selection structures are designed to be used as a plurality of side gates for a plurality of channels in the active strip stack to form a plurality of Tandem selection switch. A method of operating an integrated circuit having a memory array, comprising: applying a first control voltage to a first active strip stack selection structure, the first control voltage being applied to: (i) a first active strip stack a first side gate and a second side gate, the first side gates are opposite to the second side gate, and the first active strips are stacked on a second active strip stack and a third active strip stack (ii) one of the first active strips of the second active strip stack, rather than a second side gate, and (iii) one of the first side gate stacks of the third active strip stack, rather than a first Two side gates. The method of claim 19, wherein the first active strip stack has a plurality of first ends and second ends on opposite sides of a length direction of the first active strip stack, and the first control voltage And applying the first active strip stack selection structure to the first active strip stack on a first side of the plurality of character lines, and the method further comprises: applying a second control voltage to a second active The strip stack selection structure is on a second side of one of the word lines as a first side gate instead of a second side gate. For example, the method described in claim 20 of the patent scope further includes: A third control voltage is applied to a third active strip stack selection structure, the second side of the word lines being a second side gate instead of a first side gate.