CN220474340U

CN220474340U - Memory array and memory

Info

Publication number: CN220474340U
Application number: CN202321816357.8U
Authority: CN
Inventors: 冯骏; 李琪; 熊涛
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2023-07-11
Filing date: 2023-07-11
Publication date: 2024-02-09
Anticipated expiration: 2033-07-11

Abstract

The application provides a memory array and a memory, comprising: a plurality of bit lines arranged at intervals; the active areas are provided with storage unit pairs comprising two storage units, each storage unit pair comprises a first area, a second area and a channel area positioned between the first area and the second area, and one storage unit pair is connected with two bit lines; one bit line overlaps one active region, or one bit line overlaps two adjacent active regions and an isolation region between the two adjacent active regions.

Description

Memory array and memory

Technical Field

The present disclosure relates to the field of memory technologies, and in particular, to a memory array and a memory.

Background

Nonvolatile Memory (NVM) has the characteristics of storing, reading and erasing data many times, and the stored data will not disappear after power failure, so it is widely used in personal computers and electronic devices. However, the difficulty of the manufacturing process of some nonvolatile memories is great at present.

Therefore, it is necessary to provide a technical solution to improve the problem of the difficulty of the manufacturing process of the memory.

Disclosure of Invention

The present utility model provides a memory array and a memory, which can solve the problem of difficult manufacturing process of the memory.

In a first aspect, the present application provides a memory array comprising:

a plurality of bit lines arranged at intervals; and

the device comprises a plurality of active areas which are arranged at intervals, wherein an isolation area is arranged between two adjacent active areas, the active areas are provided with memory cell pairs which comprise two memory cells, each memory cell pair comprises a first area, a second area and a channel area which is positioned between the first area and the second area, and one memory cell pair is connected with two bit lines;

one bit line overlaps one active region, or one bit line overlaps two adjacent active regions and the isolation region between the two adjacent active regions.

In some embodiments, one of the bit lines overlaps two adjacent active regions and the isolation region between the two adjacent active regions, and at least part of the bit line extends in a zigzag shape.

In some embodiments, one of the bit lines includes a first line segment and a second line segment connected to each other, an extension direction of the first line segment intersecting an extension direction of the second line segment, and the first line segment and the second line segment each intersect two adjacent active regions and the isolation region between the two adjacent active regions.

In some embodiments, the memory array further comprises: and a plurality of contacts positioned at the positions where the active areas and the bit lines intersect, wherein one part of the contacts are respectively contacted with the first areas and the bit lines at opposite ends, and the other part of the contacts are respectively contacted with the second areas and the bit lines at opposite ends.

In some embodiments, the memory array further comprises: and the redundant active areas are positioned on at least one side of the plurality of active areas, and one bit line overlaps one redundant active area, one active area adjacent to the redundant active area and an isolation area between the redundant active areas and the active areas.

In some embodiments, one of the bit lines overlaps one of the active regions;

the memory array further includes: a plurality of connection lines, one end of each connection line is connected with one of the two adjacent bit lines, and the other end of each connection line is disconnected with the other of the two adjacent bit lines; and

and a plurality of contacts, wherein one part of the contacts are respectively contacted with one end of the connecting wire and the first area, and the other part of the contacts are respectively contacted with the other end of the connecting wire and the second area.

In some embodiments, the bit lines extend in a straight line.

In some embodiments, the active region extends in a straight line.

In some embodiments, the memory cell pair further includes a first gate, a second gate, and a third gate located on one side of the channel region and overlapping the channel region, the first gate being shared by two of the memory cells of the memory cell pair;

the memory array further includes:

a plurality of first control signal lines intersecting the plurality of bit lines and connected to the first gates of the pair of memory cells;

a plurality of second control signal lines connected to the second gates of the first control gates of the pair of memory cells; and

and a plurality of third control signal lines connected to the third gates of the second control gates of the pair of memory cells.

In some embodiments, the memory array comprises:

a semiconductor layer including a plurality of the active regions; and

a first conductive layer including a plurality of the first control signal lines, the first conductive layer being located at one side of the semiconductor layer in a thickness direction of the semiconductor layer; and

and a second conductive layer including a plurality of bit lines, and being located at a side of the first conductive layer away from the semiconductor layer in a thickness direction of the semiconductor layer, or being located between the first conductive layer and the semiconductor layer in the thickness direction of the semiconductor layer.

In some embodiments, the first control signal line intersects the active region, and an included angle between the first control signal line and the active region is greater than 0 degrees and less than 90 degrees.

In a second aspect, the present application further provides a memory comprising the memory array of any of the embodiments described above.

According to some embodiments of the present application, since one bit line overlaps one active region, or one bit line overlaps two adjacent active regions and an isolation region between two adjacent active regions, conductive lines connecting the bit line and the memory cell pairs in the related art may be reduced or even eliminated, thereby simplifying the manufacturing process of the memory array and the memory. In addition, one bit line is overlapped with one active region, or one bit line is overlapped with two adjacent active regions and an isolation region between the two adjacent active regions, so that more layout space can be provided for the active regions, and further the density of the memory array and the memory cell pairs of the memory is increased.

Drawings

FIG. 1 is a schematic diagram of a memory array according to some embodiments of the present application;

FIG. 2 is a schematic cross-sectional view taken along the line Z1-Z1 shown in FIG. 1;

FIG. 3 is a schematic circuit diagram of the memory array of FIG. 1;

FIG. 4 is a schematic diagram of a memory array according to other embodiments of the present application;

FIG. 5 is a schematic cross-sectional view taken along the line Z2-Z2 in FIG. 4;

FIG. 6 is a circuit schematic of the memory array of FIG. 4;

fig. 7 is a schematic diagram of a memory according to some embodiments of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a memory array according to some embodiments of the present application, fig. 2 is a schematic sectional structural diagram taken along a line Z1-Z1 shown in fig. 1, and fig. 3 is a schematic circuit diagram of the memory array shown in fig. 1.

Referring to fig. 1 and 3, the memory array 100 includes a plurality of active areas AA, a plurality of bit lines BL, a plurality of first control signal lines WL, a plurality of second control signal lines CgA, a plurality of third control signal lines CgB, and a plurality of contacts CT.

Referring to fig. 2, the memory array 100 includes a semiconductor layer 10, a first conductive layer 11 and a second conductive layer 12. In the thickness direction z of the semiconductor layer 10, the first conductive layer 11 and the second conductive layer 12 are located on the same side of the semiconductor layer 10, and the second conductive layer 12 is located on a side of the first conductive layer 11 away from the semiconductor layer 10.

In other embodiments, the second conductive layer 12 may also be located on one side of the first conductive layer 11 and the semiconductor layer 10 in the thickness direction z of the semiconductor layer 10.

The semiconductor layer 10 includes a plurality of active regions AA spaced apart from each other, and the semiconductor layer 10 further includes an isolation region GA between two adjacent active regions AA. The first conductive layer 11 includes a plurality of first control signal lines WL, and the first conductive layer 11 may further include a plurality of second control signal lines CgA and a plurality of third control signal lines CgB. The second conductive layer 12 includes a plurality of bit lines BL.

In some embodiments, semiconductor layer 10 includes, but is not limited to, a silicon substrate. The first conductive layer 11 and the second conductive layer 12 include a conductive material including a metal, polysilicon, and the like. Metals include, but are not limited to, tungsten, copper, aluminum, and combinations thereof.

The plurality of active areas AA extend along a third direction w and are arranged at intervals along a first direction x, and the first direction x intersects the third direction w. Each active area AA is provided with a plurality of memory cell pairs U connected in series, and each memory cell pair U includes a first memory cell U1 and a second memory cell U2. The plurality of memory cell U pairs disposed in the plurality of active areas AA are arranged in an array along the first direction x and the third direction w.

In some embodiments, as shown in fig. 1, the included angle between the first direction x and the third direction w is an acute angle, but is not limited thereto. In some embodiments, the angle between the first direction x and the third direction w may be an obtuse angle.

In other embodiments, the first direction x and the third direction w may be perpendicular, which is beneficial to increasing the number of active areas AA, and thus increasing the density of the memory cell pairs U.

In other embodiments, the plurality of active areas AA may also extend in the first direction x and be arranged in the second direction y.

In some embodiments, the plurality of active areas AA extend in a straight line to simplify the process of forming the plurality of active areas AA and reduce the difficulty of fabricating the memory array.

In other embodiments, at least part of the plurality of active areas AA may also extend in a zigzag shape, so as to facilitate the intersection of the plurality of active areas AA and the plurality of bit lines BL, reduce the number of wirings connecting the memory cell pairs U and the bit lines BL, and reduce the difficulty in manufacturing the memory array.

In some embodiments, the plurality of active areas AA are arranged at equal intervals in the first direction x to simplify the process of preparing the plurality of active areas AA. Illustratively, in the first direction x, the spacing between adjacent active areas AA is greater than or equal to 0.05 microns and less than or equal to 0.1 microns. The width of each active area AA is greater than or equal to 0.05 microns and less than or equal to 0.2 microns.

Illustratively, the plurality of active areas AA include an active area AA1, an active area AA2, an active area AA3, an active area AA4, and the like, which are sequentially arranged at intervals along the first direction x.

As shown in fig. 2, each memory cell pair U includes a first region 10a, a second region 10b, a channel region 10c, a first gate WG, a second gate CG1, a third gate CG2, a first floating gate FG1, and a second floating gate FG2.

In the third direction w, the first region 10a and the second region 10b are connected to opposite sides of the channel region 10c, respectively. The first region 10a and the second region 10b are P-type doped regions or N-type doped regions.

The first gate electrode WG, the second gate electrode CG1, and the third gate electrode CG2 are located on one side of the channel region 10c and overlap the channel region 10c in the thickness direction z of the semiconductor layer 10. The second gate CG1 and the third gate CG2 are located on opposite sides of the first gate WG, respectively, in the extension direction of the active area AA, i.e. in the third direction w.

The first floating gate FG1 and the second floating gate FG2 are also located on one side of the channel region 10c and overlap the channel region 10 c. In the thickness direction z of the semiconductor layer 10, the first floating gate FG1 overlaps the second gate CG1 and is located between the channel region 10c and the second gate CG1, the first floating gate FG1, the second gate CG1 and the channel region 10c are insulated from each other, and the first memory cell U1 includes the first floating gate FG1 and the second gate CG1, that is, the first memory cell U1 is a memory transistor. In the thickness direction z of the semiconductor layer 10, the second floating gate FG2 overlaps the third gate CG2 and is located between the channel region 10c and the third gate CG2, the second floating gate FG2, the third gate CG2 and the channel region 10c are insulated from each other, and the second memory cell U2 includes the second floating gate FG2 and the third gate CG2, that is, the second memory cell U2 is also a memory transistor. The first memory cell U1 and the second memory cell U2 share the first gate WG, the first area 10a and the second area 10b.

As shown in fig. 1, the plurality of first control signal lines WL extend in a first direction x and are arranged at intervals in a second direction y, and the first direction x intersects the second direction y. One first control signal line WL is connected to first gates WG of a plurality of memory cell pairs U of a row of memory cell pairs U including the plurality of memory cell pairs U arranged side by side in the first direction x.

In some embodiments, the first direction x is perpendicular to the second direction y, but is not limited thereto. In some embodiments, the angle between the first direction x and the second direction y may be an obtuse angle or an acute angle.

In some embodiments, the first gate WG is a word line gate, and the first control signal line WL includes a word line selection signal line, but is not limited thereto.

In other embodiments, the first gate WG may be an erase gate, and the first control signal line WL may also include an erase gate line.

In some embodiments, the plurality of first control signal lines WL extend in a straight line shape to simplify a manufacturing process of the plurality of first control signal lines WL and simplify a process of manufacturing the memory array 100.

In some embodiments, as shown in fig. 1, the first control signal line WL intersects the active area AA, and the included angle between the first control signal line WL and the active area AA is greater than 0 degrees and less than 90 degrees, which is beneficial for the intersection of the active area AA and the bit line BL, reducing the number of wirings connecting the memory cell pair U and the bit line BL, and reducing the difficulty in manufacturing the memory array 100.

In other embodiments, the first control signal line WL intersects the active area AA, and an angle between the first control signal line WL and the active area AA is 0 degrees or 90 degrees, i.e., the first control signal line WL is parallel or perpendicular to the active area AA. Under the condition that the first control signal line WL is vertical to the active area AA, more active areas AA are arranged, and the density of the memory cell pair U is increased.

Illustratively, as shown in fig. 1, the plurality of first control signal lines WL include a first control signal line WL <0>, a first control signal line WL <1>, a first control signal line WL <2>, a first control signal line WL <3>, and the like, which are sequentially arranged in the second direction y.

As shown in fig. 1, the plurality of second control signal lines CgA extend in the first direction x and are arranged at intervals in the second direction y. One second control signal line CgA is adjacent to one first control signal line WL and is disposed at an interval. One second control signal line CgA is connected to the second gates CG1 of the plurality of memory cell pairs U of one row of memory cell pairs U, and one second control signal line CgA controls on and off of the plurality of first memory cells U1 of one row of memory cell pairs U.

In some embodiments, the plurality of second control signal lines CgA extend in a straight line shape to simplify a manufacturing process of the plurality of second control signal lines CgA, thereby simplifying a process of manufacturing the memory array 100.

Illustratively, the plurality of second control signal lines CgA includes a second control signal line CgA <0>, a second control signal line CgA <1>, a second control signal line CgA <2>, a second control signal line CgA <3>, and the like, which are sequentially arranged in the second direction y.

Wherein, in the second direction y, the second control signal line CgA <0> is disposed adjacent to the first control signal line WL <0>, and the second control signal line CgA <0> is located on a side of the first control signal line WL <0> close to the first control signal line WL <1 >. In the second direction y, the second control signal line CgA <1> is disposed adjacent to the first control signal line WL <1>, and the second control signal line CgA <1> is located on a side of the first control signal line WL <1> close to the first control signal line WL <0 >. In the second direction y, the second control signal line CgA <2> is disposed adjacent to the first control signal line WL <2>, and the second control signal line CgA <2> is located on a side of the first control signal line WL <2> away from the first control signal line WL <1 >. In the second direction y, the second control signal line CgA <3> is disposed adjacent to the first control signal line WL <3>, and the second control signal line CgA <3> is located on a side of the first control signal line WL <3> close to the first control signal line WL <2 >.

As shown in fig. 1, a plurality of third control signal lines CgB extend in the first direction x and are arranged at intervals in the second direction y. In the second direction y, one third control signal line CgB is adjacent to and spaced apart from one first control signal line WL. One third control signal line CgB is connected to the third gates CG2 of the plurality of memory cell pairs U of one row of memory cell pairs U, and the corresponding one third control signal line CgB controls the turning on and off of the plurality of second memory cells U2 of one row of memory cell pairs U.

In some embodiments, the plurality of third control signal lines CgB extend in a straight line to simplify the manufacturing process of the plurality of third control signal lines CgB, thereby simplifying the process of manufacturing the memory array 100.

Illustratively, the plurality of third control signal lines CgB includes a third control signal line CgB <0>, a third control signal line CgB <1>, a third control signal line CgB <2>, and a third control signal line CgB <3> sequentially arranged in the second direction y.

Wherein, the third control signal line CgB <0> is disposed adjacent to the first control signal line WL <0>, and the third control signal line CgB <0> is located at a side of the first control signal line WL <0> away from the first control signal line WL <1 >. The third control signal line CgB <1> is provided adjacent to the first control signal line WL <1>, and the third control signal line CgB <1> is located on a side of the first control signal line WL <1> close to the first control signal line WL <2 >. The third control signal line CgB <2> is disposed adjacent to the first control signal line WL <2>, and the third control signal line CgB <2> is located on a side of the first control signal line WL <2> away from the first control signal line WL <3>. The third control signal line CgB <3> is disposed adjacent to the first control signal line WL <3>, and the third control signal line CgB <3> is located on a side of the first control signal line WL <3> away from the first control signal line WL <2 >.

Adjacent one third control signal line CgB, one second control signal line CgA, and one first control signal line WL constitute one control signal line group K, and a plurality of control signal line groups K are arranged at intervals along the second direction y. In one, one third control signal line CgB and one second control signal line CgA are located on opposite sides of one first control signal line WL, respectively, in the second direction y.

Illustratively, the spacing d between adjacent two control signal line groups K is greater than or equal to 0.1 microns and less than or equal to 0.4 microns. In addition, a dimension c occupied by one control signal line group K in the second direction y is greater than 0.1 micrometers and less than or equal to 0.4 micrometers.

As shown in fig. 1, a plurality of bit lines BL are arranged at intervals along a first direction x, and one memory cell pair U is connected to two adjacent bit lines BL. Accordingly, two bit lines BL and one first control signal line WL can be controlled to realize a selected operation of one memory cell pair U. In addition, one memory cell pair U is connected to two bit lines BL, so that the ground terminal of each memory cell pair U can be omitted, the layout space of the memory cell pairs U can be further increased, and the density of the memory cell pairs U in the memory array 100 can be improved.

Two adjacent pairs of memory cells U in the first direction x share a bit line BL. Illustratively, a pair of memory cells U connected to the first control signal line WL <0>, the bit line BL0, and the bit line BL1, and a pair of memory cells U connected to the first control signal line WL <0>, the bit line BL1, and the bit line BL1 are adjacently disposed in the first direction x and share the bit line BL1.

Under the condition that a plurality of bit lines BL and a plurality of active areas AA are arranged along the first direction x, one bit line BL overlaps with two adjacent active areas AA and an isolation area GA between the two adjacent active areas AA, which is beneficial to removing an extra conductive layer needed for connecting a memory cell pair U and the bit line BL in the related technology, and further simplifying the preparation process of the memory array. Moreover, one bit line BL overlaps two adjacent active areas AA and the isolation area GA between the two adjacent active areas AA, so that the space in the first direction x can be more fully utilized, more active areas AA and bit lines BL are arranged, and the density of the memory cell pairs U of the memory array 100 is increased.

Referring to fig. 1 and 2, a plurality of contacts CT are located at the intersection of the active area AA and the bit line BL, wherein one portion of the contacts CT has opposite ends contacting the first region 10a and the bit line BL, and the other portion of contacts CT has opposite ends contacting the second region 10b and the bit line BL. Thus, one memory cell pair U is connected to two bit lines BL through two contacts CT without the need for additional conductive layers.

Illustratively, the plurality of bit lines BL include bit lines BL0, BL1, BL2, BL3, BL4, and the like, which are sequentially arranged at intervals in the first direction x. The bit line BL1 overlaps the active area AA1, the active area AA2, and the isolation area GA between the active area AA1 and the active area AA 2. The bit line BL2 overlaps the active area AA2, the active area AA3, and the isolation area GA between the active area AA2 and the active area AA 3. The bit line BL3 overlaps the active area AA3, the active area AA4, and the isolation area GA between the active area AA3 and the active area AA 4.

Illustratively, the first contact CT1 has two ends in contact with the first region 10a and the bit line BL3, respectively, and the second contact CT2 has two opposite ends in contact with the second region 10b and the bit line BL4, respectively.

It should be noted that, in some related art, when one memory cell pair is connected to two bit lines, in addition to the plurality of contacts that are respectively in contact with the source region and the drain region of the memory cell pair, an additional conductive layer is required to connect the plurality of contacts and the bit lines, that is, the contacts are connected to the bit lines through the additional conductive layer, which results in an increase in difficulty in manufacturing the memory array.

In some embodiments, in the case where the plurality of active regions AA extend in a straight line shape, at least part of the bit line BL extends in a zigzag shape so as to achieve overlapping of one bit line BL with two adjacent active regions AA and the isolation region GA between the two adjacent active regions AA.

In some embodiments, in the case where at least a portion of the bit line BL extends in a zigzag shape, the bit line BL includes a plurality of straight line segments so as to simplify a manufacturing process of the plurality of bit lines BL while the bit line BL intersects the active region AA. In some embodiments, the bit line BL may also include an arc segment in the case where at least a portion of the bit line BL extends in a zigzag shape.

In some embodiments, as shown in fig. 1, one bit line BL includes a first line segment BLD1 and a second line segment BLD2 connected to each other, and the first line segment BLD1 and the second line segment BLD2 each extend in a straight line shape. In a direction intersecting the first direction x, the plurality of first line segments BLD1 and the plurality of second line segments BLD2 are alternately connected in a one-to-one manner. The extending direction P1 of the first line segment BLD1 intersects the extending direction P2 of the second line segment BLD2, and the first line segment BLD1 and the second line segment BLD2 each intersect two adjacent active areas AA and an isolation area GA between the two adjacent active areas AA. In the second direction y, opposite ends of the first line segment BLD1 are respectively located at opposite sides of one control signal line group K, and opposite ends of the second line segment BLD1 are respectively located at opposite sides of the other control signal line group K. The first and second line segments BLD1 and BLD2 have an angle greater than 0 degrees and less than 90 degrees with the first control signal line WL.

In other embodiments, the bit line BL may further include a third line segment (not shown) connected to at least one of the first line segment BLD1 and the second line segment BLD2, the third line segment overlapping and parallel with the active area AA, and the third line segment being a straight line segment. By this design, the designs of the first line segment BLD1 and the second line segment BLD2 can be more adjustable.

In some embodiments, the memory array 100 also includes a redundant active area DAA. In the first direction x, the redundant active area DAA is located at least on one side of the plurality of active areas AA, and an isolation area GA is disposed between the redundant active area DAA and the adjacent active areas AA, so as to improve the process yield of the plurality of active areas AA and improve the performance of the memory array 100.

Referring to fig. 1 and 3, the redundant active area DAA is provided with a pair of redundant storage units DU, and a plurality of serially connected pairs of redundant storage units DU form a redundant storage string DuS, and the pairs of redundant storage units DU are not used for storing data.

It should be noted that, as shown in fig. 3, a plurality of memory cell pairs U of one active area AA are connected in series to form a memory string, and the plurality of memory cell pairs U are used for storing data.

In some embodiments, one redundant active area DAA is provided at one side of the plurality of active areas AA in the first direction x. One BL bit line overlaps one redundant active area DAA, one active area AA adjacent to the redundant active area DAA, and an isolation area GA between the redundant active area DAA and the active area AA.

Illustratively, the bit line BL0 intersects one of the redundant active areas DAA, the active area AA1, and the isolation area GA between the redundant active area DAA and the active area AA 1.

In other embodiments, in the first direction x, the plurality of active areas AA are located between two redundant active areas DAA.

In some embodiments, the shape and size of the redundant active area DAA are the same as the shape and size of the active area AA, so that the redundant active area DAA and the active area AA are manufactured by the same process, which simplifies the manufacturing difficulty of the memory array 100.

In some embodiments of the present application, one bit line BL overlaps two adjacent active regions AA and an isolation region GA between the two adjacent active regions AA, which is advantageous for removing an additional conductive layer required for connecting the memory cell pair U and the bit line BL in the related art, thereby simplifying the fabrication process of the memory array. In addition, in the case where the plurality of bit lines BL and the plurality of active regions AA are arranged along the first direction x, one bit line BL overlaps with two adjacent active regions AA and the isolation region GA between two adjacent active regions AA, so that the space in the first direction x can be more fully utilized, more active regions AA and bit lines BL can be arranged, and the density of the memory cell pairs U of the memory array 100 can be increased.

Referring to fig. 4 to 6, fig. 4 is a schematic structural diagram of a memory array according to other embodiments of the present application, fig. 5 is a schematic sectional structural diagram taken along a line Z2-Z2 shown in fig. 4, and fig. 6 is a schematic circuit diagram of the memory array shown in fig. 4.

The memory array 100 shown in fig. 4 is substantially similar to the memory array 100 shown in fig. 1, and the differences are that one bit line BL overlaps one active area AA, and the memory array 100 further includes a plurality of connection lines CL. One end of the connection line CL is connected to one of the adjacent two bit lines BL, and the other end of the connection line CL is disconnected from the other of the adjacent two bit lines BL. Opposite ends of one portion of the contact CT are respectively in contact with one end of the connection line CT and the first region 10a, and opposite ends of the other portion of the contact CT are respectively in contact with the other end of the connection line CL and the second region 10b.

For example, referring to fig. 4 and 5, the bit line BL0 overlaps the active area AA0, the bit line BL1 overlaps the active area AA1, the bit line BL2 overlaps the active area AA2, the bit line BL3 overlaps the active area AA3, and the bit line BL4 overlaps the active area AA 4. One end of the connection line CL is connected to the bit line BL3, and the other end of the connection line CL is disconnected from the bit line BL 2. Opposite ends of the second contact CT2 are respectively in contact with one end of the connection line CT and the first region 10a, and opposite ends of the first contact CT1 are respectively in contact with the other end of the connection line CT and the second region 10b.

In other embodiments of the present application, one bit line BL overlaps one active area AA, so that the number of connection lines CL connecting the memory cell pairs U and the two bit lines BL can be reduced, thereby simplifying the manufacturing difficulty of the memory array 100. Moreover, one bit line BL overlaps one active area AA, which is also advantageous for more active areas AA to be laid out, and the density of memory cell pairs U in the memory array 100 is increased.

In other embodiments, the bit lines BL and the active areas AA extend in a straight line in the third direction w, so as to simplify the manufacturing process of the bit lines BL and the active areas AA.

In other embodiments, at least part of the bit line BL and at least part of the active area AA may also extend in a zigzag shape.

In other embodiments, as shown in fig. 4, the angle between the bit line BL and the first control signal line WL may be greater than 0 degrees and less than 90 degrees. For example, the included angle between the bit line BL and the first control signal line WL is 10 degrees, 15 degrees, 20 degrees, 25 degrees, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, or 85 degrees.

In other embodiments, the bit line BL and the first control signal line WL may be perpendicular to each other.

In other embodiments, a plurality of connection lines CL are disposed in a region between two adjacent control signal line groups K, and the connection lines CL extend along the first direction x. One connection line CL overlaps with the isolation regions GA between the adjacent two active regions AA.

In other embodiments, the memory array 100 further includes a third conductive layer 13, the third conductive layer 13 including a plurality of connection lines CL. In the thickness direction z of the semiconductor layer 10, the third conductive layer 13 is located between the semiconductor layer 10 and the second conductive layer 12, and the plurality of contacts CT are located between the third conductive layer 13 and the semiconductor layer 10.

Referring to fig. 7, the present application further provides a memory 200, where the memory 200 is a nonvolatile memory. Memory 200 includes memory array 100 of any of the embodiments described above and peripheral circuitry (not shown) coupled to memory array 100.

The above description of the embodiments is only for helping to understand the technical solution of the present application and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory array, comprising:

a plurality of bit lines arranged at intervals;

2. The memory array of claim 1, wherein one of the bit lines overlaps two adjacent ones of the active regions and the isolation region between the two adjacent ones of the active regions, at least a portion of the bit lines extending in a zigzag shape.

3. The memory array of claim 2, wherein one of the bit lines includes a first line segment and a second line segment connected to each other, an extension direction of the first line segment intersecting an extension direction of the second line segment, the first line segment and the second line segment each intersecting two adjacent active regions and the isolation region between the two adjacent active regions.

4. The memory array of claim 2, wherein the memory array further comprises: and a plurality of contacts positioned at the positions where the active areas and the bit lines intersect, wherein one part of the contacts are respectively contacted with the first areas and the bit lines at opposite ends, and the other part of the contacts are respectively contacted with the second areas and the bit lines at opposite ends.

5. The memory array of claim 2, wherein the memory array further comprises: and the redundant active areas are positioned on at least one side of the plurality of active areas, and one bit line overlaps one redundant active area, one active area adjacent to the redundant active area and an isolation area between the redundant active areas and the active areas.

6. The memory array of claim 1, wherein one of the bit lines overlaps one of the active regions;

7. The memory array of claim 6, wherein the bit lines extend in a straight line.

8. The memory array of any of claims 1-7, wherein the active region extends in a straight line.

9. The memory array of any of claims 1-7, wherein the pair of memory cells further comprises a first gate, a second gate, and a third gate on one side of the channel region and overlapping the channel region, the first gate being shared by two of the memory cells of the pair of memory cells;

the memory array further includes:

a plurality of second control signal lines connected to the second gates of the pair of memory cells; and

and a plurality of third control signal lines connected to the third gates of the pair of memory cells.

10. The memory array of claim 9, wherein the memory array comprises:

a semiconductor layer including a plurality of the active regions; and

11. The memory array of claim 9, wherein the first control signal line intersects the active region and an angle between the first control signal line and the active region is greater than 0 degrees and less than 90 degrees.

12. A memory comprising the memory array of any of claims 1-11.